tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull late arm64 fixes from Will Deacon:
"Three small arm64 fixes for 5.0.

They fix a build breakage with clang introduced in 4.20, an oversight
in our sigframe restoration relating to the SSBS bit and a boot fix
for systems with newer revisions of our interrupt controller.

Summary:

- Fix handling of PSTATE.SSBS bit in sigreturn()

- Fix version checking of the GIC during early boot

- Fix clang builds failing due to use of NEON in the crypto code"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: Relax GIC version check during early boot
arm64/neon: Disable -Wincompatible-pointer-types when building with Clang
arm64: fix SSBS sanitization

Linus Torvalds d6622d91 7c903253

+13 -9
+4
arch/arm64/include/asm/neon-intrinsics.h
··· 36 36 #include <arm_neon.h> 37 37 #endif 38 38 39 + #ifdef CONFIG_CC_IS_CLANG 40 + #pragma clang diagnostic ignored "-Wincompatible-pointer-types" 41 + #endif 42 + 39 43 #endif /* __ASM_NEON_INTRINSICS_H */
+1 -2
arch/arm64/kernel/head.S
··· 539 539 /* GICv3 system register access */ 540 540 mrs x0, id_aa64pfr0_el1 541 541 ubfx x0, x0, #24, #4 542 - cmp x0, #1 543 - b.ne 3f 542 + cbz x0, 3f 544 543 545 544 mrs_s x0, SYS_ICC_SRE_EL2 546 545 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
+8 -7
arch/arm64/kernel/ptrace.c
··· 1702 1702 } 1703 1703 1704 1704 /* 1705 - * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487C.a 1706 - * We also take into account DIT (bit 24), which is not yet documented, and 1707 - * treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may be 1708 - * allocated an EL0 meaning in future. 1705 + * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a. 1706 + * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which is 1707 + * not described in ARM DDI 0487D.a. 1708 + * We treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may 1709 + * be allocated an EL0 meaning in future. 1709 1710 * Userspace cannot use these until they have an architectural meaning. 1710 1711 * Note that this follows the SPSR_ELx format, not the AArch32 PSR format. 1711 1712 * We also reserve IL for the kernel; SS is handled dynamically. 1712 1713 */ 1713 1714 #define SPSR_EL1_AARCH64_RES0_BITS \ 1714 - (GENMASK_ULL(63,32) | GENMASK_ULL(27, 25) | GENMASK_ULL(23, 22) | \ 1715 - GENMASK_ULL(20, 10) | GENMASK_ULL(5, 5)) 1715 + (GENMASK_ULL(63, 32) | GENMASK_ULL(27, 25) | GENMASK_ULL(23, 22) | \ 1716 + GENMASK_ULL(20, 13) | GENMASK_ULL(11, 10) | GENMASK_ULL(5, 5)) 1716 1717 #define SPSR_EL1_AARCH32_RES0_BITS \ 1717 - (GENMASK_ULL(63,32) | GENMASK_ULL(23, 22) | GENMASK_ULL(20,20)) 1718 + (GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20)) 1718 1719 1719 1720 static int valid_compat_regs(struct user_pt_regs *regs) 1720 1721 {