Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf vendor events: Add nehalemex counter information
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-26-irogers@google.com
authored by
Ian Rogers
Weilin Wang
Caleb Biggers
and committed by
Namhyung Kim
d6977722
af557589
+560
+315
tools/perf/pmu-events/arch/x86/nehalemex/cache.json
+315
tools/perf/pmu-events/arch/x86/nehalemex/cache.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles L1D locked",
4
+
"Counter": "0,1",
4
5
"EventCode": "0x63",
5
6
"EventName": "CACHE_LOCK_CYCLES.L1D",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Cycles L1D and L2 locked",
11
+
"Counter": "0,1",
12
12
"EventCode": "0x63",
13
13
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "L1D cache lines replaced in M state",
18
+
"Counter": "0,1",
20
19
"EventCode": "0x51",
21
20
"EventName": "L1D.M_EVICT",
22
21
"SampleAfterValue": "2000000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "L1D cache lines allocated in the M state",
25
+
"Counter": "0,1",
28
26
"EventCode": "0x51",
29
27
"EventName": "L1D.M_REPL",
30
28
"SampleAfterValue": "2000000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "L1D snoop eviction of cache lines in M state",
32
+
"Counter": "0,1",
36
33
"EventCode": "0x51",
37
34
"EventName": "L1D.M_SNOOP_EVICT",
38
35
"SampleAfterValue": "2000000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "L1 data cache lines allocated",
39
+
"Counter": "0,1",
44
40
"EventCode": "0x51",
45
41
"EventName": "L1D.REPL",
46
42
"SampleAfterValue": "2000000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "All references to the L1 data cache",
46
+
"Counter": "0,1",
52
47
"EventCode": "0x43",
53
48
"EventName": "L1D_ALL_REF.ANY",
54
49
"SampleAfterValue": "2000000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "L1 data cacheable reads and writes",
53
+
"Counter": "0,1",
60
54
"EventCode": "0x43",
61
55
"EventName": "L1D_ALL_REF.CACHEABLE",
62
56
"SampleAfterValue": "2000000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "L1 data cache read in E state",
60
+
"Counter": "0,1",
68
61
"EventCode": "0x40",
69
62
"EventName": "L1D_CACHE_LD.E_STATE",
70
63
"SampleAfterValue": "2000000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "L1 data cache read in I state (misses)",
67
+
"Counter": "0,1",
76
68
"EventCode": "0x40",
77
69
"EventName": "L1D_CACHE_LD.I_STATE",
78
70
"SampleAfterValue": "2000000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "L1 data cache reads",
74
+
"Counter": "0,1",
84
75
"EventCode": "0x40",
85
76
"EventName": "L1D_CACHE_LD.MESI",
86
77
"SampleAfterValue": "2000000",
···
89
78
},
90
79
{
91
80
"BriefDescription": "L1 data cache read in M state",
81
+
"Counter": "0,1",
92
82
"EventCode": "0x40",
93
83
"EventName": "L1D_CACHE_LD.M_STATE",
94
84
"SampleAfterValue": "2000000",
···
97
85
},
98
86
{
99
87
"BriefDescription": "L1 data cache read in S state",
88
+
"Counter": "0,1",
100
89
"EventCode": "0x40",
101
90
"EventName": "L1D_CACHE_LD.S_STATE",
102
91
"SampleAfterValue": "2000000",
···
105
92
},
106
93
{
107
94
"BriefDescription": "L1 data cache load locks in E state",
95
+
"Counter": "0,1",
108
96
"EventCode": "0x42",
109
97
"EventName": "L1D_CACHE_LOCK.E_STATE",
110
98
"SampleAfterValue": "2000000",
···
113
99
},
114
100
{
115
101
"BriefDescription": "L1 data cache load lock hits",
102
+
"Counter": "0,1",
116
103
"EventCode": "0x42",
117
104
"EventName": "L1D_CACHE_LOCK.HIT",
118
105
"SampleAfterValue": "2000000",
···
121
106
},
122
107
{
123
108
"BriefDescription": "L1 data cache load locks in M state",
109
+
"Counter": "0,1",
124
110
"EventCode": "0x42",
125
111
"EventName": "L1D_CACHE_LOCK.M_STATE",
126
112
"SampleAfterValue": "2000000",
···
129
113
},
130
114
{
131
115
"BriefDescription": "L1 data cache load locks in S state",
116
+
"Counter": "0,1",
132
117
"EventCode": "0x42",
133
118
"EventName": "L1D_CACHE_LOCK.S_STATE",
134
119
"SampleAfterValue": "2000000",
···
137
120
},
138
121
{
139
122
"BriefDescription": "L1D load lock accepted in fill buffer",
123
+
"Counter": "0,1",
140
124
"EventCode": "0x53",
141
125
"EventName": "L1D_CACHE_LOCK_FB_HIT",
142
126
"SampleAfterValue": "2000000",
···
145
127
},
146
128
{
147
129
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
130
+
"Counter": "0,1",
148
131
"EventCode": "0x52",
149
132
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
150
133
"SampleAfterValue": "2000000",
···
153
134
},
154
135
{
155
136
"BriefDescription": "L1 data cache stores in E state",
137
+
"Counter": "0,1",
156
138
"EventCode": "0x41",
157
139
"EventName": "L1D_CACHE_ST.E_STATE",
158
140
"SampleAfterValue": "2000000",
···
161
141
},
162
142
{
163
143
"BriefDescription": "L1 data cache stores in M state",
144
+
"Counter": "0,1",
164
145
"EventCode": "0x41",
165
146
"EventName": "L1D_CACHE_ST.M_STATE",
166
147
"SampleAfterValue": "2000000",
···
169
148
},
170
149
{
171
150
"BriefDescription": "L1 data cache stores in S state",
151
+
"Counter": "0,1",
172
152
"EventCode": "0x41",
173
153
"EventName": "L1D_CACHE_ST.S_STATE",
174
154
"SampleAfterValue": "2000000",
···
177
155
},
178
156
{
179
157
"BriefDescription": "L1D hardware prefetch misses",
158
+
"Counter": "0,1",
180
159
"EventCode": "0x4E",
181
160
"EventName": "L1D_PREFETCH.MISS",
182
161
"SampleAfterValue": "200000",
···
185
162
},
186
163
{
187
164
"BriefDescription": "L1D hardware prefetch requests",
165
+
"Counter": "0,1",
188
166
"EventCode": "0x4E",
189
167
"EventName": "L1D_PREFETCH.REQUESTS",
190
168
"SampleAfterValue": "200000",
···
193
169
},
194
170
{
195
171
"BriefDescription": "L1D hardware prefetch requests triggered",
172
+
"Counter": "0,1",
196
173
"EventCode": "0x4E",
197
174
"EventName": "L1D_PREFETCH.TRIGGERS",
198
175
"SampleAfterValue": "200000",
···
201
176
},
202
177
{
203
178
"BriefDescription": "L1 writebacks to L2 in E state",
179
+
"Counter": "0,1,2,3",
204
180
"EventCode": "0x28",
205
181
"EventName": "L1D_WB_L2.E_STATE",
206
182
"SampleAfterValue": "100000",
···
209
183
},
210
184
{
211
185
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
186
+
"Counter": "0,1,2,3",
212
187
"EventCode": "0x28",
213
188
"EventName": "L1D_WB_L2.I_STATE",
214
189
"SampleAfterValue": "100000",
···
217
190
},
218
191
{
219
192
"BriefDescription": "All L1 writebacks to L2",
193
+
"Counter": "0,1,2,3",
220
194
"EventCode": "0x28",
221
195
"EventName": "L1D_WB_L2.MESI",
222
196
"SampleAfterValue": "100000",
···
225
197
},
226
198
{
227
199
"BriefDescription": "L1 writebacks to L2 in M state",
200
+
"Counter": "0,1,2,3",
228
201
"EventCode": "0x28",
229
202
"EventName": "L1D_WB_L2.M_STATE",
230
203
"SampleAfterValue": "100000",
···
233
204
},
234
205
{
235
206
"BriefDescription": "L1 writebacks to L2 in S state",
207
+
"Counter": "0,1,2,3",
236
208
"EventCode": "0x28",
237
209
"EventName": "L1D_WB_L2.S_STATE",
238
210
"SampleAfterValue": "100000",
···
241
211
},
242
212
{
243
213
"BriefDescription": "All L2 data requests",
214
+
"Counter": "0,1,2,3",
244
215
"EventCode": "0x26",
245
216
"EventName": "L2_DATA_RQSTS.ANY",
246
217
"SampleAfterValue": "200000",
···
249
218
},
250
219
{
251
220
"BriefDescription": "L2 data demand loads in E state",
221
+
"Counter": "0,1,2,3",
252
222
"EventCode": "0x26",
253
223
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
254
224
"SampleAfterValue": "200000",
···
257
225
},
258
226
{
259
227
"BriefDescription": "L2 data demand loads in I state (misses)",
228
+
"Counter": "0,1,2,3",
260
229
"EventCode": "0x26",
261
230
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
262
231
"SampleAfterValue": "200000",
···
265
232
},
266
233
{
267
234
"BriefDescription": "L2 data demand requests",
235
+
"Counter": "0,1,2,3",
268
236
"EventCode": "0x26",
269
237
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
270
238
"SampleAfterValue": "200000",
···
273
239
},
274
240
{
275
241
"BriefDescription": "L2 data demand loads in M state",
242
+
"Counter": "0,1,2,3",
276
243
"EventCode": "0x26",
277
244
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
278
245
"SampleAfterValue": "200000",
···
281
246
},
282
247
{
283
248
"BriefDescription": "L2 data demand loads in S state",
249
+
"Counter": "0,1,2,3",
284
250
"EventCode": "0x26",
285
251
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
286
252
"SampleAfterValue": "200000",
···
289
253
},
290
254
{
291
255
"BriefDescription": "L2 data prefetches in E state",
256
+
"Counter": "0,1,2,3",
292
257
"EventCode": "0x26",
293
258
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
294
259
"SampleAfterValue": "200000",
···
297
260
},
298
261
{
299
262
"BriefDescription": "L2 data prefetches in the I state (misses)",
263
+
"Counter": "0,1,2,3",
300
264
"EventCode": "0x26",
301
265
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
302
266
"SampleAfterValue": "200000",
···
305
267
},
306
268
{
307
269
"BriefDescription": "All L2 data prefetches",
270
+
"Counter": "0,1,2,3",
308
271
"EventCode": "0x26",
309
272
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
310
273
"SampleAfterValue": "200000",
···
313
274
},
314
275
{
315
276
"BriefDescription": "L2 data prefetches in M state",
277
+
"Counter": "0,1,2,3",
316
278
"EventCode": "0x26",
317
279
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
318
280
"SampleAfterValue": "200000",
···
321
281
},
322
282
{
323
283
"BriefDescription": "L2 data prefetches in the S state",
284
+
"Counter": "0,1,2,3",
324
285
"EventCode": "0x26",
325
286
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
326
287
"SampleAfterValue": "200000",
···
329
288
},
330
289
{
331
290
"BriefDescription": "L2 lines allocated",
291
+
"Counter": "0,1,2,3",
332
292
"EventCode": "0xF1",
333
293
"EventName": "L2_LINES_IN.ANY",
334
294
"SampleAfterValue": "100000",
···
337
295
},
338
296
{
339
297
"BriefDescription": "L2 lines allocated in the E state",
298
+
"Counter": "0,1,2,3",
340
299
"EventCode": "0xF1",
341
300
"EventName": "L2_LINES_IN.E_STATE",
342
301
"SampleAfterValue": "100000",
···
345
302
},
346
303
{
347
304
"BriefDescription": "L2 lines allocated in the S state",
305
+
"Counter": "0,1,2,3",
348
306
"EventCode": "0xF1",
349
307
"EventName": "L2_LINES_IN.S_STATE",
350
308
"SampleAfterValue": "100000",
···
353
309
},
354
310
{
355
311
"BriefDescription": "L2 lines evicted",
312
+
"Counter": "0,1,2,3",
356
313
"EventCode": "0xF2",
357
314
"EventName": "L2_LINES_OUT.ANY",
358
315
"SampleAfterValue": "100000",
···
361
316
},
362
317
{
363
318
"BriefDescription": "L2 lines evicted by a demand request",
319
+
"Counter": "0,1,2,3",
364
320
"EventCode": "0xF2",
365
321
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
366
322
"SampleAfterValue": "100000",
···
369
323
},
370
324
{
371
325
"BriefDescription": "L2 modified lines evicted by a demand request",
326
+
"Counter": "0,1,2,3",
372
327
"EventCode": "0xF2",
373
328
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
374
329
"SampleAfterValue": "100000",
···
377
330
},
378
331
{
379
332
"BriefDescription": "L2 lines evicted by a prefetch request",
333
+
"Counter": "0,1,2,3",
380
334
"EventCode": "0xF2",
381
335
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
382
336
"SampleAfterValue": "100000",
···
385
337
},
386
338
{
387
339
"BriefDescription": "L2 modified lines evicted by a prefetch request",
340
+
"Counter": "0,1,2,3",
388
341
"EventCode": "0xF2",
389
342
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
390
343
"SampleAfterValue": "100000",
···
393
344
},
394
345
{
395
346
"BriefDescription": "L2 instruction fetches",
347
+
"Counter": "0,1,2,3",
396
348
"EventCode": "0x24",
397
349
"EventName": "L2_RQSTS.IFETCHES",
398
350
"SampleAfterValue": "200000",
···
401
351
},
402
352
{
403
353
"BriefDescription": "L2 instruction fetch hits",
354
+
"Counter": "0,1,2,3",
404
355
"EventCode": "0x24",
405
356
"EventName": "L2_RQSTS.IFETCH_HIT",
406
357
"SampleAfterValue": "200000",
···
409
358
},
410
359
{
411
360
"BriefDescription": "L2 instruction fetch misses",
361
+
"Counter": "0,1,2,3",
412
362
"EventCode": "0x24",
413
363
"EventName": "L2_RQSTS.IFETCH_MISS",
414
364
"SampleAfterValue": "200000",
···
417
365
},
418
366
{
419
367
"BriefDescription": "L2 load hits",
368
+
"Counter": "0,1,2,3",
420
369
"EventCode": "0x24",
421
370
"EventName": "L2_RQSTS.LD_HIT",
422
371
"SampleAfterValue": "200000",
···
425
372
},
426
373
{
427
374
"BriefDescription": "L2 load misses",
375
+
"Counter": "0,1,2,3",
428
376
"EventCode": "0x24",
429
377
"EventName": "L2_RQSTS.LD_MISS",
430
378
"SampleAfterValue": "200000",
···
433
379
},
434
380
{
435
381
"BriefDescription": "L2 requests",
382
+
"Counter": "0,1,2,3",
436
383
"EventCode": "0x24",
437
384
"EventName": "L2_RQSTS.LOADS",
438
385
"SampleAfterValue": "200000",
···
441
386
},
442
387
{
443
388
"BriefDescription": "All L2 misses",
389
+
"Counter": "0,1,2,3",
444
390
"EventCode": "0x24",
445
391
"EventName": "L2_RQSTS.MISS",
446
392
"SampleAfterValue": "200000",
···
449
393
},
450
394
{
451
395
"BriefDescription": "All L2 prefetches",
396
+
"Counter": "0,1,2,3",
452
397
"EventCode": "0x24",
453
398
"EventName": "L2_RQSTS.PREFETCHES",
454
399
"SampleAfterValue": "200000",
···
457
400
},
458
401
{
459
402
"BriefDescription": "L2 prefetch hits",
403
+
"Counter": "0,1,2,3",
460
404
"EventCode": "0x24",
461
405
"EventName": "L2_RQSTS.PREFETCH_HIT",
462
406
"SampleAfterValue": "200000",
···
465
407
},
466
408
{
467
409
"BriefDescription": "L2 prefetch misses",
410
+
"Counter": "0,1,2,3",
468
411
"EventCode": "0x24",
469
412
"EventName": "L2_RQSTS.PREFETCH_MISS",
470
413
"SampleAfterValue": "200000",
···
473
414
},
474
415
{
475
416
"BriefDescription": "All L2 requests",
417
+
"Counter": "0,1,2,3",
476
418
"EventCode": "0x24",
477
419
"EventName": "L2_RQSTS.REFERENCES",
478
420
"SampleAfterValue": "200000",
···
481
421
},
482
422
{
483
423
"BriefDescription": "L2 RFO requests",
424
+
"Counter": "0,1,2,3",
484
425
"EventCode": "0x24",
485
426
"EventName": "L2_RQSTS.RFOS",
486
427
"SampleAfterValue": "200000",
···
489
428
},
490
429
{
491
430
"BriefDescription": "L2 RFO hits",
431
+
"Counter": "0,1,2,3",
492
432
"EventCode": "0x24",
493
433
"EventName": "L2_RQSTS.RFO_HIT",
494
434
"SampleAfterValue": "200000",
···
497
435
},
498
436
{
499
437
"BriefDescription": "L2 RFO misses",
438
+
"Counter": "0,1,2,3",
500
439
"EventCode": "0x24",
501
440
"EventName": "L2_RQSTS.RFO_MISS",
502
441
"SampleAfterValue": "200000",
···
505
442
},
506
443
{
507
444
"BriefDescription": "All L2 transactions",
445
+
"Counter": "0,1,2,3",
508
446
"EventCode": "0xF0",
509
447
"EventName": "L2_TRANSACTIONS.ANY",
510
448
"SampleAfterValue": "200000",
···
513
449
},
514
450
{
515
451
"BriefDescription": "L2 fill transactions",
452
+
"Counter": "0,1,2,3",
516
453
"EventCode": "0xF0",
517
454
"EventName": "L2_TRANSACTIONS.FILL",
518
455
"SampleAfterValue": "200000",
···
521
456
},
522
457
{
523
458
"BriefDescription": "L2 instruction fetch transactions",
459
+
"Counter": "0,1,2,3",
524
460
"EventCode": "0xF0",
525
461
"EventName": "L2_TRANSACTIONS.IFETCH",
526
462
"SampleAfterValue": "200000",
···
529
463
},
530
464
{
531
465
"BriefDescription": "L1D writeback to L2 transactions",
466
+
"Counter": "0,1,2,3",
532
467
"EventCode": "0xF0",
533
468
"EventName": "L2_TRANSACTIONS.L1D_WB",
534
469
"SampleAfterValue": "200000",
···
537
470
},
538
471
{
539
472
"BriefDescription": "L2 Load transactions",
473
+
"Counter": "0,1,2,3",
540
474
"EventCode": "0xF0",
541
475
"EventName": "L2_TRANSACTIONS.LOAD",
542
476
"SampleAfterValue": "200000",
···
545
477
},
546
478
{
547
479
"BriefDescription": "L2 prefetch transactions",
480
+
"Counter": "0,1,2,3",
548
481
"EventCode": "0xF0",
549
482
"EventName": "L2_TRANSACTIONS.PREFETCH",
550
483
"SampleAfterValue": "200000",
···
553
484
},
554
485
{
555
486
"BriefDescription": "L2 RFO transactions",
487
+
"Counter": "0,1,2,3",
556
488
"EventCode": "0xF0",
557
489
"EventName": "L2_TRANSACTIONS.RFO",
558
490
"SampleAfterValue": "200000",
···
561
491
},
562
492
{
563
493
"BriefDescription": "L2 writeback to LLC transactions",
494
+
"Counter": "0,1,2,3",
564
495
"EventCode": "0xF0",
565
496
"EventName": "L2_TRANSACTIONS.WB",
566
497
"SampleAfterValue": "200000",
···
569
498
},
570
499
{
571
500
"BriefDescription": "L2 demand lock RFOs in E state",
501
+
"Counter": "0,1,2,3",
572
502
"EventCode": "0x27",
573
503
"EventName": "L2_WRITE.LOCK.E_STATE",
574
504
"SampleAfterValue": "100000",
···
577
505
},
578
506
{
579
507
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
508
+
"Counter": "0,1,2,3",
580
509
"EventCode": "0x27",
581
510
"EventName": "L2_WRITE.LOCK.HIT",
582
511
"SampleAfterValue": "100000",
···
585
512
},
586
513
{
587
514
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
515
+
"Counter": "0,1,2,3",
588
516
"EventCode": "0x27",
589
517
"EventName": "L2_WRITE.LOCK.I_STATE",
590
518
"SampleAfterValue": "100000",
···
593
519
},
594
520
{
595
521
"BriefDescription": "All demand L2 lock RFOs",
522
+
"Counter": "0,1,2,3",
596
523
"EventCode": "0x27",
597
524
"EventName": "L2_WRITE.LOCK.MESI",
598
525
"SampleAfterValue": "100000",
···
601
526
},
602
527
{
603
528
"BriefDescription": "L2 demand lock RFOs in M state",
529
+
"Counter": "0,1,2,3",
604
530
"EventCode": "0x27",
605
531
"EventName": "L2_WRITE.LOCK.M_STATE",
606
532
"SampleAfterValue": "100000",
···
609
533
},
610
534
{
611
535
"BriefDescription": "L2 demand lock RFOs in S state",
536
+
"Counter": "0,1,2,3",
612
537
"EventCode": "0x27",
613
538
"EventName": "L2_WRITE.LOCK.S_STATE",
614
539
"SampleAfterValue": "100000",
···
617
540
},
618
541
{
619
542
"BriefDescription": "All L2 demand store RFOs that hit the cache",
543
+
"Counter": "0,1,2,3",
620
544
"EventCode": "0x27",
621
545
"EventName": "L2_WRITE.RFO.HIT",
622
546
"SampleAfterValue": "100000",
···
625
547
},
626
548
{
627
549
"BriefDescription": "L2 demand store RFOs in I state (misses)",
550
+
"Counter": "0,1,2,3",
628
551
"EventCode": "0x27",
629
552
"EventName": "L2_WRITE.RFO.I_STATE",
630
553
"SampleAfterValue": "100000",
···
633
554
},
634
555
{
635
556
"BriefDescription": "All L2 demand store RFOs",
557
+
"Counter": "0,1,2,3",
636
558
"EventCode": "0x27",
637
559
"EventName": "L2_WRITE.RFO.MESI",
638
560
"SampleAfterValue": "100000",
···
641
561
},
642
562
{
643
563
"BriefDescription": "L2 demand store RFOs in M state",
564
+
"Counter": "0,1,2,3",
644
565
"EventCode": "0x27",
645
566
"EventName": "L2_WRITE.RFO.M_STATE",
646
567
"SampleAfterValue": "100000",
···
649
568
},
650
569
{
651
570
"BriefDescription": "L2 demand store RFOs in S state",
571
+
"Counter": "0,1,2,3",
652
572
"EventCode": "0x27",
653
573
"EventName": "L2_WRITE.RFO.S_STATE",
654
574
"SampleAfterValue": "100000",
···
657
575
},
658
576
{
659
577
"BriefDescription": "Longest latency cache miss",
578
+
"Counter": "0,1,2,3",
660
579
"EventCode": "0x2E",
661
580
"EventName": "LONGEST_LAT_CACHE.MISS",
662
581
"SampleAfterValue": "100000",
···
665
582
},
666
583
{
667
584
"BriefDescription": "Longest latency cache reference",
585
+
"Counter": "0,1,2,3",
668
586
"EventCode": "0x2E",
669
587
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
670
588
"SampleAfterValue": "200000",
···
673
589
},
674
590
{
675
591
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
592
+
"Counter": "3",
676
593
"EventCode": "0xB",
677
594
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
678
595
"MSRIndex": "0x3F6",
···
683
598
},
684
599
{
685
600
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
601
+
"Counter": "3",
686
602
"EventCode": "0xB",
687
603
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
688
604
"MSRIndex": "0x3F6",
···
694
608
},
695
609
{
696
610
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
611
+
"Counter": "3",
697
612
"EventCode": "0xB",
698
613
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
699
614
"MSRIndex": "0x3F6",
···
705
618
},
706
619
{
707
620
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
621
+
"Counter": "3",
708
622
"EventCode": "0xB",
709
623
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
710
624
"MSRIndex": "0x3F6",
···
716
628
},
717
629
{
718
630
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
631
+
"Counter": "3",
719
632
"EventCode": "0xB",
720
633
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
721
634
"MSRIndex": "0x3F6",
···
727
638
},
728
639
{
729
640
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
641
+
"Counter": "3",
730
642
"EventCode": "0xB",
731
643
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
732
644
"MSRIndex": "0x3F6",
···
738
648
},
739
649
{
740
650
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
651
+
"Counter": "3",
741
652
"EventCode": "0xB",
742
653
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
743
654
"MSRIndex": "0x3F6",
···
749
658
},
750
659
{
751
660
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
661
+
"Counter": "3",
752
662
"EventCode": "0xB",
753
663
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
754
664
"MSRIndex": "0x3F6",
···
760
668
},
761
669
{
762
670
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
671
+
"Counter": "3",
763
672
"EventCode": "0xB",
764
673
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
765
674
"MSRIndex": "0x3F6",
···
771
678
},
772
679
{
773
680
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
681
+
"Counter": "3",
774
682
"EventCode": "0xB",
775
683
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
776
684
"MSRIndex": "0x3F6",
···
782
688
},
783
689
{
784
690
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
691
+
"Counter": "3",
785
692
"EventCode": "0xB",
786
693
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
787
694
"MSRIndex": "0x3F6",
···
793
698
},
794
699
{
795
700
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
701
+
"Counter": "3",
796
702
"EventCode": "0xB",
797
703
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
798
704
"MSRIndex": "0x3F6",
···
804
708
},
805
709
{
806
710
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
711
+
"Counter": "3",
807
712
"EventCode": "0xB",
808
713
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
809
714
"MSRIndex": "0x3F6",
···
815
718
},
816
719
{
817
720
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
721
+
"Counter": "3",
818
722
"EventCode": "0xB",
819
723
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
820
724
"MSRIndex": "0x3F6",
···
826
728
},
827
729
{
828
730
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
731
+
"Counter": "3",
829
732
"EventCode": "0xB",
830
733
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
831
734
"MSRIndex": "0x3F6",
···
837
738
},
838
739
{
839
740
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
741
+
"Counter": "0,1,2,3",
840
742
"EventCode": "0xB",
841
743
"EventName": "MEM_INST_RETIRED.LOADS",
842
744
"PEBS": "1",
···
846
746
},
847
747
{
848
748
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
749
+
"Counter": "0,1,2,3",
849
750
"EventCode": "0xB",
850
751
"EventName": "MEM_INST_RETIRED.STORES",
851
752
"PEBS": "1",
···
855
754
},
856
755
{
857
756
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
757
+
"Counter": "0,1,2,3",
858
758
"EventCode": "0xCB",
859
759
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
860
760
"PEBS": "1",
···
864
762
},
865
763
{
866
764
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
765
+
"Counter": "0,1,2,3",
867
766
"EventCode": "0xCB",
868
767
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
869
768
"PEBS": "1",
···
873
770
},
874
771
{
875
772
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
773
+
"Counter": "0,1,2,3",
876
774
"EventCode": "0xCB",
877
775
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
878
776
"PEBS": "1",
···
882
778
},
883
779
{
884
780
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
781
+
"Counter": "0,1,2,3",
885
782
"EventCode": "0xCB",
886
783
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
887
784
"PEBS": "1",
···
891
786
},
892
787
{
893
788
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
789
+
"Counter": "0,1,2,3",
894
790
"EventCode": "0xCB",
895
791
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
896
792
"PEBS": "1",
···
900
794
},
901
795
{
902
796
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
797
+
"Counter": "0,1,2,3",
903
798
"EventCode": "0xCB",
904
799
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
905
800
"PEBS": "1",
···
909
802
},
910
803
{
911
804
"BriefDescription": "Offcore L1 data cache writebacks",
805
+
"Counter": "0,1,2,3",
912
806
"EventCode": "0xB0",
913
807
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
914
808
"SampleAfterValue": "100000",
···
917
809
},
918
810
{
919
811
"BriefDescription": "Offcore requests blocked due to Super Queue full",
812
+
"Counter": "0,1,2,3",
920
813
"EventCode": "0xB2",
921
814
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
922
815
"SampleAfterValue": "100000",
···
925
816
},
926
817
{
927
818
"BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
819
+
"Counter": "2",
928
820
"EventCode": "0xB7",
929
821
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
930
822
"MSRIndex": "0x1A6",
···
935
825
},
936
826
{
937
827
"BriefDescription": "All offcore data reads",
828
+
"Counter": "2",
938
829
"EventCode": "0xB7",
939
830
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
940
831
"MSRIndex": "0x1A6",
···
945
834
},
946
835
{
947
836
"BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
837
+
"Counter": "2",
948
838
"EventCode": "0xB7",
949
839
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
950
840
"MSRIndex": "0x1A6",
···
955
843
},
956
844
{
957
845
"BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
846
+
"Counter": "2",
958
847
"EventCode": "0xB7",
959
848
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
960
849
"MSRIndex": "0x1A6",
···
965
852
},
966
853
{
967
854
"BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
855
+
"Counter": "2",
968
856
"EventCode": "0xB7",
969
857
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
970
858
"MSRIndex": "0x1A6",
···
975
861
},
976
862
{
977
863
"BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
864
+
"Counter": "2",
978
865
"EventCode": "0xB7",
979
866
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
980
867
"MSRIndex": "0x1A6",
···
985
870
},
986
871
{
987
872
"BriefDescription": "Offcore data reads satisfied by the LLC",
873
+
"Counter": "2",
988
874
"EventCode": "0xB7",
989
875
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
990
876
"MSRIndex": "0x1A6",
···
995
879
},
996
880
{
997
881
"BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
882
+
"Counter": "2",
998
883
"EventCode": "0xB7",
999
884
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
1000
885
"MSRIndex": "0x1A6",
···
1005
888
},
1006
889
{
1007
890
"BriefDescription": "Offcore data reads satisfied by a remote cache",
891
+
"Counter": "2",
1008
892
"EventCode": "0xB7",
1009
893
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
1010
894
"MSRIndex": "0x1A6",
···
1015
897
},
1016
898
{
1017
899
"BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
900
+
"Counter": "2",
1018
901
"EventCode": "0xB7",
1019
902
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
1020
903
"MSRIndex": "0x1A6",
···
1025
906
},
1026
907
{
1027
908
"BriefDescription": "Offcore data reads that HIT in a remote cache",
909
+
"Counter": "2",
1028
910
"EventCode": "0xB7",
1029
911
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
1030
912
"MSRIndex": "0x1A6",
···
1035
915
},
1036
916
{
1037
917
"BriefDescription": "Offcore data reads that HITM in a remote cache",
918
+
"Counter": "2",
1038
919
"EventCode": "0xB7",
1039
920
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
1040
921
"MSRIndex": "0x1A6",
···
1045
924
},
1046
925
{
1047
926
"BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
927
+
"Counter": "2",
1048
928
"EventCode": "0xB7",
1049
929
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
1050
930
"MSRIndex": "0x1A6",
···
1055
933
},
1056
934
{
1057
935
"BriefDescription": "All offcore code reads",
936
+
"Counter": "2",
1058
937
"EventCode": "0xB7",
1059
938
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
1060
939
"MSRIndex": "0x1A6",
···
1065
942
},
1066
943
{
1067
944
"BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
945
+
"Counter": "2",
1068
946
"EventCode": "0xB7",
1069
947
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
1070
948
"MSRIndex": "0x1A6",
···
1075
951
},
1076
952
{
1077
953
"BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
954
+
"Counter": "2",
1078
955
"EventCode": "0xB7",
1079
956
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
1080
957
"MSRIndex": "0x1A6",
···
1085
960
},
1086
961
{
1087
962
"BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
963
+
"Counter": "2",
1088
964
"EventCode": "0xB7",
1089
965
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1090
966
"MSRIndex": "0x1A6",
···
1095
969
},
1096
970
{
1097
971
"BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
972
+
"Counter": "2",
1098
973
"EventCode": "0xB7",
1099
974
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1100
975
"MSRIndex": "0x1A6",
···
1105
978
},
1106
979
{
1107
980
"BriefDescription": "Offcore code reads satisfied by the LLC",
981
+
"Counter": "2",
1108
982
"EventCode": "0xB7",
1109
983
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
1110
984
"MSRIndex": "0x1A6",
···
1115
987
},
1116
988
{
1117
989
"BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
990
+
"Counter": "2",
1118
991
"EventCode": "0xB7",
1119
992
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
1120
993
"MSRIndex": "0x1A6",
···
1125
996
},
1126
997
{
1127
998
"BriefDescription": "Offcore code reads satisfied by a remote cache",
999
+
"Counter": "2",
1128
1000
"EventCode": "0xB7",
1129
1001
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
1130
1002
"MSRIndex": "0x1A6",
···
1135
1005
},
1136
1006
{
1137
1007
"BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
1008
+
"Counter": "2",
1138
1009
"EventCode": "0xB7",
1139
1010
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
1140
1011
"MSRIndex": "0x1A6",
···
1145
1014
},
1146
1015
{
1147
1016
"BriefDescription": "Offcore code reads that HIT in a remote cache",
1017
+
"Counter": "2",
1148
1018
"EventCode": "0xB7",
1149
1019
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
1150
1020
"MSRIndex": "0x1A6",
···
1155
1023
},
1156
1024
{
1157
1025
"BriefDescription": "Offcore code reads that HITM in a remote cache",
1026
+
"Counter": "2",
1158
1027
"EventCode": "0xB7",
1159
1028
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
1160
1029
"MSRIndex": "0x1A6",
···
1165
1032
},
1166
1033
{
1167
1034
"BriefDescription": "Offcore requests satisfied by any cache or DRAM",
1035
+
"Counter": "2",
1168
1036
"EventCode": "0xB7",
1169
1037
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1170
1038
"MSRIndex": "0x1A6",
···
1175
1041
},
1176
1042
{
1177
1043
"BriefDescription": "All offcore requests",
1044
+
"Counter": "2",
1178
1045
"EventCode": "0xB7",
1179
1046
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1180
1047
"MSRIndex": "0x1A6",
···
1185
1050
},
1186
1051
{
1187
1052
"BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
1053
+
"Counter": "2",
1188
1054
"EventCode": "0xB7",
1189
1055
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1190
1056
"MSRIndex": "0x1A6",
···
1195
1059
},
1196
1060
{
1197
1061
"BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
1062
+
"Counter": "2",
1198
1063
"EventCode": "0xB7",
1199
1064
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1200
1065
"MSRIndex": "0x1A6",
···
1205
1068
},
1206
1069
{
1207
1070
"BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
1071
+
"Counter": "2",
1208
1072
"EventCode": "0xB7",
1209
1073
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1210
1074
"MSRIndex": "0x1A6",
···
1215
1077
},
1216
1078
{
1217
1079
"BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
1080
+
"Counter": "2",
1218
1081
"EventCode": "0xB7",
1219
1082
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1220
1083
"MSRIndex": "0x1A6",
···
1225
1086
},
1226
1087
{
1227
1088
"BriefDescription": "Offcore requests satisfied by the LLC",
1089
+
"Counter": "2",
1228
1090
"EventCode": "0xB7",
1229
1091
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1230
1092
"MSRIndex": "0x1A6",
···
1235
1095
},
1236
1096
{
1237
1097
"BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
1098
+
"Counter": "2",
1238
1099
"EventCode": "0xB7",
1239
1100
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
1240
1101
"MSRIndex": "0x1A6",
···
1245
1104
},
1246
1105
{
1247
1106
"BriefDescription": "Offcore requests satisfied by a remote cache",
1107
+
"Counter": "2",
1248
1108
"EventCode": "0xB7",
1249
1109
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
1250
1110
"MSRIndex": "0x1A6",
···
1255
1113
},
1256
1114
{
1257
1115
"BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
1116
+
"Counter": "2",
1258
1117
"EventCode": "0xB7",
1259
1118
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
1260
1119
"MSRIndex": "0x1A6",
···
1265
1122
},
1266
1123
{
1267
1124
"BriefDescription": "Offcore requests that HIT in a remote cache",
1125
+
"Counter": "2",
1268
1126
"EventCode": "0xB7",
1269
1127
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
1270
1128
"MSRIndex": "0x1A6",
···
1275
1131
},
1276
1132
{
1277
1133
"BriefDescription": "Offcore requests that HITM in a remote cache",
1134
+
"Counter": "2",
1278
1135
"EventCode": "0xB7",
1279
1136
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1280
1137
"MSRIndex": "0x1A6",
···
1285
1140
},
1286
1141
{
1287
1142
"BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
1143
+
"Counter": "2",
1288
1144
"EventCode": "0xB7",
1289
1145
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1290
1146
"MSRIndex": "0x1A6",
···
1295
1149
},
1296
1150
{
1297
1151
"BriefDescription": "All offcore RFO requests",
1152
+
"Counter": "2",
1298
1153
"EventCode": "0xB7",
1299
1154
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1300
1155
"MSRIndex": "0x1A6",
···
1305
1158
},
1306
1159
{
1307
1160
"BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
1161
+
"Counter": "2",
1308
1162
"EventCode": "0xB7",
1309
1163
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1310
1164
"MSRIndex": "0x1A6",
···
1315
1167
},
1316
1168
{
1317
1169
"BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
1170
+
"Counter": "2",
1318
1171
"EventCode": "0xB7",
1319
1172
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1320
1173
"MSRIndex": "0x1A6",
···
1325
1176
},
1326
1177
{
1327
1178
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
1179
+
"Counter": "2",
1328
1180
"EventCode": "0xB7",
1329
1181
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1330
1182
"MSRIndex": "0x1A6",
···
1335
1185
},
1336
1186
{
1337
1187
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
1188
+
"Counter": "2",
1338
1189
"EventCode": "0xB7",
1339
1190
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1340
1191
"MSRIndex": "0x1A6",
···
1345
1194
},
1346
1195
{
1347
1196
"BriefDescription": "Offcore RFO requests satisfied by the LLC",
1197
+
"Counter": "2",
1348
1198
"EventCode": "0xB7",
1349
1199
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1350
1200
"MSRIndex": "0x1A6",
···
1355
1203
},
1356
1204
{
1357
1205
"BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
1206
+
"Counter": "2",
1358
1207
"EventCode": "0xB7",
1359
1208
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
1360
1209
"MSRIndex": "0x1A6",
···
1365
1212
},
1366
1213
{
1367
1214
"BriefDescription": "Offcore RFO requests satisfied by a remote cache",
1215
+
"Counter": "2",
1368
1216
"EventCode": "0xB7",
1369
1217
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
1370
1218
"MSRIndex": "0x1A6",
···
1375
1221
},
1376
1222
{
1377
1223
"BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
1224
+
"Counter": "2",
1378
1225
"EventCode": "0xB7",
1379
1226
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
1380
1227
"MSRIndex": "0x1A6",
···
1385
1230
},
1386
1231
{
1387
1232
"BriefDescription": "Offcore RFO requests that HIT in a remote cache",
1233
+
"Counter": "2",
1388
1234
"EventCode": "0xB7",
1389
1235
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
1390
1236
"MSRIndex": "0x1A6",
···
1395
1239
},
1396
1240
{
1397
1241
"BriefDescription": "Offcore RFO requests that HITM in a remote cache",
1242
+
"Counter": "2",
1398
1243
"EventCode": "0xB7",
1399
1244
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1400
1245
"MSRIndex": "0x1A6",
···
1405
1248
},
1406
1249
{
1407
1250
"BriefDescription": "Offcore writebacks to any cache or DRAM.",
1251
+
"Counter": "2",
1408
1252
"EventCode": "0xB7",
1409
1253
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1410
1254
"MSRIndex": "0x1A6",
···
1415
1257
},
1416
1258
{
1417
1259
"BriefDescription": "All offcore writebacks",
1260
+
"Counter": "2",
1418
1261
"EventCode": "0xB7",
1419
1262
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1420
1263
"MSRIndex": "0x1A6",
···
1425
1266
},
1426
1267
{
1427
1268
"BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
1269
+
"Counter": "2",
1428
1270
"EventCode": "0xB7",
1429
1271
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1430
1272
"MSRIndex": "0x1A6",
···
1435
1275
},
1436
1276
{
1437
1277
"BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
1278
+
"Counter": "2",
1438
1279
"EventCode": "0xB7",
1439
1280
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1440
1281
"MSRIndex": "0x1A6",
···
1445
1284
},
1446
1285
{
1447
1286
"BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
1287
+
"Counter": "2",
1448
1288
"EventCode": "0xB7",
1449
1289
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1450
1290
"MSRIndex": "0x1A6",
···
1455
1293
},
1456
1294
{
1457
1295
"BriefDescription": "Offcore writebacks to the LLC",
1296
+
"Counter": "2",
1458
1297
"EventCode": "0xB7",
1459
1298
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1460
1299
"MSRIndex": "0x1A6",
···
1465
1302
},
1466
1303
{
1467
1304
"BriefDescription": "Offcore writebacks to the LLC or local DRAM",
1305
+
"Counter": "2",
1468
1306
"EventCode": "0xB7",
1469
1307
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
1470
1308
"MSRIndex": "0x1A6",
···
1475
1311
},
1476
1312
{
1477
1313
"BriefDescription": "Offcore writebacks to a remote cache",
1314
+
"Counter": "2",
1478
1315
"EventCode": "0xB7",
1479
1316
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
1480
1317
"MSRIndex": "0x1A6",
···
1485
1320
},
1486
1321
{
1487
1322
"BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
1323
+
"Counter": "2",
1488
1324
"EventCode": "0xB7",
1489
1325
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
1490
1326
"MSRIndex": "0x1A6",
···
1495
1329
},
1496
1330
{
1497
1331
"BriefDescription": "Offcore writebacks that HIT in a remote cache",
1332
+
"Counter": "2",
1498
1333
"EventCode": "0xB7",
1499
1334
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
1500
1335
"MSRIndex": "0x1A6",
···
1505
1338
},
1506
1339
{
1507
1340
"BriefDescription": "Offcore writebacks that HITM in a remote cache",
1341
+
"Counter": "2",
1508
1342
"EventCode": "0xB7",
1509
1343
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1510
1344
"MSRIndex": "0x1A6",
···
1515
1347
},
1516
1348
{
1517
1349
"BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
1350
+
"Counter": "2",
1518
1351
"EventCode": "0xB7",
1519
1352
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1520
1353
"MSRIndex": "0x1A6",
···
1525
1356
},
1526
1357
{
1527
1358
"BriefDescription": "All offcore code or data read requests",
1359
+
"Counter": "2",
1528
1360
"EventCode": "0xB7",
1529
1361
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1530
1362
"MSRIndex": "0x1A6",
···
1535
1365
},
1536
1366
{
1537
1367
"BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
1368
+
"Counter": "2",
1538
1369
"EventCode": "0xB7",
1539
1370
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1540
1371
"MSRIndex": "0x1A6",
···
1545
1374
},
1546
1375
{
1547
1376
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
1377
+
"Counter": "2",
1548
1378
"EventCode": "0xB7",
1549
1379
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1550
1380
"MSRIndex": "0x1A6",
···
1555
1383
},
1556
1384
{
1557
1385
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
1386
+
"Counter": "2",
1558
1387
"EventCode": "0xB7",
1559
1388
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1560
1389
"MSRIndex": "0x1A6",
···
1565
1392
},
1566
1393
{
1567
1394
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
1395
+
"Counter": "2",
1568
1396
"EventCode": "0xB7",
1569
1397
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1570
1398
"MSRIndex": "0x1A6",
···
1575
1401
},
1576
1402
{
1577
1403
"BriefDescription": "Offcore code or data read requests satisfied by the LLC",
1404
+
"Counter": "2",
1578
1405
"EventCode": "0xB7",
1579
1406
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1580
1407
"MSRIndex": "0x1A6",
···
1585
1410
},
1586
1411
{
1587
1412
"BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
1413
+
"Counter": "2",
1588
1414
"EventCode": "0xB7",
1589
1415
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
1590
1416
"MSRIndex": "0x1A6",
···
1595
1419
},
1596
1420
{
1597
1421
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
1422
+
"Counter": "2",
1598
1423
"EventCode": "0xB7",
1599
1424
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
1600
1425
"MSRIndex": "0x1A6",
···
1605
1428
},
1606
1429
{
1607
1430
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
1431
+
"Counter": "2",
1608
1432
"EventCode": "0xB7",
1609
1433
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
1610
1434
"MSRIndex": "0x1A6",
···
1615
1437
},
1616
1438
{
1617
1439
"BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
1440
+
"Counter": "2",
1618
1441
"EventCode": "0xB7",
1619
1442
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
1620
1443
"MSRIndex": "0x1A6",
···
1625
1446
},
1626
1447
{
1627
1448
"BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
1449
+
"Counter": "2",
1628
1450
"EventCode": "0xB7",
1629
1451
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1630
1452
"MSRIndex": "0x1A6",
···
1635
1455
},
1636
1456
{
1637
1457
"BriefDescription": "Offcore request = all data, response = any cache_dram",
1458
+
"Counter": "2",
1638
1459
"EventCode": "0xB7",
1639
1460
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1640
1461
"MSRIndex": "0x1A6",
···
1645
1464
},
1646
1465
{
1647
1466
"BriefDescription": "Offcore request = all data, response = any location",
1467
+
"Counter": "2",
1648
1468
"EventCode": "0xB7",
1649
1469
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1650
1470
"MSRIndex": "0x1A6",
···
1655
1473
},
1656
1474
{
1657
1475
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
1476
+
"Counter": "2",
1658
1477
"EventCode": "0xB7",
1659
1478
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1660
1479
"MSRIndex": "0x1A6",
···
1665
1482
},
1666
1483
{
1667
1484
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
1485
+
"Counter": "2",
1668
1486
"EventCode": "0xB7",
1669
1487
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1670
1488
"MSRIndex": "0x1A6",
···
1675
1491
},
1676
1492
{
1677
1493
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
1494
+
"Counter": "2",
1678
1495
"EventCode": "0xB7",
1679
1496
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1680
1497
"MSRIndex": "0x1A6",
···
1685
1500
},
1686
1501
{
1687
1502
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
1503
+
"Counter": "2",
1688
1504
"EventCode": "0xB7",
1689
1505
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1690
1506
"MSRIndex": "0x1A6",
···
1695
1509
},
1696
1510
{
1697
1511
"BriefDescription": "Offcore request = all data, response = local cache",
1512
+
"Counter": "2",
1698
1513
"EventCode": "0xB7",
1699
1514
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1700
1515
"MSRIndex": "0x1A6",
···
1705
1518
},
1706
1519
{
1707
1520
"BriefDescription": "Offcore request = all data, response = local cache or dram",
1521
+
"Counter": "2",
1708
1522
"EventCode": "0xB7",
1709
1523
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
1710
1524
"MSRIndex": "0x1A6",
···
1715
1527
},
1716
1528
{
1717
1529
"BriefDescription": "Offcore request = all data, response = remote cache",
1530
+
"Counter": "2",
1718
1531
"EventCode": "0xB7",
1719
1532
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
1720
1533
"MSRIndex": "0x1A6",
···
1725
1536
},
1726
1537
{
1727
1538
"BriefDescription": "Offcore request = all data, response = remote cache or dram",
1539
+
"Counter": "2",
1728
1540
"EventCode": "0xB7",
1729
1541
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
1730
1542
"MSRIndex": "0x1A6",
···
1735
1545
},
1736
1546
{
1737
1547
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
1548
+
"Counter": "2",
1738
1549
"EventCode": "0xB7",
1739
1550
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
1740
1551
"MSRIndex": "0x1A6",
···
1745
1554
},
1746
1555
{
1747
1556
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
1557
+
"Counter": "2",
1748
1558
"EventCode": "0xB7",
1749
1559
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1750
1560
"MSRIndex": "0x1A6",
···
1755
1563
},
1756
1564
{
1757
1565
"BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
1566
+
"Counter": "2",
1758
1567
"EventCode": "0xB7",
1759
1568
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1760
1569
"MSRIndex": "0x1A6",
···
1765
1572
},
1766
1573
{
1767
1574
"BriefDescription": "All offcore demand data requests",
1575
+
"Counter": "2",
1768
1576
"EventCode": "0xB7",
1769
1577
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1770
1578
"MSRIndex": "0x1A6",
···
1775
1581
},
1776
1582
{
1777
1583
"BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
1584
+
"Counter": "2",
1778
1585
"EventCode": "0xB7",
1779
1586
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1780
1587
"MSRIndex": "0x1A6",
···
1785
1590
},
1786
1591
{
1787
1592
"BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
1593
+
"Counter": "2",
1788
1594
"EventCode": "0xB7",
1789
1595
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1790
1596
"MSRIndex": "0x1A6",
···
1795
1599
},
1796
1600
{
1797
1601
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
1602
+
"Counter": "2",
1798
1603
"EventCode": "0xB7",
1799
1604
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1800
1605
"MSRIndex": "0x1A6",
···
1805
1608
},
1806
1609
{
1807
1610
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
1611
+
"Counter": "2",
1808
1612
"EventCode": "0xB7",
1809
1613
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1810
1614
"MSRIndex": "0x1A6",
···
1815
1617
},
1816
1618
{
1817
1619
"BriefDescription": "Offcore demand data requests satisfied by the LLC",
1620
+
"Counter": "2",
1818
1621
"EventCode": "0xB7",
1819
1622
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1820
1623
"MSRIndex": "0x1A6",
···
1825
1626
},
1826
1627
{
1827
1628
"BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
1629
+
"Counter": "2",
1828
1630
"EventCode": "0xB7",
1829
1631
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
1830
1632
"MSRIndex": "0x1A6",
···
1835
1635
},
1836
1636
{
1837
1637
"BriefDescription": "Offcore demand data requests satisfied by a remote cache",
1638
+
"Counter": "2",
1838
1639
"EventCode": "0xB7",
1839
1640
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
1840
1641
"MSRIndex": "0x1A6",
···
1845
1644
},
1846
1645
{
1847
1646
"BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
1647
+
"Counter": "2",
1848
1648
"EventCode": "0xB7",
1849
1649
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
1850
1650
"MSRIndex": "0x1A6",
···
1855
1653
},
1856
1654
{
1857
1655
"BriefDescription": "Offcore demand data requests that HIT in a remote cache",
1656
+
"Counter": "2",
1858
1657
"EventCode": "0xB7",
1859
1658
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
1860
1659
"MSRIndex": "0x1A6",
···
1865
1662
},
1866
1663
{
1867
1664
"BriefDescription": "Offcore demand data requests that HITM in a remote cache",
1665
+
"Counter": "2",
1868
1666
"EventCode": "0xB7",
1869
1667
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
1870
1668
"MSRIndex": "0x1A6",
···
1875
1671
},
1876
1672
{
1877
1673
"BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
1674
+
"Counter": "2",
1878
1675
"EventCode": "0xB7",
1879
1676
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
1880
1677
"MSRIndex": "0x1A6",
···
1885
1680
},
1886
1681
{
1887
1682
"BriefDescription": "All offcore demand data reads",
1683
+
"Counter": "2",
1888
1684
"EventCode": "0xB7",
1889
1685
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
1890
1686
"MSRIndex": "0x1A6",
···
1895
1689
},
1896
1690
{
1897
1691
"BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
1692
+
"Counter": "2",
1898
1693
"EventCode": "0xB7",
1899
1694
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
1900
1695
"MSRIndex": "0x1A6",
···
1905
1698
},
1906
1699
{
1907
1700
"BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
1701
+
"Counter": "2",
1908
1702
"EventCode": "0xB7",
1909
1703
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
1910
1704
"MSRIndex": "0x1A6",
···
1915
1707
},
1916
1708
{
1917
1709
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
1710
+
"Counter": "2",
1918
1711
"EventCode": "0xB7",
1919
1712
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
1920
1713
"MSRIndex": "0x1A6",
···
1925
1716
},
1926
1717
{
1927
1718
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
1719
+
"Counter": "2",
1928
1720
"EventCode": "0xB7",
1929
1721
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
1930
1722
"MSRIndex": "0x1A6",
···
1935
1725
},
1936
1726
{
1937
1727
"BriefDescription": "Offcore demand data reads satisfied by the LLC",
1728
+
"Counter": "2",
1938
1729
"EventCode": "0xB7",
1939
1730
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
1940
1731
"MSRIndex": "0x1A6",
···
1945
1734
},
1946
1735
{
1947
1736
"BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
1737
+
"Counter": "2",
1948
1738
"EventCode": "0xB7",
1949
1739
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
1950
1740
"MSRIndex": "0x1A6",
···
1955
1743
},
1956
1744
{
1957
1745
"BriefDescription": "Offcore demand data reads satisfied by a remote cache",
1746
+
"Counter": "2",
1958
1747
"EventCode": "0xB7",
1959
1748
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
1960
1749
"MSRIndex": "0x1A6",
···
1965
1752
},
1966
1753
{
1967
1754
"BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
1755
+
"Counter": "2",
1968
1756
"EventCode": "0xB7",
1969
1757
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
1970
1758
"MSRIndex": "0x1A6",
···
1975
1761
},
1976
1762
{
1977
1763
"BriefDescription": "Offcore demand data reads that HIT in a remote cache",
1764
+
"Counter": "2",
1978
1765
"EventCode": "0xB7",
1979
1766
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
1980
1767
"MSRIndex": "0x1A6",
···
1985
1770
},
1986
1771
{
1987
1772
"BriefDescription": "Offcore demand data reads that HITM in a remote cache",
1773
+
"Counter": "2",
1988
1774
"EventCode": "0xB7",
1989
1775
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
1990
1776
"MSRIndex": "0x1A6",
···
1995
1779
},
1996
1780
{
1997
1781
"BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
1782
+
"Counter": "2",
1998
1783
"EventCode": "0xB7",
1999
1784
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
2000
1785
"MSRIndex": "0x1A6",
···
2005
1788
},
2006
1789
{
2007
1790
"BriefDescription": "All offcore demand code reads",
1791
+
"Counter": "2",
2008
1792
"EventCode": "0xB7",
2009
1793
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
2010
1794
"MSRIndex": "0x1A6",
···
2015
1797
},
2016
1798
{
2017
1799
"BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
1800
+
"Counter": "2",
2018
1801
"EventCode": "0xB7",
2019
1802
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
2020
1803
"MSRIndex": "0x1A6",
···
2025
1806
},
2026
1807
{
2027
1808
"BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
1809
+
"Counter": "2",
2028
1810
"EventCode": "0xB7",
2029
1811
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
2030
1812
"MSRIndex": "0x1A6",
···
2035
1815
},
2036
1816
{
2037
1817
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
1818
+
"Counter": "2",
2038
1819
"EventCode": "0xB7",
2039
1820
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2040
1821
"MSRIndex": "0x1A6",
···
2045
1824
},
2046
1825
{
2047
1826
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
1827
+
"Counter": "2",
2048
1828
"EventCode": "0xB7",
2049
1829
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2050
1830
"MSRIndex": "0x1A6",
···
2055
1833
},
2056
1834
{
2057
1835
"BriefDescription": "Offcore demand code reads satisfied by the LLC",
1836
+
"Counter": "2",
2058
1837
"EventCode": "0xB7",
2059
1838
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
2060
1839
"MSRIndex": "0x1A6",
···
2065
1842
},
2066
1843
{
2067
1844
"BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
1845
+
"Counter": "2",
2068
1846
"EventCode": "0xB7",
2069
1847
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
2070
1848
"MSRIndex": "0x1A6",
···
2075
1851
},
2076
1852
{
2077
1853
"BriefDescription": "Offcore demand code reads satisfied by a remote cache",
1854
+
"Counter": "2",
2078
1855
"EventCode": "0xB7",
2079
1856
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
2080
1857
"MSRIndex": "0x1A6",
···
2085
1860
},
2086
1861
{
2087
1862
"BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
1863
+
"Counter": "2",
2088
1864
"EventCode": "0xB7",
2089
1865
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
2090
1866
"MSRIndex": "0x1A6",
···
2095
1869
},
2096
1870
{
2097
1871
"BriefDescription": "Offcore demand code reads that HIT in a remote cache",
1872
+
"Counter": "2",
2098
1873
"EventCode": "0xB7",
2099
1874
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
2100
1875
"MSRIndex": "0x1A6",
···
2105
1878
},
2106
1879
{
2107
1880
"BriefDescription": "Offcore demand code reads that HITM in a remote cache",
1881
+
"Counter": "2",
2108
1882
"EventCode": "0xB7",
2109
1883
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
2110
1884
"MSRIndex": "0x1A6",
···
2115
1887
},
2116
1888
{
2117
1889
"BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
1890
+
"Counter": "2",
2118
1891
"EventCode": "0xB7",
2119
1892
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
2120
1893
"MSRIndex": "0x1A6",
···
2125
1896
},
2126
1897
{
2127
1898
"BriefDescription": "All offcore demand RFO requests",
1899
+
"Counter": "2",
2128
1900
"EventCode": "0xB7",
2129
1901
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
2130
1902
"MSRIndex": "0x1A6",
···
2135
1905
},
2136
1906
{
2137
1907
"BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
1908
+
"Counter": "2",
2138
1909
"EventCode": "0xB7",
2139
1910
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
2140
1911
"MSRIndex": "0x1A6",
···
2145
1914
},
2146
1915
{
2147
1916
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
1917
+
"Counter": "2",
2148
1918
"EventCode": "0xB7",
2149
1919
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
2150
1920
"MSRIndex": "0x1A6",
···
2155
1923
},
2156
1924
{
2157
1925
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
1926
+
"Counter": "2",
2158
1927
"EventCode": "0xB7",
2159
1928
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
2160
1929
"MSRIndex": "0x1A6",
···
2165
1932
},
2166
1933
{
2167
1934
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
1935
+
"Counter": "2",
2168
1936
"EventCode": "0xB7",
2169
1937
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
2170
1938
"MSRIndex": "0x1A6",
···
2175
1941
},
2176
1942
{
2177
1943
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
1944
+
"Counter": "2",
2178
1945
"EventCode": "0xB7",
2179
1946
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
2180
1947
"MSRIndex": "0x1A6",
···
2185
1950
},
2186
1951
{
2187
1952
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
1953
+
"Counter": "2",
2188
1954
"EventCode": "0xB7",
2189
1955
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
2190
1956
"MSRIndex": "0x1A6",
···
2195
1959
},
2196
1960
{
2197
1961
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
1962
+
"Counter": "2",
2198
1963
"EventCode": "0xB7",
2199
1964
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
2200
1965
"MSRIndex": "0x1A6",
···
2205
1968
},
2206
1969
{
2207
1970
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
1971
+
"Counter": "2",
2208
1972
"EventCode": "0xB7",
2209
1973
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
2210
1974
"MSRIndex": "0x1A6",
···
2215
1977
},
2216
1978
{
2217
1979
"BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
1980
+
"Counter": "2",
2218
1981
"EventCode": "0xB7",
2219
1982
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
2220
1983
"MSRIndex": "0x1A6",
···
2225
1986
},
2226
1987
{
2227
1988
"BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
1989
+
"Counter": "2",
2228
1990
"EventCode": "0xB7",
2229
1991
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
2230
1992
"MSRIndex": "0x1A6",
···
2235
1995
},
2236
1996
{
2237
1997
"BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
1998
+
"Counter": "2",
2238
1999
"EventCode": "0xB7",
2239
2000
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
2240
2001
"MSRIndex": "0x1A6",
···
2245
2004
},
2246
2005
{
2247
2006
"BriefDescription": "All offcore other requests",
2007
+
"Counter": "2",
2248
2008
"EventCode": "0xB7",
2249
2009
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
2250
2010
"MSRIndex": "0x1A6",
···
2255
2013
},
2256
2014
{
2257
2015
"BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
2016
+
"Counter": "2",
2258
2017
"EventCode": "0xB7",
2259
2018
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
2260
2019
"MSRIndex": "0x1A6",
···
2265
2022
},
2266
2023
{
2267
2024
"BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
2025
+
"Counter": "2",
2268
2026
"EventCode": "0xB7",
2269
2027
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
2270
2028
"MSRIndex": "0x1A6",
···
2275
2031
},
2276
2032
{
2277
2033
"BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
2034
+
"Counter": "2",
2278
2035
"EventCode": "0xB7",
2279
2036
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
2280
2037
"MSRIndex": "0x1A6",
···
2285
2040
},
2286
2041
{
2287
2042
"BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
2043
+
"Counter": "2",
2288
2044
"EventCode": "0xB7",
2289
2045
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
2290
2046
"MSRIndex": "0x1A6",
···
2295
2049
},
2296
2050
{
2297
2051
"BriefDescription": "Offcore other requests satisfied by the LLC",
2052
+
"Counter": "2",
2298
2053
"EventCode": "0xB7",
2299
2054
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
2300
2055
"MSRIndex": "0x1A6",
···
2305
2058
},
2306
2059
{
2307
2060
"BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
2061
+
"Counter": "2",
2308
2062
"EventCode": "0xB7",
2309
2063
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
2310
2064
"MSRIndex": "0x1A6",
···
2315
2067
},
2316
2068
{
2317
2069
"BriefDescription": "Offcore other requests satisfied by a remote cache",
2070
+
"Counter": "2",
2318
2071
"EventCode": "0xB7",
2319
2072
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
2320
2073
"MSRIndex": "0x1A6",
···
2325
2076
},
2326
2077
{
2327
2078
"BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
2079
+
"Counter": "2",
2328
2080
"EventCode": "0xB7",
2329
2081
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
2330
2082
"MSRIndex": "0x1A6",
···
2335
2085
},
2336
2086
{
2337
2087
"BriefDescription": "Offcore other requests that HIT in a remote cache",
2088
+
"Counter": "2",
2338
2089
"EventCode": "0xB7",
2339
2090
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
2340
2091
"MSRIndex": "0x1A6",
···
2345
2094
},
2346
2095
{
2347
2096
"BriefDescription": "Offcore other requests that HITM in a remote cache",
2097
+
"Counter": "2",
2348
2098
"EventCode": "0xB7",
2349
2099
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
2350
2100
"MSRIndex": "0x1A6",
···
2355
2103
},
2356
2104
{
2357
2105
"BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
2106
+
"Counter": "2",
2358
2107
"EventCode": "0xB7",
2359
2108
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
2360
2109
"MSRIndex": "0x1A6",
···
2365
2112
},
2366
2113
{
2367
2114
"BriefDescription": "All offcore prefetch data requests",
2115
+
"Counter": "2",
2368
2116
"EventCode": "0xB7",
2369
2117
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
2370
2118
"MSRIndex": "0x1A6",
···
2375
2121
},
2376
2122
{
2377
2123
"BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
2124
+
"Counter": "2",
2378
2125
"EventCode": "0xB7",
2379
2126
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
2380
2127
"MSRIndex": "0x1A6",
···
2385
2130
},
2386
2131
{
2387
2132
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
2133
+
"Counter": "2",
2388
2134
"EventCode": "0xB7",
2389
2135
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
2390
2136
"MSRIndex": "0x1A6",
···
2395
2139
},
2396
2140
{
2397
2141
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
2142
+
"Counter": "2",
2398
2143
"EventCode": "0xB7",
2399
2144
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
2400
2145
"MSRIndex": "0x1A6",
···
2405
2148
},
2406
2149
{
2407
2150
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
2151
+
"Counter": "2",
2408
2152
"EventCode": "0xB7",
2409
2153
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
2410
2154
"MSRIndex": "0x1A6",
···
2415
2157
},
2416
2158
{
2417
2159
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
2160
+
"Counter": "2",
2418
2161
"EventCode": "0xB7",
2419
2162
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
2420
2163
"MSRIndex": "0x1A6",
···
2425
2166
},
2426
2167
{
2427
2168
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
2169
+
"Counter": "2",
2428
2170
"EventCode": "0xB7",
2429
2171
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
2430
2172
"MSRIndex": "0x1A6",
···
2435
2175
},
2436
2176
{
2437
2177
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
2178
+
"Counter": "2",
2438
2179
"EventCode": "0xB7",
2439
2180
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
2440
2181
"MSRIndex": "0x1A6",
···
2445
2184
},
2446
2185
{
2447
2186
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
2187
+
"Counter": "2",
2448
2188
"EventCode": "0xB7",
2449
2189
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
2450
2190
"MSRIndex": "0x1A6",
···
2455
2193
},
2456
2194
{
2457
2195
"BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
2196
+
"Counter": "2",
2458
2197
"EventCode": "0xB7",
2459
2198
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
2460
2199
"MSRIndex": "0x1A6",
···
2465
2202
},
2466
2203
{
2467
2204
"BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
2205
+
"Counter": "2",
2468
2206
"EventCode": "0xB7",
2469
2207
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
2470
2208
"MSRIndex": "0x1A6",
···
2475
2211
},
2476
2212
{
2477
2213
"BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
2214
+
"Counter": "2",
2478
2215
"EventCode": "0xB7",
2479
2216
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
2480
2217
"MSRIndex": "0x1A6",
···
2485
2220
},
2486
2221
{
2487
2222
"BriefDescription": "All offcore prefetch data reads",
2223
+
"Counter": "2",
2488
2224
"EventCode": "0xB7",
2489
2225
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2490
2226
"MSRIndex": "0x1A6",
···
2495
2229
},
2496
2230
{
2497
2231
"BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
2232
+
"Counter": "2",
2498
2233
"EventCode": "0xB7",
2499
2234
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2500
2235
"MSRIndex": "0x1A6",
···
2505
2238
},
2506
2239
{
2507
2240
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
2241
+
"Counter": "2",
2508
2242
"EventCode": "0xB7",
2509
2243
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2510
2244
"MSRIndex": "0x1A6",
···
2515
2247
},
2516
2248
{
2517
2249
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
2250
+
"Counter": "2",
2518
2251
"EventCode": "0xB7",
2519
2252
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2520
2253
"MSRIndex": "0x1A6",
···
2525
2256
},
2526
2257
{
2527
2258
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
2259
+
"Counter": "2",
2528
2260
"EventCode": "0xB7",
2529
2261
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2530
2262
"MSRIndex": "0x1A6",
···
2535
2265
},
2536
2266
{
2537
2267
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
2268
+
"Counter": "2",
2538
2269
"EventCode": "0xB7",
2539
2270
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2540
2271
"MSRIndex": "0x1A6",
···
2545
2274
},
2546
2275
{
2547
2276
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
2277
+
"Counter": "2",
2548
2278
"EventCode": "0xB7",
2549
2279
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
2550
2280
"MSRIndex": "0x1A6",
···
2555
2283
},
2556
2284
{
2557
2285
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
2286
+
"Counter": "2",
2558
2287
"EventCode": "0xB7",
2559
2288
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
2560
2289
"MSRIndex": "0x1A6",
···
2565
2292
},
2566
2293
{
2567
2294
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
2295
+
"Counter": "2",
2568
2296
"EventCode": "0xB7",
2569
2297
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
2570
2298
"MSRIndex": "0x1A6",
···
2575
2301
},
2576
2302
{
2577
2303
"BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
2304
+
"Counter": "2",
2578
2305
"EventCode": "0xB7",
2579
2306
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
2580
2307
"MSRIndex": "0x1A6",
···
2585
2310
},
2586
2311
{
2587
2312
"BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
2313
+
"Counter": "2",
2588
2314
"EventCode": "0xB7",
2589
2315
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2590
2316
"MSRIndex": "0x1A6",
···
2595
2319
},
2596
2320
{
2597
2321
"BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
2322
+
"Counter": "2",
2598
2323
"EventCode": "0xB7",
2599
2324
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2600
2325
"MSRIndex": "0x1A6",
···
2605
2328
},
2606
2329
{
2607
2330
"BriefDescription": "All offcore prefetch code reads",
2331
+
"Counter": "2",
2608
2332
"EventCode": "0xB7",
2609
2333
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2610
2334
"MSRIndex": "0x1A6",
···
2615
2337
},
2616
2338
{
2617
2339
"BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
2340
+
"Counter": "2",
2618
2341
"EventCode": "0xB7",
2619
2342
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2620
2343
"MSRIndex": "0x1A6",
···
2625
2346
},
2626
2347
{
2627
2348
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
2349
+
"Counter": "2",
2628
2350
"EventCode": "0xB7",
2629
2351
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2630
2352
"MSRIndex": "0x1A6",
···
2635
2355
},
2636
2356
{
2637
2357
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
2358
+
"Counter": "2",
2638
2359
"EventCode": "0xB7",
2639
2360
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2640
2361
"MSRIndex": "0x1A6",
···
2645
2364
},
2646
2365
{
2647
2366
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
2367
+
"Counter": "2",
2648
2368
"EventCode": "0xB7",
2649
2369
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2650
2370
"MSRIndex": "0x1A6",
···
2655
2373
},
2656
2374
{
2657
2375
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
2376
+
"Counter": "2",
2658
2377
"EventCode": "0xB7",
2659
2378
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2660
2379
"MSRIndex": "0x1A6",
···
2665
2382
},
2666
2383
{
2667
2384
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
2385
+
"Counter": "2",
2668
2386
"EventCode": "0xB7",
2669
2387
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
2670
2388
"MSRIndex": "0x1A6",
···
2675
2391
},
2676
2392
{
2677
2393
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
2394
+
"Counter": "2",
2678
2395
"EventCode": "0xB7",
2679
2396
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
2680
2397
"MSRIndex": "0x1A6",
···
2685
2400
},
2686
2401
{
2687
2402
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
2403
+
"Counter": "2",
2688
2404
"EventCode": "0xB7",
2689
2405
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
2690
2406
"MSRIndex": "0x1A6",
···
2695
2409
},
2696
2410
{
2697
2411
"BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
2412
+
"Counter": "2",
2698
2413
"EventCode": "0xB7",
2699
2414
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
2700
2415
"MSRIndex": "0x1A6",
···
2705
2418
},
2706
2419
{
2707
2420
"BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
2421
+
"Counter": "2",
2708
2422
"EventCode": "0xB7",
2709
2423
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2710
2424
"MSRIndex": "0x1A6",
···
2715
2427
},
2716
2428
{
2717
2429
"BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
2430
+
"Counter": "2",
2718
2431
"EventCode": "0xB7",
2719
2432
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2720
2433
"MSRIndex": "0x1A6",
···
2725
2436
},
2726
2437
{
2727
2438
"BriefDescription": "All offcore prefetch RFO requests",
2439
+
"Counter": "2",
2728
2440
"EventCode": "0xB7",
2729
2441
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2730
2442
"MSRIndex": "0x1A6",
···
2735
2445
},
2736
2446
{
2737
2447
"BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
2448
+
"Counter": "2",
2738
2449
"EventCode": "0xB7",
2739
2450
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2740
2451
"MSRIndex": "0x1A6",
···
2745
2454
},
2746
2455
{
2747
2456
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
2457
+
"Counter": "2",
2748
2458
"EventCode": "0xB7",
2749
2459
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
2750
2460
"MSRIndex": "0x1A6",
···
2755
2463
},
2756
2464
{
2757
2465
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
2466
+
"Counter": "2",
2758
2467
"EventCode": "0xB7",
2759
2468
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
2760
2469
"MSRIndex": "0x1A6",
···
2765
2472
},
2766
2473
{
2767
2474
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
2475
+
"Counter": "2",
2768
2476
"EventCode": "0xB7",
2769
2477
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
2770
2478
"MSRIndex": "0x1A6",
···
2775
2481
},
2776
2482
{
2777
2483
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
2484
+
"Counter": "2",
2778
2485
"EventCode": "0xB7",
2779
2486
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
2780
2487
"MSRIndex": "0x1A6",
···
2785
2490
},
2786
2491
{
2787
2492
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
2493
+
"Counter": "2",
2788
2494
"EventCode": "0xB7",
2789
2495
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
2790
2496
"MSRIndex": "0x1A6",
···
2795
2499
},
2796
2500
{
2797
2501
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
2502
+
"Counter": "2",
2798
2503
"EventCode": "0xB7",
2799
2504
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
2800
2505
"MSRIndex": "0x1A6",
···
2805
2508
},
2806
2509
{
2807
2510
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
2511
+
"Counter": "2",
2808
2512
"EventCode": "0xB7",
2809
2513
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
2810
2514
"MSRIndex": "0x1A6",
···
2815
2517
},
2816
2518
{
2817
2519
"BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
2520
+
"Counter": "2",
2818
2521
"EventCode": "0xB7",
2819
2522
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
2820
2523
"MSRIndex": "0x1A6",
···
2825
2526
},
2826
2527
{
2827
2528
"BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
2529
+
"Counter": "2",
2828
2530
"EventCode": "0xB7",
2829
2531
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
2830
2532
"MSRIndex": "0x1A6",
···
2835
2535
},
2836
2536
{
2837
2537
"BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
2538
+
"Counter": "2",
2838
2539
"EventCode": "0xB7",
2839
2540
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
2840
2541
"MSRIndex": "0x1A6",
···
2845
2544
},
2846
2545
{
2847
2546
"BriefDescription": "All offcore prefetch requests",
2547
+
"Counter": "2",
2848
2548
"EventCode": "0xB7",
2849
2549
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
2850
2550
"MSRIndex": "0x1A6",
···
2855
2553
},
2856
2554
{
2857
2555
"BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
2556
+
"Counter": "2",
2858
2557
"EventCode": "0xB7",
2859
2558
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
2860
2559
"MSRIndex": "0x1A6",
···
2865
2562
},
2866
2563
{
2867
2564
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
2565
+
"Counter": "2",
2868
2566
"EventCode": "0xB7",
2869
2567
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
2870
2568
"MSRIndex": "0x1A6",
···
2875
2571
},
2876
2572
{
2877
2573
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
2574
+
"Counter": "2",
2878
2575
"EventCode": "0xB7",
2879
2576
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
2880
2577
"MSRIndex": "0x1A6",
···
2885
2580
},
2886
2581
{
2887
2582
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
2583
+
"Counter": "2",
2888
2584
"EventCode": "0xB7",
2889
2585
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
2890
2586
"MSRIndex": "0x1A6",
···
2895
2589
},
2896
2590
{
2897
2591
"BriefDescription": "Offcore prefetch requests satisfied by the LLC",
2592
+
"Counter": "2",
2898
2593
"EventCode": "0xB7",
2899
2594
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
2900
2595
"MSRIndex": "0x1A6",
···
2905
2598
},
2906
2599
{
2907
2600
"BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
2601
+
"Counter": "2",
2908
2602
"EventCode": "0xB7",
2909
2603
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
2910
2604
"MSRIndex": "0x1A6",
···
2915
2607
},
2916
2608
{
2917
2609
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
2610
+
"Counter": "2",
2918
2611
"EventCode": "0xB7",
2919
2612
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
2920
2613
"MSRIndex": "0x1A6",
···
2925
2616
},
2926
2617
{
2927
2618
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
2619
+
"Counter": "2",
2928
2620
"EventCode": "0xB7",
2929
2621
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
2930
2622
"MSRIndex": "0x1A6",
···
2935
2625
},
2936
2626
{
2937
2627
"BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
2628
+
"Counter": "2",
2938
2629
"EventCode": "0xB7",
2939
2630
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
2940
2631
"MSRIndex": "0x1A6",
···
2945
2634
},
2946
2635
{
2947
2636
"BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
2637
+
"Counter": "2",
2948
2638
"EventCode": "0xB7",
2949
2639
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
2950
2640
"MSRIndex": "0x1A6",
···
2955
2643
},
2956
2644
{
2957
2645
"BriefDescription": "Super Queue lock splits across a cache line",
2646
+
"Counter": "0,1,2,3",
2958
2647
"EventCode": "0xF4",
2959
2648
"EventName": "SQ_MISC.SPLIT_LOCK",
2960
2649
"SampleAfterValue": "2000000",
···
2963
2650
},
2964
2651
{
2965
2652
"BriefDescription": "Loads delayed with at-Retirement block code",
2653
+
"Counter": "0,1,2,3",
2966
2654
"EventCode": "0x6",
2967
2655
"EventName": "STORE_BLOCKS.AT_RET",
2968
2656
"SampleAfterValue": "200000",
···
2971
2657
},
2972
2658
{
2973
2659
"BriefDescription": "Cacheable loads delayed with L1D block code",
2660
+
"Counter": "0,1,2,3",
2974
2661
"EventCode": "0x6",
2975
2662
"EventName": "STORE_BLOCKS.L1D_BLOCK",
2976
2663
"SampleAfterValue": "200000",
+7
tools/perf/pmu-events/arch/x86/nehalemex/counter.json
+7
tools/perf/pmu-events/arch/x86/nehalemex/counter.json
+28
tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json
+28
tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "X87 Floating point assists (Precise Event)",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xF7",
5
6
"EventName": "FP_ASSIST.ALL",
6
7
"PEBS": "1",
···
10
9
},
11
10
{
12
11
"BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0xF7",
14
14
"EventName": "FP_ASSIST.INPUT",
15
15
"PEBS": "1",
···
19
17
},
20
18
{
21
19
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
20
+
"Counter": "0,1,2,3",
22
21
"EventCode": "0xF7",
23
22
"EventName": "FP_ASSIST.OUTPUT",
24
23
"PEBS": "1",
···
28
25
},
29
26
{
30
27
"BriefDescription": "MMX Uops",
28
+
"Counter": "0,1,2,3",
31
29
"EventCode": "0x10",
32
30
"EventName": "FP_COMP_OPS_EXE.MMX",
33
31
"SampleAfterValue": "2000000",
···
36
32
},
37
33
{
38
34
"BriefDescription": "SSE2 integer Uops",
35
+
"Counter": "0,1,2,3",
39
36
"EventCode": "0x10",
40
37
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
41
38
"SampleAfterValue": "2000000",
···
44
39
},
45
40
{
46
41
"BriefDescription": "SSE* FP double precision Uops",
42
+
"Counter": "0,1,2,3",
47
43
"EventCode": "0x10",
48
44
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
49
45
"SampleAfterValue": "2000000",
···
52
46
},
53
47
{
54
48
"BriefDescription": "SSE and SSE2 FP Uops",
49
+
"Counter": "0,1,2,3",
55
50
"EventCode": "0x10",
56
51
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
57
52
"SampleAfterValue": "2000000",
···
60
53
},
61
54
{
62
55
"BriefDescription": "SSE FP packed Uops",
56
+
"Counter": "0,1,2,3",
63
57
"EventCode": "0x10",
64
58
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
65
59
"SampleAfterValue": "2000000",
···
68
60
},
69
61
{
70
62
"BriefDescription": "SSE FP scalar Uops",
63
+
"Counter": "0,1,2,3",
71
64
"EventCode": "0x10",
72
65
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
73
66
"SampleAfterValue": "2000000",
···
76
67
},
77
68
{
78
69
"BriefDescription": "SSE* FP single precision Uops",
70
+
"Counter": "0,1,2,3",
79
71
"EventCode": "0x10",
80
72
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
81
73
"SampleAfterValue": "2000000",
···
84
74
},
85
75
{
86
76
"BriefDescription": "Computational floating-point operations executed",
77
+
"Counter": "0,1,2,3",
87
78
"EventCode": "0x10",
88
79
"EventName": "FP_COMP_OPS_EXE.X87",
89
80
"SampleAfterValue": "2000000",
···
92
81
},
93
82
{
94
83
"BriefDescription": "All Floating Point to and from MMX transitions",
84
+
"Counter": "0,1,2,3",
95
85
"EventCode": "0xCC",
96
86
"EventName": "FP_MMX_TRANS.ANY",
97
87
"SampleAfterValue": "2000000",
···
100
88
},
101
89
{
102
90
"BriefDescription": "Transitions from MMX to Floating Point instructions",
91
+
"Counter": "0,1,2,3",
103
92
"EventCode": "0xCC",
104
93
"EventName": "FP_MMX_TRANS.TO_FP",
105
94
"SampleAfterValue": "2000000",
···
108
95
},
109
96
{
110
97
"BriefDescription": "Transitions from Floating Point to MMX instructions",
98
+
"Counter": "0,1,2,3",
111
99
"EventCode": "0xCC",
112
100
"EventName": "FP_MMX_TRANS.TO_MMX",
113
101
"SampleAfterValue": "2000000",
···
116
102
},
117
103
{
118
104
"BriefDescription": "128 bit SIMD integer pack operations",
105
+
"Counter": "0,1,2,3",
119
106
"EventCode": "0x12",
120
107
"EventName": "SIMD_INT_128.PACK",
121
108
"SampleAfterValue": "200000",
···
124
109
},
125
110
{
126
111
"BriefDescription": "128 bit SIMD integer arithmetic operations",
112
+
"Counter": "0,1,2,3",
127
113
"EventCode": "0x12",
128
114
"EventName": "SIMD_INT_128.PACKED_ARITH",
129
115
"SampleAfterValue": "200000",
···
132
116
},
133
117
{
134
118
"BriefDescription": "128 bit SIMD integer logical operations",
119
+
"Counter": "0,1,2,3",
135
120
"EventCode": "0x12",
136
121
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
137
122
"SampleAfterValue": "200000",
···
140
123
},
141
124
{
142
125
"BriefDescription": "128 bit SIMD integer multiply operations",
126
+
"Counter": "0,1,2,3",
143
127
"EventCode": "0x12",
144
128
"EventName": "SIMD_INT_128.PACKED_MPY",
145
129
"SampleAfterValue": "200000",
···
148
130
},
149
131
{
150
132
"BriefDescription": "128 bit SIMD integer shift operations",
133
+
"Counter": "0,1,2,3",
151
134
"EventCode": "0x12",
152
135
"EventName": "SIMD_INT_128.PACKED_SHIFT",
153
136
"SampleAfterValue": "200000",
···
156
137
},
157
138
{
158
139
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
140
+
"Counter": "0,1,2,3",
159
141
"EventCode": "0x12",
160
142
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
161
143
"SampleAfterValue": "200000",
···
164
144
},
165
145
{
166
146
"BriefDescription": "128 bit SIMD integer unpack operations",
147
+
"Counter": "0,1,2,3",
167
148
"EventCode": "0x12",
168
149
"EventName": "SIMD_INT_128.UNPACK",
169
150
"SampleAfterValue": "200000",
···
172
151
},
173
152
{
174
153
"BriefDescription": "SIMD integer 64 bit pack operations",
154
+
"Counter": "0,1,2,3",
175
155
"EventCode": "0xFD",
176
156
"EventName": "SIMD_INT_64.PACK",
177
157
"SampleAfterValue": "200000",
···
180
158
},
181
159
{
182
160
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
161
+
"Counter": "0,1,2,3",
183
162
"EventCode": "0xFD",
184
163
"EventName": "SIMD_INT_64.PACKED_ARITH",
185
164
"SampleAfterValue": "200000",
···
188
165
},
189
166
{
190
167
"BriefDescription": "SIMD integer 64 bit logical operations",
168
+
"Counter": "0,1,2,3",
191
169
"EventCode": "0xFD",
192
170
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
193
171
"SampleAfterValue": "200000",
···
196
172
},
197
173
{
198
174
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
175
+
"Counter": "0,1,2,3",
199
176
"EventCode": "0xFD",
200
177
"EventName": "SIMD_INT_64.PACKED_MPY",
201
178
"SampleAfterValue": "200000",
···
204
179
},
205
180
{
206
181
"BriefDescription": "SIMD integer 64 bit shift operations",
182
+
"Counter": "0,1,2,3",
207
183
"EventCode": "0xFD",
208
184
"EventName": "SIMD_INT_64.PACKED_SHIFT",
209
185
"SampleAfterValue": "200000",
···
212
186
},
213
187
{
214
188
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
189
+
"Counter": "0,1,2,3",
215
190
"EventCode": "0xFD",
216
191
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
217
192
"SampleAfterValue": "200000",
···
220
193
},
221
194
{
222
195
"BriefDescription": "SIMD integer 64 bit unpack operations",
196
+
"Counter": "0,1,2,3",
223
197
"EventCode": "0xFD",
224
198
"EventName": "SIMD_INT_64.UNPACK",
225
199
"SampleAfterValue": "200000",
+3
tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
+3
tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Instructions decoded",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xD0",
5
6
"EventName": "MACRO_INSTS.DECODED",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Macro-fused instructions decoded",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0xA6",
13
13
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "Two Uop instructions decoded",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x19",
21
20
"EventName": "TWO_UOP_INSTS_DECODED",
22
21
"SampleAfterValue": "2000000",
+67
tools/perf/pmu-events/arch/x86/nehalemex/memory.json
+67
tools/perf/pmu-events/arch/x86/nehalemex/memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Offcore data reads satisfied by any DRAM",
4
+
"Counter": "2",
4
5
"EventCode": "0xB7",
5
6
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
6
7
"MSRIndex": "0x1A6",
···
11
10
},
12
11
{
13
12
"BriefDescription": "Offcore data reads that missed the LLC",
13
+
"Counter": "2",
14
14
"EventCode": "0xB7",
15
15
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
16
16
"MSRIndex": "0x1A6",
···
21
19
},
22
20
{
23
21
"BriefDescription": "Offcore data reads satisfied by the local DRAM",
22
+
"Counter": "2",
24
23
"EventCode": "0xB7",
25
24
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
26
25
"MSRIndex": "0x1A6",
···
31
28
},
32
29
{
33
30
"BriefDescription": "Offcore data reads satisfied by a remote DRAM",
31
+
"Counter": "2",
34
32
"EventCode": "0xB7",
35
33
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
36
34
"MSRIndex": "0x1A6",
···
41
37
},
42
38
{
43
39
"BriefDescription": "Offcore code reads satisfied by any DRAM",
40
+
"Counter": "2",
44
41
"EventCode": "0xB7",
45
42
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
46
43
"MSRIndex": "0x1A6",
···
51
46
},
52
47
{
53
48
"BriefDescription": "Offcore code reads that missed the LLC",
49
+
"Counter": "2",
54
50
"EventCode": "0xB7",
55
51
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
56
52
"MSRIndex": "0x1A6",
···
61
55
},
62
56
{
63
57
"BriefDescription": "Offcore code reads satisfied by the local DRAM",
58
+
"Counter": "2",
64
59
"EventCode": "0xB7",
65
60
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
66
61
"MSRIndex": "0x1A6",
···
71
64
},
72
65
{
73
66
"BriefDescription": "Offcore code reads satisfied by a remote DRAM",
67
+
"Counter": "2",
74
68
"EventCode": "0xB7",
75
69
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
76
70
"MSRIndex": "0x1A6",
···
81
73
},
82
74
{
83
75
"BriefDescription": "Offcore requests satisfied by any DRAM",
76
+
"Counter": "2",
84
77
"EventCode": "0xB7",
85
78
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
86
79
"MSRIndex": "0x1A6",
···
91
82
},
92
83
{
93
84
"BriefDescription": "Offcore requests that missed the LLC",
85
+
"Counter": "2",
94
86
"EventCode": "0xB7",
95
87
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
96
88
"MSRIndex": "0x1A6",
···
101
91
},
102
92
{
103
93
"BriefDescription": "Offcore requests satisfied by the local DRAM",
94
+
"Counter": "2",
104
95
"EventCode": "0xB7",
105
96
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
106
97
"MSRIndex": "0x1A6",
···
111
100
},
112
101
{
113
102
"BriefDescription": "Offcore requests satisfied by a remote DRAM",
103
+
"Counter": "2",
114
104
"EventCode": "0xB7",
115
105
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
116
106
"MSRIndex": "0x1A6",
···
121
109
},
122
110
{
123
111
"BriefDescription": "Offcore RFO requests satisfied by any DRAM",
112
+
"Counter": "2",
124
113
"EventCode": "0xB7",
125
114
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
126
115
"MSRIndex": "0x1A6",
···
131
118
},
132
119
{
133
120
"BriefDescription": "Offcore RFO requests that missed the LLC",
121
+
"Counter": "2",
134
122
"EventCode": "0xB7",
135
123
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
136
124
"MSRIndex": "0x1A6",
···
141
127
},
142
128
{
143
129
"BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
130
+
"Counter": "2",
144
131
"EventCode": "0xB7",
145
132
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
146
133
"MSRIndex": "0x1A6",
···
151
136
},
152
137
{
153
138
"BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
139
+
"Counter": "2",
154
140
"EventCode": "0xB7",
155
141
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
156
142
"MSRIndex": "0x1A6",
···
161
145
},
162
146
{
163
147
"BriefDescription": "Offcore writebacks to any DRAM",
148
+
"Counter": "2",
164
149
"EventCode": "0xB7",
165
150
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
166
151
"MSRIndex": "0x1A6",
···
171
154
},
172
155
{
173
156
"BriefDescription": "Offcore writebacks that missed the LLC",
157
+
"Counter": "2",
174
158
"EventCode": "0xB7",
175
159
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
176
160
"MSRIndex": "0x1A6",
···
181
163
},
182
164
{
183
165
"BriefDescription": "Offcore writebacks to the local DRAM",
166
+
"Counter": "2",
184
167
"EventCode": "0xB7",
185
168
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
186
169
"MSRIndex": "0x1A6",
···
191
172
},
192
173
{
193
174
"BriefDescription": "Offcore writebacks to a remote DRAM",
175
+
"Counter": "2",
194
176
"EventCode": "0xB7",
195
177
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
196
178
"MSRIndex": "0x1A6",
···
201
181
},
202
182
{
203
183
"BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
184
+
"Counter": "2",
204
185
"EventCode": "0xB7",
205
186
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
206
187
"MSRIndex": "0x1A6",
···
211
190
},
212
191
{
213
192
"BriefDescription": "Offcore code or data read requests that missed the LLC",
193
+
"Counter": "2",
214
194
"EventCode": "0xB7",
215
195
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
216
196
"MSRIndex": "0x1A6",
···
221
199
},
222
200
{
223
201
"BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
202
+
"Counter": "2",
224
203
"EventCode": "0xB7",
225
204
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
226
205
"MSRIndex": "0x1A6",
···
231
208
},
232
209
{
233
210
"BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
211
+
"Counter": "2",
234
212
"EventCode": "0xB7",
235
213
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
236
214
"MSRIndex": "0x1A6",
···
241
217
},
242
218
{
243
219
"BriefDescription": "Offcore request = all data, response = any DRAM",
220
+
"Counter": "2",
244
221
"EventCode": "0xB7",
245
222
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
246
223
"MSRIndex": "0x1A6",
···
251
226
},
252
227
{
253
228
"BriefDescription": "Offcore request = all data, response = any LLC miss",
229
+
"Counter": "2",
254
230
"EventCode": "0xB7",
255
231
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
256
232
"MSRIndex": "0x1A6",
···
261
235
},
262
236
{
263
237
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
238
+
"Counter": "2",
264
239
"EventCode": "0xB7",
265
240
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
266
241
"MSRIndex": "0x1A6",
···
271
244
},
272
245
{
273
246
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
247
+
"Counter": "2",
274
248
"EventCode": "0xB7",
275
249
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
276
250
"MSRIndex": "0x1A6",
···
281
253
},
282
254
{
283
255
"BriefDescription": "Offcore demand data requests satisfied by any DRAM",
256
+
"Counter": "2",
284
257
"EventCode": "0xB7",
285
258
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
286
259
"MSRIndex": "0x1A6",
···
291
262
},
292
263
{
293
264
"BriefDescription": "Offcore demand data requests that missed the LLC",
265
+
"Counter": "2",
294
266
"EventCode": "0xB7",
295
267
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
296
268
"MSRIndex": "0x1A6",
···
301
271
},
302
272
{
303
273
"BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
274
+
"Counter": "2",
304
275
"EventCode": "0xB7",
305
276
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
306
277
"MSRIndex": "0x1A6",
···
311
280
},
312
281
{
313
282
"BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
283
+
"Counter": "2",
314
284
"EventCode": "0xB7",
315
285
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
316
286
"MSRIndex": "0x1A6",
···
321
289
},
322
290
{
323
291
"BriefDescription": "Offcore demand data reads satisfied by any DRAM",
292
+
"Counter": "2",
324
293
"EventCode": "0xB7",
325
294
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
326
295
"MSRIndex": "0x1A6",
···
331
298
},
332
299
{
333
300
"BriefDescription": "Offcore demand data reads that missed the LLC",
301
+
"Counter": "2",
334
302
"EventCode": "0xB7",
335
303
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
336
304
"MSRIndex": "0x1A6",
···
341
307
},
342
308
{
343
309
"BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
310
+
"Counter": "2",
344
311
"EventCode": "0xB7",
345
312
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
346
313
"MSRIndex": "0x1A6",
···
351
316
},
352
317
{
353
318
"BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
319
+
"Counter": "2",
354
320
"EventCode": "0xB7",
355
321
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
356
322
"MSRIndex": "0x1A6",
···
361
325
},
362
326
{
363
327
"BriefDescription": "Offcore demand code reads satisfied by any DRAM",
328
+
"Counter": "2",
364
329
"EventCode": "0xB7",
365
330
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
366
331
"MSRIndex": "0x1A6",
···
371
334
},
372
335
{
373
336
"BriefDescription": "Offcore demand code reads that missed the LLC",
337
+
"Counter": "2",
374
338
"EventCode": "0xB7",
375
339
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
376
340
"MSRIndex": "0x1A6",
···
381
343
},
382
344
{
383
345
"BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
346
+
"Counter": "2",
384
347
"EventCode": "0xB7",
385
348
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
386
349
"MSRIndex": "0x1A6",
···
391
352
},
392
353
{
393
354
"BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
355
+
"Counter": "2",
394
356
"EventCode": "0xB7",
395
357
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
396
358
"MSRIndex": "0x1A6",
···
401
361
},
402
362
{
403
363
"BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
364
+
"Counter": "2",
404
365
"EventCode": "0xB7",
405
366
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
406
367
"MSRIndex": "0x1A6",
···
411
370
},
412
371
{
413
372
"BriefDescription": "Offcore demand RFO requests that missed the LLC",
373
+
"Counter": "2",
414
374
"EventCode": "0xB7",
415
375
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
416
376
"MSRIndex": "0x1A6",
···
421
379
},
422
380
{
423
381
"BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
382
+
"Counter": "2",
424
383
"EventCode": "0xB7",
425
384
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
426
385
"MSRIndex": "0x1A6",
···
431
388
},
432
389
{
433
390
"BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
391
+
"Counter": "2",
434
392
"EventCode": "0xB7",
435
393
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
436
394
"MSRIndex": "0x1A6",
···
441
397
},
442
398
{
443
399
"BriefDescription": "Offcore other requests satisfied by any DRAM",
400
+
"Counter": "2",
444
401
"EventCode": "0xB7",
445
402
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
446
403
"MSRIndex": "0x1A6",
···
451
406
},
452
407
{
453
408
"BriefDescription": "Offcore other requests that missed the LLC",
409
+
"Counter": "2",
454
410
"EventCode": "0xB7",
455
411
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
456
412
"MSRIndex": "0x1A6",
···
461
415
},
462
416
{
463
417
"BriefDescription": "Offcore other requests satisfied by a remote DRAM",
418
+
"Counter": "2",
464
419
"EventCode": "0xB7",
465
420
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
466
421
"MSRIndex": "0x1A6",
···
471
424
},
472
425
{
473
426
"BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
427
+
"Counter": "2",
474
428
"EventCode": "0xB7",
475
429
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
476
430
"MSRIndex": "0x1A6",
···
481
433
},
482
434
{
483
435
"BriefDescription": "Offcore prefetch data requests that missed the LLC",
436
+
"Counter": "2",
484
437
"EventCode": "0xB7",
485
438
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
486
439
"MSRIndex": "0x1A6",
···
491
442
},
492
443
{
493
444
"BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
445
+
"Counter": "2",
494
446
"EventCode": "0xB7",
495
447
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
496
448
"MSRIndex": "0x1A6",
···
501
451
},
502
452
{
503
453
"BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
454
+
"Counter": "2",
504
455
"EventCode": "0xB7",
505
456
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
506
457
"MSRIndex": "0x1A6",
···
511
460
},
512
461
{
513
462
"BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
463
+
"Counter": "2",
514
464
"EventCode": "0xB7",
515
465
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
516
466
"MSRIndex": "0x1A6",
···
521
469
},
522
470
{
523
471
"BriefDescription": "Offcore prefetch data reads that missed the LLC",
472
+
"Counter": "2",
524
473
"EventCode": "0xB7",
525
474
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
526
475
"MSRIndex": "0x1A6",
···
531
478
},
532
479
{
533
480
"BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
481
+
"Counter": "2",
534
482
"EventCode": "0xB7",
535
483
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
536
484
"MSRIndex": "0x1A6",
···
541
487
},
542
488
{
543
489
"BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
490
+
"Counter": "2",
544
491
"EventCode": "0xB7",
545
492
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
546
493
"MSRIndex": "0x1A6",
···
551
496
},
552
497
{
553
498
"BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
499
+
"Counter": "2",
554
500
"EventCode": "0xB7",
555
501
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
556
502
"MSRIndex": "0x1A6",
···
561
505
},
562
506
{
563
507
"BriefDescription": "Offcore prefetch code reads that missed the LLC",
508
+
"Counter": "2",
564
509
"EventCode": "0xB7",
565
510
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
566
511
"MSRIndex": "0x1A6",
···
571
514
},
572
515
{
573
516
"BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
517
+
"Counter": "2",
574
518
"EventCode": "0xB7",
575
519
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
576
520
"MSRIndex": "0x1A6",
···
581
523
},
582
524
{
583
525
"BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
526
+
"Counter": "2",
584
527
"EventCode": "0xB7",
585
528
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
586
529
"MSRIndex": "0x1A6",
···
591
532
},
592
533
{
593
534
"BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
535
+
"Counter": "2",
594
536
"EventCode": "0xB7",
595
537
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
596
538
"MSRIndex": "0x1A6",
···
601
541
},
602
542
{
603
543
"BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
544
+
"Counter": "2",
604
545
"EventCode": "0xB7",
605
546
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
606
547
"MSRIndex": "0x1A6",
···
611
550
},
612
551
{
613
552
"BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
553
+
"Counter": "2",
614
554
"EventCode": "0xB7",
615
555
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
616
556
"MSRIndex": "0x1A6",
···
621
559
},
622
560
{
623
561
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
562
+
"Counter": "2",
624
563
"EventCode": "0xB7",
625
564
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
626
565
"MSRIndex": "0x1A6",
···
631
568
},
632
569
{
633
570
"BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
571
+
"Counter": "2",
634
572
"EventCode": "0xB7",
635
573
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
636
574
"MSRIndex": "0x1A6",
···
641
577
},
642
578
{
643
579
"BriefDescription": "Offcore prefetch requests that missed the LLC",
580
+
"Counter": "2",
644
581
"EventCode": "0xB7",
645
582
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
646
583
"MSRIndex": "0x1A6",
···
651
586
},
652
587
{
653
588
"BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
589
+
"Counter": "2",
654
590
"EventCode": "0xB7",
655
591
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
656
592
"MSRIndex": "0x1A6",
···
661
595
},
662
596
{
663
597
"BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
598
+
"Counter": "2",
664
599
"EventCode": "0xB7",
665
600
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
666
601
"MSRIndex": "0x1A6",
+18
tools/perf/pmu-events/arch/x86/nehalemex/other.json
+18
tools/perf/pmu-events/arch/x86/nehalemex/other.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "ES segment renames",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xD5",
5
6
"EventName": "ES_REG_RENAMES",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "I/O transactions",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0x6C",
13
13
"EventName": "IO_TRANSACTIONS",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "L1I instruction fetch stall cycles",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x80",
21
20
"EventName": "L1I.CYCLES_STALLED",
22
21
"SampleAfterValue": "2000000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "L1I instruction fetch hits",
25
+
"Counter": "0,1,2,3",
28
26
"EventCode": "0x80",
29
27
"EventName": "L1I.HITS",
30
28
"SampleAfterValue": "2000000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "L1I instruction fetch misses",
32
+
"Counter": "0,1,2,3",
36
33
"EventCode": "0x80",
37
34
"EventName": "L1I.MISSES",
38
35
"SampleAfterValue": "2000000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "L1I Instruction fetches",
39
+
"Counter": "0,1,2,3",
44
40
"EventCode": "0x80",
45
41
"EventName": "L1I.READS",
46
42
"SampleAfterValue": "2000000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "Large ITLB hit",
46
+
"Counter": "0,1,2,3",
52
47
"EventCode": "0x82",
53
48
"EventName": "LARGE_ITLB.HIT",
54
49
"SampleAfterValue": "200000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "All loads dispatched",
53
+
"Counter": "0,1,2,3",
60
54
"EventCode": "0x13",
61
55
"EventName": "LOAD_DISPATCH.ANY",
62
56
"SampleAfterValue": "2000000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "Loads dispatched from the MOB",
60
+
"Counter": "0,1,2,3",
68
61
"EventCode": "0x13",
69
62
"EventName": "LOAD_DISPATCH.MOB",
70
63
"SampleAfterValue": "2000000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "Loads dispatched that bypass the MOB",
67
+
"Counter": "0,1,2,3",
76
68
"EventCode": "0x13",
77
69
"EventName": "LOAD_DISPATCH.RS",
78
70
"SampleAfterValue": "2000000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "Loads dispatched from stage 305",
74
+
"Counter": "0,1,2,3",
84
75
"EventCode": "0x13",
85
76
"EventName": "LOAD_DISPATCH.RS_DELAYED",
86
77
"SampleAfterValue": "2000000",
···
89
78
},
90
79
{
91
80
"BriefDescription": "False dependencies due to partial address aliasing",
81
+
"Counter": "0,1,2,3",
92
82
"EventCode": "0x7",
93
83
"EventName": "PARTIAL_ADDRESS_ALIAS",
94
84
"SampleAfterValue": "200000",
···
97
85
},
98
86
{
99
87
"BriefDescription": "All Store buffer stall cycles",
88
+
"Counter": "0,1,2,3",
100
89
"EventCode": "0x4",
101
90
"EventName": "SB_DRAIN.ANY",
102
91
"SampleAfterValue": "200000",
···
105
92
},
106
93
{
107
94
"BriefDescription": "Segment rename stall cycles",
95
+
"Counter": "0,1,2,3",
108
96
"EventCode": "0xD4",
109
97
"EventName": "SEG_RENAME_STALLS",
110
98
"SampleAfterValue": "2000000",
···
113
99
},
114
100
{
115
101
"BriefDescription": "Thread responded HIT to snoop",
102
+
"Counter": "0,1,2,3",
116
103
"EventCode": "0xB8",
117
104
"EventName": "SNOOP_RESPONSE.HIT",
118
105
"SampleAfterValue": "100000",
···
121
106
},
122
107
{
123
108
"BriefDescription": "Thread responded HITE to snoop",
109
+
"Counter": "0,1,2,3",
124
110
"EventCode": "0xB8",
125
111
"EventName": "SNOOP_RESPONSE.HITE",
126
112
"SampleAfterValue": "100000",
···
129
113
},
130
114
{
131
115
"BriefDescription": "Thread responded HITM to snoop",
116
+
"Counter": "0,1,2,3",
132
117
"EventCode": "0xB8",
133
118
"EventName": "SNOOP_RESPONSE.HITM",
134
119
"SampleAfterValue": "100000",
···
137
120
},
138
121
{
139
122
"BriefDescription": "Super Queue full stall cycles",
123
+
"Counter": "0,1,2,3",
140
124
"EventCode": "0xF6",
141
125
"EventName": "SQ_FULL_STALL_CYCLES",
142
126
"SampleAfterValue": "2000000",
+109
tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json
+109
tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles the divider is busy",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x14",
5
6
"EventName": "ARITH.CYCLES_DIV_BUSY",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Divide Operations executed",
11
+
"Counter": "0,1,2,3",
12
12
"CounterMask": "1",
13
13
"EdgeDetect": "1",
14
14
"EventCode": "0x14",
···
20
18
},
21
19
{
22
20
"BriefDescription": "Multiply operations executed",
21
+
"Counter": "0,1,2,3",
23
22
"EventCode": "0x14",
24
23
"EventName": "ARITH.MUL",
25
24
"SampleAfterValue": "2000000",
···
28
25
},
29
26
{
30
27
"BriefDescription": "BACLEAR asserted with bad target address",
28
+
"Counter": "0,1,2,3",
31
29
"EventCode": "0xE6",
32
30
"EventName": "BACLEAR.BAD_TARGET",
33
31
"SampleAfterValue": "2000000",
···
36
32
},
37
33
{
38
34
"BriefDescription": "BACLEAR asserted, regardless of cause",
35
+
"Counter": "0,1,2,3",
39
36
"EventCode": "0xE6",
40
37
"EventName": "BACLEAR.CLEAR",
41
38
"SampleAfterValue": "2000000",
···
44
39
},
45
40
{
46
41
"BriefDescription": "Instruction queue forced BACLEAR",
42
+
"Counter": "0,1,2,3",
47
43
"EventCode": "0xA7",
48
44
"EventName": "BACLEAR_FORCE_IQ",
49
45
"SampleAfterValue": "2000000",
···
52
46
},
53
47
{
54
48
"BriefDescription": "Early Branch Prediciton Unit clears",
49
+
"Counter": "0,1,2,3",
55
50
"EventCode": "0xE8",
56
51
"EventName": "BPU_CLEARS.EARLY",
57
52
"SampleAfterValue": "2000000",
···
60
53
},
61
54
{
62
55
"BriefDescription": "Late Branch Prediction Unit clears",
56
+
"Counter": "0,1,2,3",
63
57
"EventCode": "0xE8",
64
58
"EventName": "BPU_CLEARS.LATE",
65
59
"SampleAfterValue": "2000000",
···
68
60
},
69
61
{
70
62
"BriefDescription": "Branch prediction unit missed call or return",
63
+
"Counter": "0,1,2,3",
71
64
"EventCode": "0xE5",
72
65
"EventName": "BPU_MISSED_CALL_RET",
73
66
"SampleAfterValue": "2000000",
···
76
67
},
77
68
{
78
69
"BriefDescription": "Branch instructions decoded",
70
+
"Counter": "0,1,2,3",
79
71
"EventCode": "0xE0",
80
72
"EventName": "BR_INST_DECODED",
81
73
"SampleAfterValue": "2000000",
···
84
74
},
85
75
{
86
76
"BriefDescription": "Branch instructions executed",
77
+
"Counter": "0,1,2,3",
87
78
"EventCode": "0x88",
88
79
"EventName": "BR_INST_EXEC.ANY",
89
80
"SampleAfterValue": "200000",
···
92
81
},
93
82
{
94
83
"BriefDescription": "Conditional branch instructions executed",
84
+
"Counter": "0,1,2,3",
95
85
"EventCode": "0x88",
96
86
"EventName": "BR_INST_EXEC.COND",
97
87
"SampleAfterValue": "200000",
···
100
88
},
101
89
{
102
90
"BriefDescription": "Unconditional branches executed",
91
+
"Counter": "0,1,2,3",
103
92
"EventCode": "0x88",
104
93
"EventName": "BR_INST_EXEC.DIRECT",
105
94
"SampleAfterValue": "200000",
···
108
95
},
109
96
{
110
97
"BriefDescription": "Unconditional call branches executed",
98
+
"Counter": "0,1,2,3",
111
99
"EventCode": "0x88",
112
100
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
113
101
"SampleAfterValue": "20000",
···
116
102
},
117
103
{
118
104
"BriefDescription": "Indirect call branches executed",
105
+
"Counter": "0,1,2,3",
119
106
"EventCode": "0x88",
120
107
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
121
108
"SampleAfterValue": "20000",
···
124
109
},
125
110
{
126
111
"BriefDescription": "Indirect non call branches executed",
112
+
"Counter": "0,1,2,3",
127
113
"EventCode": "0x88",
128
114
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
129
115
"SampleAfterValue": "20000",
···
132
116
},
133
117
{
134
118
"BriefDescription": "Call branches executed",
119
+
"Counter": "0,1,2,3",
135
120
"EventCode": "0x88",
136
121
"EventName": "BR_INST_EXEC.NEAR_CALLS",
137
122
"SampleAfterValue": "20000",
···
140
123
},
141
124
{
142
125
"BriefDescription": "All non call branches executed",
126
+
"Counter": "0,1,2,3",
143
127
"EventCode": "0x88",
144
128
"EventName": "BR_INST_EXEC.NON_CALLS",
145
129
"SampleAfterValue": "200000",
···
148
130
},
149
131
{
150
132
"BriefDescription": "Indirect return branches executed",
133
+
"Counter": "0,1,2,3",
151
134
"EventCode": "0x88",
152
135
"EventName": "BR_INST_EXEC.RETURN_NEAR",
153
136
"SampleAfterValue": "20000",
···
156
137
},
157
138
{
158
139
"BriefDescription": "Taken branches executed",
140
+
"Counter": "0,1,2,3",
159
141
"EventCode": "0x88",
160
142
"EventName": "BR_INST_EXEC.TAKEN",
161
143
"SampleAfterValue": "200000",
···
164
144
},
165
145
{
166
146
"BriefDescription": "Retired branch instructions (Precise Event)",
147
+
"Counter": "0,1,2,3",
167
148
"EventCode": "0xC4",
168
149
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
169
150
"PEBS": "1",
···
173
152
},
174
153
{
175
154
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
155
+
"Counter": "0,1,2,3",
176
156
"EventCode": "0xC4",
177
157
"EventName": "BR_INST_RETIRED.CONDITIONAL",
178
158
"PEBS": "1",
···
182
160
},
183
161
{
184
162
"BriefDescription": "Retired near call instructions (Precise Event)",
163
+
"Counter": "0,1,2,3",
185
164
"EventCode": "0xC4",
186
165
"EventName": "BR_INST_RETIRED.NEAR_CALL",
187
166
"PEBS": "1",
···
191
168
},
192
169
{
193
170
"BriefDescription": "Mispredicted branches executed",
171
+
"Counter": "0,1,2,3",
194
172
"EventCode": "0x89",
195
173
"EventName": "BR_MISP_EXEC.ANY",
196
174
"SampleAfterValue": "20000",
···
199
175
},
200
176
{
201
177
"BriefDescription": "Mispredicted conditional branches executed",
178
+
"Counter": "0,1,2,3",
202
179
"EventCode": "0x89",
203
180
"EventName": "BR_MISP_EXEC.COND",
204
181
"SampleAfterValue": "20000",
···
207
182
},
208
183
{
209
184
"BriefDescription": "Mispredicted unconditional branches executed",
185
+
"Counter": "0,1,2,3",
210
186
"EventCode": "0x89",
211
187
"EventName": "BR_MISP_EXEC.DIRECT",
212
188
"SampleAfterValue": "20000",
···
215
189
},
216
190
{
217
191
"BriefDescription": "Mispredicted non call branches executed",
192
+
"Counter": "0,1,2,3",
218
193
"EventCode": "0x89",
219
194
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
220
195
"SampleAfterValue": "2000",
···
223
196
},
224
197
{
225
198
"BriefDescription": "Mispredicted indirect call branches executed",
199
+
"Counter": "0,1,2,3",
226
200
"EventCode": "0x89",
227
201
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
228
202
"SampleAfterValue": "2000",
···
231
203
},
232
204
{
233
205
"BriefDescription": "Mispredicted indirect non call branches executed",
206
+
"Counter": "0,1,2,3",
234
207
"EventCode": "0x89",
235
208
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
236
209
"SampleAfterValue": "2000",
···
239
210
},
240
211
{
241
212
"BriefDescription": "Mispredicted call branches executed",
213
+
"Counter": "0,1,2,3",
242
214
"EventCode": "0x89",
243
215
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
244
216
"SampleAfterValue": "2000",
···
247
217
},
248
218
{
249
219
"BriefDescription": "Mispredicted non call branches executed",
220
+
"Counter": "0,1,2,3",
250
221
"EventCode": "0x89",
251
222
"EventName": "BR_MISP_EXEC.NON_CALLS",
252
223
"SampleAfterValue": "20000",
···
255
224
},
256
225
{
257
226
"BriefDescription": "Mispredicted return branches executed",
227
+
"Counter": "0,1,2,3",
258
228
"EventCode": "0x89",
259
229
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
260
230
"SampleAfterValue": "2000",
···
263
231
},
264
232
{
265
233
"BriefDescription": "Mispredicted taken branches executed",
234
+
"Counter": "0,1,2,3",
266
235
"EventCode": "0x89",
267
236
"EventName": "BR_MISP_EXEC.TAKEN",
268
237
"SampleAfterValue": "20000",
···
271
238
},
272
239
{
273
240
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
241
+
"Counter": "0,1,2,3",
274
242
"EventCode": "0xC5",
275
243
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
276
244
"PEBS": "1",
···
280
246
},
281
247
{
282
248
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
249
+
"Counter": "Fixed counter 3",
283
250
"EventName": "CPU_CLK_UNHALTED.REF",
284
251
"SampleAfterValue": "2000000"
285
252
},
286
253
{
287
254
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
255
+
"Counter": "0,1,2,3",
288
256
"EventCode": "0x3C",
289
257
"EventName": "CPU_CLK_UNHALTED.REF_P",
290
258
"SampleAfterValue": "100000",
···
294
258
},
295
259
{
296
260
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
261
+
"Counter": "Fixed counter 2",
297
262
"EventName": "CPU_CLK_UNHALTED.THREAD",
298
263
"SampleAfterValue": "2000000"
299
264
},
300
265
{
301
266
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
267
+
"Counter": "0,1,2,3",
302
268
"EventCode": "0x3C",
303
269
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
304
270
"SampleAfterValue": "2000000"
305
271
},
306
272
{
307
273
"BriefDescription": "Total CPU cycles",
274
+
"Counter": "0,1,2,3",
308
275
"CounterMask": "2",
309
276
"EventCode": "0x3C",
310
277
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
···
316
277
},
317
278
{
318
279
"BriefDescription": "Any Instruction Length Decoder stall cycles",
280
+
"Counter": "0,1,2,3",
319
281
"EventCode": "0x87",
320
282
"EventName": "ILD_STALL.ANY",
321
283
"SampleAfterValue": "2000000",
···
324
284
},
325
285
{
326
286
"BriefDescription": "Instruction Queue full stall cycles",
287
+
"Counter": "0,1,2,3",
327
288
"EventCode": "0x87",
328
289
"EventName": "ILD_STALL.IQ_FULL",
329
290
"SampleAfterValue": "2000000",
···
332
291
},
333
292
{
334
293
"BriefDescription": "Length Change Prefix stall cycles",
294
+
"Counter": "0,1,2,3",
335
295
"EventCode": "0x87",
336
296
"EventName": "ILD_STALL.LCP",
337
297
"SampleAfterValue": "2000000",
···
340
298
},
341
299
{
342
300
"BriefDescription": "Stall cycles due to BPU MRU bypass",
301
+
"Counter": "0,1,2,3",
343
302
"EventCode": "0x87",
344
303
"EventName": "ILD_STALL.MRU",
345
304
"SampleAfterValue": "2000000",
···
348
305
},
349
306
{
350
307
"BriefDescription": "Regen stall cycles",
308
+
"Counter": "0,1,2,3",
351
309
"EventCode": "0x87",
352
310
"EventName": "ILD_STALL.REGEN",
353
311
"SampleAfterValue": "2000000",
···
356
312
},
357
313
{
358
314
"BriefDescription": "Instructions that must be decoded by decoder 0",
315
+
"Counter": "0,1,2,3",
359
316
"EventCode": "0x18",
360
317
"EventName": "INST_DECODED.DEC0",
361
318
"SampleAfterValue": "2000000",
···
364
319
},
365
320
{
366
321
"BriefDescription": "Instructions written to instruction queue.",
322
+
"Counter": "0,1,2,3",
367
323
"EventCode": "0x17",
368
324
"EventName": "INST_QUEUE_WRITES",
369
325
"SampleAfterValue": "2000000",
···
372
326
},
373
327
{
374
328
"BriefDescription": "Cycles instructions are written to the instruction queue",
329
+
"Counter": "0,1,2,3",
375
330
"EventCode": "0x1E",
376
331
"EventName": "INST_QUEUE_WRITE_CYCLES",
377
332
"SampleAfterValue": "2000000",
···
380
333
},
381
334
{
382
335
"BriefDescription": "Instructions retired (fixed counter)",
336
+
"Counter": "Fixed counter 1",
383
337
"EventName": "INST_RETIRED.ANY",
384
338
"SampleAfterValue": "2000000"
385
339
},
386
340
{
387
341
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
342
+
"Counter": "0,1,2,3",
388
343
"EventCode": "0xC0",
389
344
"EventName": "INST_RETIRED.ANY_P",
390
345
"PEBS": "1",
···
395
346
},
396
347
{
397
348
"BriefDescription": "Retired MMX instructions (Precise Event)",
349
+
"Counter": "0,1,2,3",
398
350
"EventCode": "0xC0",
399
351
"EventName": "INST_RETIRED.MMX",
400
352
"PEBS": "1",
···
404
354
},
405
355
{
406
356
"BriefDescription": "Total cycles (Precise Event)",
357
+
"Counter": "0,1,2,3",
407
358
"CounterMask": "16",
408
359
"EventCode": "0xC0",
409
360
"EventName": "INST_RETIRED.TOTAL_CYCLES",
···
415
364
},
416
365
{
417
366
"BriefDescription": "Total cycles (Precise Event)",
367
+
"Counter": "0,1,2,3",
418
368
"CounterMask": "16",
419
369
"EventCode": "0xC0",
420
370
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
···
426
374
},
427
375
{
428
376
"BriefDescription": "Retired floating-point operations (Precise Event)",
377
+
"Counter": "0,1,2,3",
429
378
"EventCode": "0xC0",
430
379
"EventName": "INST_RETIRED.X87",
431
380
"PEBS": "1",
···
435
382
},
436
383
{
437
384
"BriefDescription": "Load operations conflicting with software prefetches",
385
+
"Counter": "0,1",
438
386
"EventCode": "0x4C",
439
387
"EventName": "LOAD_HIT_PRE",
440
388
"SampleAfterValue": "200000",
···
443
389
},
444
390
{
445
391
"BriefDescription": "Cycles when uops were delivered by the LSD",
392
+
"Counter": "0,1,2,3",
446
393
"CounterMask": "1",
447
394
"EventCode": "0xA8",
448
395
"EventName": "LSD.ACTIVE",
···
452
397
},
453
398
{
454
399
"BriefDescription": "Cycles no uops were delivered by the LSD",
400
+
"Counter": "0,1,2,3",
455
401
"CounterMask": "1",
456
402
"EventCode": "0xA8",
457
403
"EventName": "LSD.INACTIVE",
···
462
406
},
463
407
{
464
408
"BriefDescription": "Loops that can't stream from the instruction queue",
409
+
"Counter": "0,1,2,3",
465
410
"EventCode": "0x20",
466
411
"EventName": "LSD_OVERFLOW",
467
412
"SampleAfterValue": "2000000",
···
470
413
},
471
414
{
472
415
"BriefDescription": "Cycles machine clear asserted",
416
+
"Counter": "0,1,2,3",
473
417
"EventCode": "0xC3",
474
418
"EventName": "MACHINE_CLEARS.CYCLES",
475
419
"SampleAfterValue": "20000",
···
478
420
},
479
421
{
480
422
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
423
+
"Counter": "0,1,2,3",
481
424
"EventCode": "0xC3",
482
425
"EventName": "MACHINE_CLEARS.MEM_ORDER",
483
426
"SampleAfterValue": "20000",
···
486
427
},
487
428
{
488
429
"BriefDescription": "Self-Modifying Code detected",
430
+
"Counter": "0,1,2,3",
489
431
"EventCode": "0xC3",
490
432
"EventName": "MACHINE_CLEARS.SMC",
491
433
"SampleAfterValue": "20000",
···
494
434
},
495
435
{
496
436
"BriefDescription": "All RAT stall cycles",
437
+
"Counter": "0,1,2,3",
497
438
"EventCode": "0xD2",
498
439
"EventName": "RAT_STALLS.ANY",
499
440
"SampleAfterValue": "2000000",
···
502
441
},
503
442
{
504
443
"BriefDescription": "Flag stall cycles",
444
+
"Counter": "0,1,2,3",
505
445
"EventCode": "0xD2",
506
446
"EventName": "RAT_STALLS.FLAGS",
507
447
"SampleAfterValue": "2000000",
···
510
448
},
511
449
{
512
450
"BriefDescription": "Partial register stall cycles",
451
+
"Counter": "0,1,2,3",
513
452
"EventCode": "0xD2",
514
453
"EventName": "RAT_STALLS.REGISTERS",
515
454
"SampleAfterValue": "2000000",
···
518
455
},
519
456
{
520
457
"BriefDescription": "ROB read port stalls cycles",
458
+
"Counter": "0,1,2,3",
521
459
"EventCode": "0xD2",
522
460
"EventName": "RAT_STALLS.ROB_READ_PORT",
523
461
"SampleAfterValue": "2000000",
···
526
462
},
527
463
{
528
464
"BriefDescription": "Scoreboard stall cycles",
465
+
"Counter": "0,1,2,3",
529
466
"EventCode": "0xD2",
530
467
"EventName": "RAT_STALLS.SCOREBOARD",
531
468
"SampleAfterValue": "2000000",
···
534
469
},
535
470
{
536
471
"BriefDescription": "Resource related stall cycles",
472
+
"Counter": "0,1,2,3",
537
473
"EventCode": "0xA2",
538
474
"EventName": "RESOURCE_STALLS.ANY",
539
475
"SampleAfterValue": "2000000",
···
542
476
},
543
477
{
544
478
"BriefDescription": "FPU control word write stall cycles",
479
+
"Counter": "0,1,2,3",
545
480
"EventCode": "0xA2",
546
481
"EventName": "RESOURCE_STALLS.FPCW",
547
482
"SampleAfterValue": "2000000",
···
550
483
},
551
484
{
552
485
"BriefDescription": "Load buffer stall cycles",
486
+
"Counter": "0,1,2,3",
553
487
"EventCode": "0xA2",
554
488
"EventName": "RESOURCE_STALLS.LOAD",
555
489
"SampleAfterValue": "2000000",
···
558
490
},
559
491
{
560
492
"BriefDescription": "MXCSR rename stall cycles",
493
+
"Counter": "0,1,2,3",
561
494
"EventCode": "0xA2",
562
495
"EventName": "RESOURCE_STALLS.MXCSR",
563
496
"SampleAfterValue": "2000000",
···
566
497
},
567
498
{
568
499
"BriefDescription": "Other Resource related stall cycles",
500
+
"Counter": "0,1,2,3",
569
501
"EventCode": "0xA2",
570
502
"EventName": "RESOURCE_STALLS.OTHER",
571
503
"SampleAfterValue": "2000000",
···
574
504
},
575
505
{
576
506
"BriefDescription": "ROB full stall cycles",
507
+
"Counter": "0,1,2,3",
577
508
"EventCode": "0xA2",
578
509
"EventName": "RESOURCE_STALLS.ROB_FULL",
579
510
"SampleAfterValue": "2000000",
···
582
511
},
583
512
{
584
513
"BriefDescription": "Reservation Station full stall cycles",
514
+
"Counter": "0,1,2,3",
585
515
"EventCode": "0xA2",
586
516
"EventName": "RESOURCE_STALLS.RS_FULL",
587
517
"SampleAfterValue": "2000000",
···
590
518
},
591
519
{
592
520
"BriefDescription": "Store buffer stall cycles",
521
+
"Counter": "0,1,2,3",
593
522
"EventCode": "0xA2",
594
523
"EventName": "RESOURCE_STALLS.STORE",
595
524
"SampleAfterValue": "2000000",
···
598
525
},
599
526
{
600
527
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
528
+
"Counter": "0,1,2,3",
601
529
"EventCode": "0xC7",
602
530
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
603
531
"PEBS": "1",
···
607
533
},
608
534
{
609
535
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
536
+
"Counter": "0,1,2,3",
610
537
"EventCode": "0xC7",
611
538
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
612
539
"PEBS": "1",
···
616
541
},
617
542
{
618
543
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
544
+
"Counter": "0,1,2,3",
619
545
"EventCode": "0xC7",
620
546
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
621
547
"PEBS": "1",
···
625
549
},
626
550
{
627
551
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
552
+
"Counter": "0,1,2,3",
628
553
"EventCode": "0xC7",
629
554
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
630
555
"PEBS": "1",
···
634
557
},
635
558
{
636
559
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
560
+
"Counter": "0,1,2,3",
637
561
"EventCode": "0xC7",
638
562
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
639
563
"PEBS": "1",
···
643
565
},
644
566
{
645
567
"BriefDescription": "Stack pointer instructions decoded",
568
+
"Counter": "0,1,2,3",
646
569
"EventCode": "0xD1",
647
570
"EventName": "UOPS_DECODED.ESP_FOLDING",
648
571
"SampleAfterValue": "2000000",
···
651
572
},
652
573
{
653
574
"BriefDescription": "Stack pointer sync operations",
575
+
"Counter": "0,1,2,3",
654
576
"EventCode": "0xD1",
655
577
"EventName": "UOPS_DECODED.ESP_SYNC",
656
578
"SampleAfterValue": "2000000",
···
659
579
},
660
580
{
661
581
"BriefDescription": "Uops decoded by Microcode Sequencer",
582
+
"Counter": "0,1,2,3",
662
583
"CounterMask": "1",
663
584
"EventCode": "0xD1",
664
585
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
···
668
587
},
669
588
{
670
589
"BriefDescription": "Cycles no Uops are decoded",
590
+
"Counter": "0,1,2,3",
671
591
"CounterMask": "1",
672
592
"EventCode": "0xD1",
673
593
"EventName": "UOPS_DECODED.STALL_CYCLES",
···
679
597
{
680
598
"AnyThread": "1",
681
599
"BriefDescription": "Cycles Uops executed on any port (core count)",
600
+
"Counter": "0,1,2,3",
682
601
"CounterMask": "1",
683
602
"EventCode": "0xB1",
684
603
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
···
689
606
{
690
607
"AnyThread": "1",
691
608
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
609
+
"Counter": "0,1,2,3",
692
610
"CounterMask": "1",
693
611
"EventCode": "0xB1",
694
612
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
···
699
615
{
700
616
"AnyThread": "1",
701
617
"BriefDescription": "Uops executed on any port (core count)",
618
+
"Counter": "0,1,2,3",
702
619
"CounterMask": "1",
703
620
"EdgeDetect": "1",
704
621
"EventCode": "0xB1",
···
711
626
{
712
627
"AnyThread": "1",
713
628
"BriefDescription": "Uops executed on ports 0-4 (core count)",
629
+
"Counter": "0,1,2,3",
714
630
"CounterMask": "1",
715
631
"EdgeDetect": "1",
716
632
"EventCode": "0xB1",
···
723
637
{
724
638
"AnyThread": "1",
725
639
"BriefDescription": "Cycles no Uops issued on any port (core count)",
640
+
"Counter": "0,1,2,3",
726
641
"CounterMask": "1",
727
642
"EventCode": "0xB1",
728
643
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
···
734
647
{
735
648
"AnyThread": "1",
736
649
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
650
+
"Counter": "0,1,2,3",
737
651
"CounterMask": "1",
738
652
"EventCode": "0xB1",
739
653
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
···
744
656
},
745
657
{
746
658
"BriefDescription": "Uops executed on port 0",
659
+
"Counter": "0,1,2,3",
747
660
"EventCode": "0xB1",
748
661
"EventName": "UOPS_EXECUTED.PORT0",
749
662
"SampleAfterValue": "2000000",
···
752
663
},
753
664
{
754
665
"BriefDescription": "Uops issued on ports 0, 1 or 5",
666
+
"Counter": "0,1,2,3",
755
667
"EventCode": "0xB1",
756
668
"EventName": "UOPS_EXECUTED.PORT015",
757
669
"SampleAfterValue": "2000000",
···
760
670
},
761
671
{
762
672
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
673
+
"Counter": "0,1,2,3",
763
674
"CounterMask": "1",
764
675
"EventCode": "0xB1",
765
676
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
···
770
679
},
771
680
{
772
681
"BriefDescription": "Uops executed on port 1",
682
+
"Counter": "0,1,2,3",
773
683
"EventCode": "0xB1",
774
684
"EventName": "UOPS_EXECUTED.PORT1",
775
685
"SampleAfterValue": "2000000",
···
779
687
{
780
688
"AnyThread": "1",
781
689
"BriefDescription": "Uops issued on ports 2, 3 or 4",
690
+
"Counter": "0,1,2,3",
782
691
"EventCode": "0xB1",
783
692
"EventName": "UOPS_EXECUTED.PORT234_CORE",
784
693
"SampleAfterValue": "2000000",
···
788
695
{
789
696
"AnyThread": "1",
790
697
"BriefDescription": "Uops executed on port 2 (core count)",
698
+
"Counter": "0,1,2,3",
791
699
"EventCode": "0xB1",
792
700
"EventName": "UOPS_EXECUTED.PORT2_CORE",
793
701
"SampleAfterValue": "2000000",
···
797
703
{
798
704
"AnyThread": "1",
799
705
"BriefDescription": "Uops executed on port 3 (core count)",
706
+
"Counter": "0,1,2,3",
800
707
"EventCode": "0xB1",
801
708
"EventName": "UOPS_EXECUTED.PORT3_CORE",
802
709
"SampleAfterValue": "2000000",
···
806
711
{
807
712
"AnyThread": "1",
808
713
"BriefDescription": "Uops executed on port 4 (core count)",
714
+
"Counter": "0,1,2,3",
809
715
"EventCode": "0xB1",
810
716
"EventName": "UOPS_EXECUTED.PORT4_CORE",
811
717
"SampleAfterValue": "2000000",
···
814
718
},
815
719
{
816
720
"BriefDescription": "Uops executed on port 5",
721
+
"Counter": "0,1,2,3",
817
722
"EventCode": "0xB1",
818
723
"EventName": "UOPS_EXECUTED.PORT5",
819
724
"SampleAfterValue": "2000000",
···
822
725
},
823
726
{
824
727
"BriefDescription": "Uops issued",
728
+
"Counter": "0,1,2,3",
825
729
"EventCode": "0xE",
826
730
"EventName": "UOPS_ISSUED.ANY",
827
731
"SampleAfterValue": "2000000",
···
831
733
{
832
734
"AnyThread": "1",
833
735
"BriefDescription": "Cycles no Uops were issued on any thread",
736
+
"Counter": "0,1,2,3",
834
737
"CounterMask": "1",
835
738
"EventCode": "0xE",
836
739
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
···
842
743
{
843
744
"AnyThread": "1",
844
745
"BriefDescription": "Cycles Uops were issued on either thread",
746
+
"Counter": "0,1,2,3",
845
747
"CounterMask": "1",
846
748
"EventCode": "0xE",
847
749
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
···
851
751
},
852
752
{
853
753
"BriefDescription": "Fused Uops issued",
754
+
"Counter": "0,1,2,3",
854
755
"EventCode": "0xE",
855
756
"EventName": "UOPS_ISSUED.FUSED",
856
757
"SampleAfterValue": "2000000",
···
859
758
},
860
759
{
861
760
"BriefDescription": "Cycles no Uops were issued",
761
+
"Counter": "0,1,2,3",
862
762
"CounterMask": "1",
863
763
"EventCode": "0xE",
864
764
"EventName": "UOPS_ISSUED.STALL_CYCLES",
···
869
767
},
870
768
{
871
769
"BriefDescription": "Cycles Uops are being retired",
770
+
"Counter": "0,1,2,3",
872
771
"CounterMask": "1",
873
772
"EventCode": "0xC2",
874
773
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
···
879
776
},
880
777
{
881
778
"BriefDescription": "Uops retired (Precise Event)",
779
+
"Counter": "0,1,2,3",
882
780
"EventCode": "0xC2",
883
781
"EventName": "UOPS_RETIRED.ANY",
884
782
"PEBS": "1",
···
888
784
},
889
785
{
890
786
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
787
+
"Counter": "0,1,2,3",
891
788
"EventCode": "0xC2",
892
789
"EventName": "UOPS_RETIRED.MACRO_FUSED",
893
790
"PEBS": "1",
···
897
792
},
898
793
{
899
794
"BriefDescription": "Retirement slots used (Precise Event)",
795
+
"Counter": "0,1,2,3",
900
796
"EventCode": "0xC2",
901
797
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
902
798
"PEBS": "1",
···
906
800
},
907
801
{
908
802
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
803
+
"Counter": "0,1,2,3",
909
804
"CounterMask": "1",
910
805
"EventCode": "0xC2",
911
806
"EventName": "UOPS_RETIRED.STALL_CYCLES",
···
917
810
},
918
811
{
919
812
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
813
+
"Counter": "0,1,2,3",
920
814
"CounterMask": "16",
921
815
"EventCode": "0xC2",
922
816
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
···
928
820
},
929
821
{
930
822
"BriefDescription": "Uop unfusions due to FP exceptions",
823
+
"Counter": "0,1,2,3",
931
824
"EventCode": "0xDB",
932
825
"EventName": "UOP_UNFUSION",
933
826
"SampleAfterValue": "2000000",
+13
tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
+13
tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "DTLB load misses",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x8",
5
6
"EventName": "DTLB_LOAD_MISSES.ANY",
6
7
"SampleAfterValue": "200000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "DTLB load miss caused by low part of address",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0x8",
13
13
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
14
14
"SampleAfterValue": "200000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "DTLB second level hit",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x8",
21
20
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
22
21
"SampleAfterValue": "2000000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "DTLB load miss page walks complete",
25
+
"Counter": "0,1,2,3",
28
26
"EventCode": "0x8",
29
27
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
30
28
"SampleAfterValue": "200000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "DTLB misses",
32
+
"Counter": "0,1,2,3",
36
33
"EventCode": "0x49",
37
34
"EventName": "DTLB_MISSES.ANY",
38
35
"SampleAfterValue": "200000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "DTLB first level misses but second level hit",
39
+
"Counter": "0,1,2,3",
44
40
"EventCode": "0x49",
45
41
"EventName": "DTLB_MISSES.STLB_HIT",
46
42
"SampleAfterValue": "200000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "DTLB miss page walks",
46
+
"Counter": "0,1,2,3",
52
47
"EventCode": "0x49",
53
48
"EventName": "DTLB_MISSES.WALK_COMPLETED",
54
49
"SampleAfterValue": "200000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "ITLB flushes",
53
+
"Counter": "0,1,2,3",
60
54
"EventCode": "0xAE",
61
55
"EventName": "ITLB_FLUSH",
62
56
"SampleAfterValue": "2000000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "ITLB miss",
60
+
"Counter": "0,1,2,3",
68
61
"EventCode": "0x85",
69
62
"EventName": "ITLB_MISSES.ANY",
70
63
"SampleAfterValue": "200000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "ITLB miss page walks",
67
+
"Counter": "0,1,2,3",
76
68
"EventCode": "0x85",
77
69
"EventName": "ITLB_MISSES.WALK_COMPLETED",
78
70
"SampleAfterValue": "200000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
74
+
"Counter": "0,1,2,3",
84
75
"EventCode": "0xC8",
85
76
"EventName": "ITLB_MISS_RETIRED",
86
77
"PEBS": "1",
···
90
79
},
91
80
{
92
81
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
82
+
"Counter": "0,1,2,3",
93
83
"EventCode": "0xCB",
94
84
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
95
85
"PEBS": "1",
···
99
87
},
100
88
{
101
89
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
90
+
"Counter": "0,1,2,3",
102
91
"EventCode": "0xC",
103
92
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
104
93
"PEBS": "1",