Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'sunxi-dt-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Allwinner device tree changes for 6.20
Not many changes this cycle.
- The A523 family of SoCs gained support for SPI controllers.
- Some cleanup of old ARM device tree files to fix DT binding validation
errors.
- D1 and A100 SoCs gained support for their LED controller. This was
from a couple years ago. The driver made it in, but the DT patches
were missed.
- D1 and T113 SoCs gained support for the internal thermal sensor.
* tag 'sunxi-dt-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
riscv: dts: allwinner: d1: Add CPU thermal sensor and zone
ARM: dts: allwinner: Replace status "failed" with "fail"
riscv: dts: allwinner: d1: Add RGB LEDs to boards
riscv: dts: allwinner: d1: Add LED controller node
arm64: dts: allwinner: a100: Add LED controller node
ARM: dts: allwinner: sun5i-a13-utoo-p66: delete "power-gpios" property
arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash
arm64: dts: allwinner: sun55i: Add SPI controllers
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+254
-4
+1
-1
arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts
+1
-1
arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts
+1
-1
arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts
+1
-1
arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts
+1
arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts
+1
arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts
···
102
102
/* The P66 uses a different EINT then the reference design */
103
103
interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
104
104
/* The icn8318 binding expects wake-gpios instead of power-gpios */
105
+
/delete-property/ power-gpios;
105
106
wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
106
107
touchscreen-size-x = <800>;
107
108
touchscreen-size-y = <480>;
+1
-1
arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts
+1
-1
arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts
+1
-1
arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts
+1
-1
arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts
+33
arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi
+33
arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi
···
4
4
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
5
5
6
6
#include <dt-bindings/interrupt-controller/arm-gic.h>
7
+
#include <dt-bindings/thermal/thermal.h>
7
8
#include <riscv/allwinner/sunxi-d1s-t113.dtsi>
8
9
#include <riscv/allwinner/sunxi-d1-t113.dtsi>
9
10
···
21
20
reg = <0>;
22
21
clocks = <&ccu CLK_CPUX>;
23
22
clock-names = "cpu";
23
+
#cooling-cells = <2>;
24
24
};
25
25
26
26
cpu1: cpu@1 {
···
30
28
reg = <1>;
31
29
clocks = <&ccu CLK_CPUX>;
32
30
clock-names = "cpu";
31
+
#cooling-cells = <2>;
33
32
};
34
33
};
35
34
···
58
55
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
59
56
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
60
57
interrupt-affinity = <&cpu0>, <&cpu1>;
58
+
};
59
+
60
+
thermal-zones {
61
+
cpu-thermal {
62
+
polling-delay-passive = <0>;
63
+
polling-delay = <0>;
64
+
thermal-sensors = <&ths>;
65
+
66
+
cooling-maps {
67
+
map0 {
68
+
trip = <&cpu_alert>;
69
+
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
70
+
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
71
+
};
72
+
};
73
+
74
+
trips {
75
+
cpu_alert: cpu-alert {
76
+
temperature = <85000>;
77
+
hysteresis = <2000>;
78
+
type = "passive";
79
+
};
80
+
81
+
cpu-crit {
82
+
temperature = <100000>;
83
+
hysteresis = <0>;
84
+
type = "critical";
85
+
};
86
+
};
87
+
};
61
88
};
62
89
};
+14
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+14
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
···
420
420
#size-cells = <0>;
421
421
};
422
422
423
+
ledc: led-controller@5018000 {
424
+
compatible = "allwinner,sun50i-a100-ledc";
425
+
reg = <0x5018000 0x400>;
426
+
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
427
+
clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
428
+
clock-names = "bus", "mod";
429
+
resets = <&ccu RST_BUS_LEDC>;
430
+
dmas = <&dma 42>;
431
+
dma-names = "tx";
432
+
#address-cells = <1>;
433
+
#size-cells = <0>;
434
+
status = "disabled";
435
+
};
436
+
423
437
emac0: ethernet@5020000 {
424
438
compatible = "allwinner,sun50i-a100-emac",
425
439
"allwinner,sun50i-a64-emac";
+94
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+94
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
···
214
214
allwinner,pinmux = <2>;
215
215
};
216
216
217
+
/omit-if-no-ref/
218
+
spi0_pc_pins: spi0-pc-pins {
219
+
pins = "PC2", "PC4", "PC12";
220
+
function = "spi0";
221
+
allwinner,pinmux = <4>;
222
+
};
223
+
224
+
/omit-if-no-ref/
225
+
spi0_cs0_pc_pin: spi0-cs0-pc-pin {
226
+
pins = "PC3";
227
+
function = "spi0";
228
+
allwinner,pinmux = <4>;
229
+
};
230
+
231
+
/omit-if-no-ref/
232
+
spi0_cs1_pc_pin: spi0-cs1-pc-pin {
233
+
pins = "PC7";
234
+
function = "spi0";
235
+
allwinner,pinmux = <4>;
236
+
};
237
+
238
+
/omit-if-no-ref/
239
+
spi0_hold_pc_pin: spi0-hold-pc-pin {
240
+
/* conflicts with eMMC D7 */
241
+
pins = "PC16";
242
+
function = "spi0";
243
+
allwinner,pinmux = <4>;
244
+
};
245
+
246
+
/omit-if-no-ref/
247
+
spi0_wp_pc_pin: spi0-wp-pc-pin {
248
+
/* conflicts with eMMC D2 */
249
+
pins = "PC15";
250
+
function = "spi0";
251
+
allwinner,pinmux = <4>;
252
+
};
253
+
217
254
uart0_pb_pins: uart0-pb-pins {
218
255
pins = "PB9", "PB10";
219
256
allwinner,pinmux = <2>;
···
600
563
#size-cells = <0>;
601
564
};
602
565
566
+
spi0: spi@4025000 {
567
+
compatible = "allwinner,sun55i-a523-spi";
568
+
reg = <0x04025000 0x1000>;
569
+
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
570
+
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
571
+
clock-names = "ahb", "mod";
572
+
dmas = <&dma 22>, <&dma 22>;
573
+
dma-names = "rx", "tx";
574
+
resets = <&ccu RST_BUS_SPI0>;
575
+
status = "disabled";
576
+
#address-cells = <1>;
577
+
#size-cells = <0>;
578
+
};
579
+
580
+
spi1: spi@4026000 {
581
+
compatible = "allwinner,sun55i-a523-spi-dbi",
582
+
"allwinner,sun55i-a523-spi";
583
+
reg = <0x04026000 0x1000>;
584
+
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
585
+
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
586
+
clock-names = "ahb", "mod";
587
+
dmas = <&dma 23>, <&dma 23>;
588
+
dma-names = "rx", "tx";
589
+
resets = <&ccu RST_BUS_SPI1>;
590
+
status = "disabled";
591
+
#address-cells = <1>;
592
+
#size-cells = <0>;
593
+
};
594
+
595
+
spi2: spi@4027000 {
596
+
compatible = "allwinner,sun55i-a523-spi";
597
+
reg = <0x04027000 0x1000>;
598
+
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
599
+
clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
600
+
clock-names = "ahb", "mod";
601
+
dmas = <&dma 24>, <&dma 24>;
602
+
dma-names = "rx", "tx";
603
+
resets = <&ccu RST_BUS_SPI2>;
604
+
status = "disabled";
605
+
#address-cells = <1>;
606
+
#size-cells = <0>;
607
+
};
608
+
603
609
usb_otg: usb@4100000 {
604
610
compatible = "allwinner,sun55i-a523-musb",
605
611
"allwinner,sun8i-a33-musb";
···
893
813
<&r_ccu CLK_R_AHB>;
894
814
clock-names = "bus", "hosc", "ahb";
895
815
#clock-cells = <1>;
816
+
};
817
+
818
+
r_spi0: spi@7092000 {
819
+
compatible = "allwinner,sun55i-a523-spi";
820
+
reg = <0x07092000 0x1000>;
821
+
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
822
+
clocks = <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>;
823
+
clock-names = "ahb", "mod";
824
+
dmas = <&dma 53>, <&dma 53>;
825
+
dma-names = "rx", "tx";
826
+
resets = <&r_ccu RST_BUS_R_SPI>;
827
+
status = "disabled";
828
+
#address-cells = <1>;
829
+
#size-cells = <0>;
896
830
};
897
831
898
832
mcu_ccu: clock-controller@7102000 {
+15
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
+15
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
···
400
400
assigned-clock-rates = <32768>;
401
401
};
402
402
403
+
&spi0 {
404
+
pinctrl-names = "default";
405
+
pinctrl-0 = <&spi0_pc_pins>, <&spi0_cs0_pc_pin>;
406
+
status = "okay";
407
+
408
+
flash@0 {
409
+
#address-cells = <1>;
410
+
#size-cells = <1>;
411
+
compatible = "jedec,spi-nor";
412
+
reg = <0>;
413
+
spi-max-frequency = <20000000>;
414
+
vcc-supply = <®_cldo1>;
415
+
};
416
+
};
417
+
403
418
&uart0 {
404
419
pinctrl-names = "default";
405
420
pinctrl-0 = <&uart0_pb_pins>;
+12
arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
+12
arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
···
59
59
status = "okay";
60
60
};
61
61
62
+
&ledc {
63
+
pinctrl-0 = <&ledc_pc0_pin>;
64
+
pinctrl-names = "default";
65
+
status = "okay";
66
+
67
+
multi-led@0 {
68
+
reg = <0x0>;
69
+
color = <LED_COLOR_ID_RGB>;
70
+
function = LED_FUNCTION_STATUS;
71
+
};
72
+
};
73
+
62
74
&mmc1 {
63
75
bus-width = <4>;
64
76
mmc-pwrseq = <&wifi_pwrseq>;
+13
arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
+13
arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
···
22
22
23
23
#include <dt-bindings/gpio/gpio.h>
24
24
#include <dt-bindings/input/input.h>
25
+
#include <dt-bindings/leds/common.h>
25
26
26
27
/dts-v1/;
27
28
···
119
118
"pin28 [gpio19]",
120
119
"pin37 [gpio23]",
121
120
"pin11 [gpio6]";
121
+
};
122
+
};
123
+
124
+
&ledc {
125
+
pinctrl-0 = <&ledc_pc0_pin>;
126
+
pinctrl-names = "default";
127
+
status = "okay";
128
+
129
+
multi-led@0 {
130
+
reg = <0x0>;
131
+
color = <LED_COLOR_ID_RGB>;
132
+
function = LED_FUNCTION_STATUS;
122
133
};
123
134
};
124
135
+6
arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+6
arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
+31
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+31
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
···
1
1
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
2
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
3
3
4
+
#include <dt-bindings/thermal/thermal.h>
5
+
4
6
#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
5
7
6
8
#include "sunxi-d1s-t113.dtsi"
···
116
114
<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
117
115
<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
118
116
<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
117
+
};
118
+
119
+
thermal-zones {
120
+
cpu-thermal {
121
+
polling-delay-passive = <0>;
122
+
polling-delay = <0>;
123
+
thermal-sensors = <&ths>;
124
+
125
+
cooling-maps {
126
+
map0 {
127
+
trip = <&cpu_alert>;
128
+
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
129
+
};
130
+
};
131
+
132
+
trips {
133
+
cpu_alert: cpu-alert {
134
+
temperature = <85000>;
135
+
hysteresis = <2000>;
136
+
type = "passive";
137
+
};
138
+
139
+
cpu-crit {
140
+
temperature = <100000>;
141
+
hysteresis = <0>;
142
+
type = "critical";
143
+
};
144
+
};
145
+
};
119
146
};
120
147
};
+31
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+31
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
···
204
204
#reset-cells = <1>;
205
205
};
206
206
207
+
ledc: led-controller@2008000 {
208
+
compatible = "allwinner,sun20i-d1-ledc",
209
+
"allwinner,sun50i-a100-ledc";
210
+
reg = <0x2008000 0x400>;
211
+
interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
212
+
clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
213
+
clock-names = "bus", "mod";
214
+
resets = <&ccu RST_BUS_LEDC>;
215
+
dmas = <&dma 42>;
216
+
dma-names = "tx";
217
+
#address-cells = <1>;
218
+
#size-cells = <0>;
219
+
status = "disabled";
220
+
};
221
+
207
222
gpadc: adc@2009000 {
208
223
compatible = "allwinner,sun20i-d1-gpadc";
209
224
reg = <0x2009000 0x400>;
···
227
212
interrupts = <SOC_PERIPHERAL_IRQ(57) IRQ_TYPE_LEVEL_HIGH>;
228
213
status = "disabled";
229
214
#io-channel-cells = <1>;
215
+
};
216
+
217
+
ths: thermal-sensor@2009400 {
218
+
compatible = "allwinner,sun20i-d1-ths";
219
+
reg = <0x2009400 0x400>;
220
+
interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>;
221
+
clocks = <&ccu CLK_BUS_THS>;
222
+
clock-names = "bus";
223
+
resets = <&ccu RST_BUS_THS>;
224
+
nvmem-cells = <&ths_calibration>;
225
+
nvmem-cell-names = "calibration";
226
+
#thermal-sensor-cells = <0>;
230
227
};
231
228
232
229
dmic: dmic@2031000 {
···
501
474
reg = <0x3006000 0x1000>;
502
475
#address-cells = <1>;
503
476
#size-cells = <1>;
477
+
478
+
ths_calibration: thermal-sensor-calibration@14 {
479
+
reg = <0x14 0x8>;
480
+
};
504
481
};
505
482
506
483
crypto: crypto@3040000 {