+1 -1

Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml

reviewed

··· 7 7 title: Qualcomm Display Clock & Reset Controller on SM6350 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@somainline.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm display clock control module provides the clocks, resets and power

+1 -1

Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml

reviewed

··· 7 7 title: Qualcomm Global Clock & Reset Controller on MSM8994 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@somainline.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm global clock control module provides the clocks, resets and power

+1 -1

Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml

reviewed

··· 7 7 title: Qualcomm Global Clock & Reset Controller on SM6125 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@somainline.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm global clock control module provides the clocks, resets and power

+1 -1

Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml

reviewed

··· 7 7 title: Qualcomm Global Clock & Reset Controller on SM6350 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@somainline.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm global clock control module provides the clocks, resets and power

+1 -1

Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml

reviewed

··· 7 7 title: Qualcomm Graphics Clock & Reset Controller on SM6115 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@linaro.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm graphics clock control module provides clocks, resets and power

+1 -1

Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml

reviewed

··· 7 7 title: Qualcomm Graphics Clock & Reset Controller on SM6125 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@linaro.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm graphics clock control module provides clocks and power domains on

+1 -1

Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml

reviewed

··· 7 7 title: Qualcomm Camera Clock & Reset Controller on SM6350 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@linaro.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm camera clock control module provides the clocks, resets and power

+1 -1

Documentation/devicetree/bindings/clock/qcom,sm6375-dispcc.yaml

reviewed

··· 7 7 title: Qualcomm Display Clock & Reset Controller on SM6375 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@linaro.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm display clock control module provides the clocks, resets and power

+1 -1

Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml

reviewed

··· 7 7 title: Qualcomm Global Clock & Reset Controller on SM6375 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@somainline.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm global clock control module provides the clocks, resets and power

+1 -1

Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml

reviewed

··· 7 7 title: Qualcomm Graphics Clock & Reset Controller on SM6375 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@linaro.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm graphics clock control module provides clocks, resets and power

+1 -1

Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml

reviewed

··· 7 7 title: Qualcomm SM8350 Video Clock & Reset Controller 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@linaro.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm video clock control module provides the clocks, resets and power

+1 -1

Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml

reviewed

··· 7 7 title: Qualcomm Graphics Clock & Reset Controller on SM8450 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@linaro.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm graphics clock control module provides the clocks, resets and power

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml

reviewed

··· 7 7 title: Qualcomm SM6375 Display MDSS 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@linaro.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: 13 13 SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks

+1 -1

Documentation/devicetree/bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml

reviewed

··· 7 7 title: ASUS Z00T TM5P5 NT35596 5.5" 1080×1920 LCD Panel 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konradybcio@gmail.com> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: |+ 13 13 This panel seems to only be found in the Asus Z00T

+1 -1

Documentation/devicetree/bindings/display/panel/sony,td4353-jdi.yaml

reviewed

··· 7 7 title: Sony TD4353 JDI 5 / 5.7" 2160x1080 MIPI-DSI Panel 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@somainline.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 The Sony TD4353 JDI is a 5 (XZ2c) / 5.7 (XZ2) inch 2160x1080

+1

Documentation/devicetree/bindings/eeprom/at25.yaml

reviewed

··· 28 28 - anvo,anv32e61w 29 29 - atmel,at25256B 30 30 - fujitsu,mb85rs1mt 31 31 + - fujitsu,mb85rs256 31 32 - fujitsu,mb85rs64 32 33 - microchip,at25160bn 33 34 - microchip,25lc040

+1 -1

Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml

reviewed

··· 8 8 9 9 maintainers: 10 10 - Bjorn Andersson <andersson@kernel.org> 11 11 - - Konrad Dybcio <konrad.dybcio@linaro.org> 11 11 + - Konrad Dybcio <konradybcio@kernel.org> 12 12 13 13 description: | 14 14 RPMh interconnect providers support system bandwidth requirements through

+1 -1

Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml

reviewed

··· 8 8 9 9 maintainers: 10 10 - Bjorn Andersson <andersson@kernel.org> 11 11 - - Konrad Dybcio <konrad.dybcio@linaro.org> 11 11 + - Konrad Dybcio <konradybcio@kernel.org> 12 12 13 13 description: | 14 14 RPMh interconnect providers support system bandwidth requirements through

+1 -1

Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml

reviewed

··· 8 8 9 9 maintainers: 10 10 - Bjorn Andersson <andersson@kernel.org> 11 11 - - Konrad Dybcio <konrad.dybcio@linaro.org> 11 11 + - Konrad Dybcio <konradybcio@kernel.org> 12 12 13 13 description: | 14 14 RPMh interconnect providers support system bandwidth requirements through

+1 -1

Documentation/devicetree/bindings/iommu/qcom,iommu.yaml

reviewed

··· 7 7 title: Qualcomm Technologies legacy IOMMU implementations 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@linaro.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 Qualcomm "B" family devices which are not compatible with arm-smmu have

+1 -1

Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml

reviewed

··· 7 7 title: Qualcomm Technologies, Inc. MDM9607 TLMM block 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@somainline.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: 13 13 Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC.

+1 -1

Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml

reviewed

··· 7 7 title: Qualcomm Technologies, Inc. SM6350 TLMM block 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@somainline.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: 13 13 Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC.

+1 -1

Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml

reviewed

··· 7 7 title: Qualcomm Technologies, Inc. SM6375 TLMM block 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@somainline.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: 13 13 Top Level Mode Multiplexer pin controller in Qualcomm SM6375 SoC.

+1 -1

Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml

reviewed

··· 8 8 9 9 maintainers: 10 10 - Bjorn Andersson <andersson@kernel.org> 11 11 - - Konrad Dybcio <konrad.dybcio@linaro.org> 11 11 + - Konrad Dybcio <konradybcio@kernel.org> 12 12 - Stephan Gerhold <stephan@gerhold.net> 13 13 14 14 description: |

+1 -1

Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml

reviewed

··· 7 7 title: Qualcomm Technologies, Inc. (QTI) RPM Master Stats 8 8 9 9 maintainers: 10 10 - - Konrad Dybcio <konrad.dybcio@linaro.org> 10 10 + - Konrad Dybcio <konradybcio@kernel.org> 11 11 12 12 description: | 13 13 The Qualcomm RPM (Resource Power Manager) architecture includes a concept

+11 -4

drivers/of/irq.c

reviewed

··· 344 344 struct device_node *p; 345 345 const __be32 *addr; 346 346 u32 intsize; 347 347 - int i, res; 347 347 + int i, res, addr_len; 348 348 + __be32 addr_buf[3] = { 0 }; 348 349 349 350 pr_debug("of_irq_parse_one: dev=%pOF, index=%d\n", device, index); 350 351 ··· 354 353 return of_irq_parse_oldworld(device, index, out_irq); 355 354 356 355 /* Get the reg property (if any) */ 357 357 - addr = of_get_property(device, "reg", NULL); 356 356 + addr = of_get_property(device, "reg", &addr_len); 357 357 + 358 358 + /* Prevent out-of-bounds read in case of longer interrupt parent address size */ 359 359 + if (addr_len > (3 * sizeof(__be32))) 360 360 + addr_len = 3 * sizeof(__be32); 361 361 + if (addr) 362 362 + memcpy(addr_buf, addr, addr_len); 358 363 359 364 /* Try the new-style interrupts-extended first */ 360 365 res = of_parse_phandle_with_args(device, "interrupts-extended", 361 366 "#interrupt-cells", index, out_irq); 362 367 if (!res) 363 363 - return of_irq_parse_raw(addr, out_irq); 368 368 + return of_irq_parse_raw(addr_buf, out_irq); 364 369 365 370 /* Look for the interrupt parent. */ 366 371 p = of_irq_find_parent(device); ··· 396 389 397 390 398 391 /* Check if there are any interrupt-map translations to process */ 399 399 - res = of_irq_parse_raw(addr, out_irq); 392 392 + res = of_irq_parse_raw(addr_buf, out_irq); 400 393 out: 401 394 of_node_put(p); 402 395 return res;