tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

iio: adc: mt6359: Add support for MediaTek MT6363 PMIC AUXADC

MediaTek MT6363 is a PMIC found on MT8196/MT6991 board designs
and communicates with the SoC over SPMI.

This PMIC integrates an Auxiliary ADC (AUXADC) which has a grand
total of 54 ADC channels: 49 PMIC-internal channels, 2 external
NTC thermistor channels and 2 generic ADC channels (mapped to 7
PMIC ADC external inputs).

To use a generic ADC channel it is necessary to enable one of
the PMIC ADC inputs at a time and only then start the reading,
so in this case it is possible to read only one external input
for each generic ADC channel.

Due to the lack of documentation, this implementation supports
using only one generic ADC channel, hence supports reading only
one external input at a time.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Link: https://patch.msgid.link/20250703141146.171431-6-angelogioacchino.delregno@collabora.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

AngeloGioacchino Del Regno and committed by
Jonathan Cameron d6f49313 dbcbed76

+252 -16
+252 -16
drivers/iio/adc/mt6359-auxadc.c
··· 7 7 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 8 8 */ 9 9 10 + #include <linux/bitfield.h> 10 11 #include <linux/bits.h> 11 12 #include <linux/cleanup.h> 12 13 #include <linux/delay.h> ··· 25 24 #include <dt-bindings/iio/adc/mediatek,mt6357-auxadc.h> 26 25 #include <dt-bindings/iio/adc/mediatek,mt6358-auxadc.h> 27 26 #include <dt-bindings/iio/adc/mediatek,mt6359-auxadc.h> 27 + #include <dt-bindings/iio/adc/mediatek,mt6363-auxadc.h> 28 28 29 29 #define AUXADC_AVG_TIME_US 10 30 30 #define AUXADC_POLL_DELAY_US 100 ··· 47 45 #define MT6359_IMP0_CONV_EN BIT(0) 48 46 #define MT6359_IMP1_IRQ_RDY BIT(15) 49 47 48 + #define MT6363_EXT_CHAN_MASK GENMASK(2, 0) 49 + #define MT6363_EXT_PURES_MASK GENMASK(4, 3) 50 + #define MT6363_PULLUP_RES_100K 0 51 + #define MT6363_PULLUP_RES_OPEN 3 52 + 50 53 enum mtk_pmic_auxadc_regs { 51 54 PMIC_AUXADC_ADC0, 52 55 PMIC_AUXADC_DCM_CON, ··· 60 53 PMIC_AUXADC_IMP3, 61 54 PMIC_AUXADC_RQST0, 62 55 PMIC_AUXADC_RQST1, 56 + PMIC_AUXADC_RQST3, 57 + PMIC_AUXADC_SDMADC_CON0, 63 58 PMIC_HK_TOP_WKEY, 64 59 PMIC_HK_TOP_RST_CON0, 65 60 PMIC_FGADC_R_CON0, ··· 83 74 PMIC_AUXADC_CHAN_TSX_TEMP, 84 75 PMIC_AUXADC_CHAN_HPOFS_CAL, 85 76 PMIC_AUXADC_CHAN_DCXO_TEMP, 77 + PMIC_AUXADC_CHAN_VTREF, 86 78 PMIC_AUXADC_CHAN_VBIF, 79 + PMIC_AUXADC_CHAN_VSYSSNS, 80 + PMIC_AUXADC_CHAN_VIN1, 81 + PMIC_AUXADC_CHAN_VIN2, 82 + PMIC_AUXADC_CHAN_VIN3, 83 + PMIC_AUXADC_CHAN_VIN4, 84 + PMIC_AUXADC_CHAN_VIN5, 85 + PMIC_AUXADC_CHAN_VIN6, 86 + PMIC_AUXADC_CHAN_VIN7, 87 87 PMIC_AUXADC_CHAN_IBAT, 88 88 PMIC_AUXADC_CHAN_VBAT, 89 89 PMIC_AUXADC_CHAN_MAX ··· 120 102 * @req_mask: Bitmask to activate a channel 121 103 * @rdy_idx: Readiness register number 122 104 * @rdy_mask: Bitmask to determine channel readiness 105 + * @ext_sel_idx: PMIC GPIO channel register number 106 + * @ext_sel_ch: PMIC GPIO number 107 + * @ext_sel_pu: PMIC GPIO channel pullup resistor selector 123 108 * @num_samples: Number of AUXADC samples for averaging 124 109 * @r_ratio: Resistance ratio fractional 125 110 */ ··· 131 110 u16 req_mask; 132 111 u8 rdy_idx; 133 112 u16 rdy_mask; 113 + s8 ext_sel_idx; 114 + u8 ext_sel_ch; 115 + u8 ext_sel_pu; 134 116 u16 num_samples; 135 117 struct u8_fract r_ratio; 136 118 }; ··· 148 124 * @sec_unlock_key: Security unlock key for HK_TOP writes 149 125 * @vref_mV: AUXADC Reference Voltage (VREF) in millivolts 150 126 * @imp_adc_num: ADC channel for battery impedance readings 127 + * @is_spmi: Defines whether this PMIC communicates over SPMI 128 + * @no_reset: If true, this PMIC does not support ADC reset 151 129 * @read_imp: Callback to read impedance channels 152 130 */ 153 131 struct mtk_pmic_auxadc_info { ··· 161 135 u16 sec_unlock_key; 162 136 u32 vref_mV; 163 137 u8 imp_adc_num; 138 + bool is_spmi; 139 + bool no_reset; 164 140 int (*read_imp)(struct mt6359_auxadc *adc_dev, 165 141 const struct iio_chan_spec *chan, int *vbat, int *ibat); 166 142 }; 167 143 168 - #define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \ 169 - _samples, _rnum, _rdiv) \ 144 + #define MTK_PMIC_ADC_EXT_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \ 145 + _ext_sel_idx, _ext_sel_ch, _ext_sel_pu, \ 146 + _samples, _rnum, _rdiv) \ 170 147 [PMIC_AUXADC_CHAN_##_ch_idx] = { \ 171 148 .req_idx = _req_idx, \ 172 149 .req_mask = BIT(_req_bit), \ 173 150 .rdy_idx = _rdy_idx, \ 174 151 .rdy_mask = BIT(_rdy_bit), \ 152 + .ext_sel_idx = _ext_sel_idx, \ 153 + .ext_sel_ch = _ext_sel_ch, \ 154 + .ext_sel_pu = _ext_sel_pu, \ 175 155 .num_samples = _samples, \ 176 156 .r_ratio = { _rnum, _rdiv } \ 177 157 } 158 + 159 + #define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \ 160 + _samples, _rnum, _rdiv) \ 161 + MTK_PMIC_ADC_EXT_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \ 162 + -1, 0, 0, _samples, _rnum, _rdiv) 178 163 179 164 #define MTK_PMIC_IIO_CHAN(_model, _name, _ch_idx, _adc_idx, _nbits, _ch_type) \ 180 165 { \ ··· 348 311 [PMIC_AUXADC_IMP3] = 0x120e, 349 312 }; 350 313 314 + static const struct iio_chan_spec mt6363_auxadc_channels[] = { 315 + MTK_PMIC_IIO_CHAN(MT6363, bat_adc, BATADC, 0, 15, IIO_RESISTANCE), 316 + MTK_PMIC_IIO_CHAN(MT6363, cdt_v, VCDT, 2, 12, IIO_TEMP), 317 + MTK_PMIC_IIO_CHAN(MT6363, batt_temp, BAT_TEMP, 3, 12, IIO_TEMP), 318 + MTK_PMIC_IIO_CHAN(MT6363, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP), 319 + MTK_PMIC_IIO_CHAN(MT6363, sys_sns_v, VSYSSNS, 6, 15, IIO_VOLTAGE), 320 + MTK_PMIC_IIO_CHAN(MT6363, tref_v, VTREF, 11, 12, IIO_VOLTAGE), 321 + MTK_PMIC_IIO_CHAN(MT6363, vcore_temp, VCORE_TEMP, 38, 12, IIO_TEMP), 322 + MTK_PMIC_IIO_CHAN(MT6363, vproc_temp, VPROC_TEMP, 39, 12, IIO_TEMP), 323 + MTK_PMIC_IIO_CHAN(MT6363, vgpu_temp, VGPU_TEMP, 40, 12, IIO_TEMP), 324 + 325 + /* For VIN, ADC12 holds the result depending on which GPIO was activated */ 326 + MTK_PMIC_IIO_CHAN(MT6363, in1_v, VIN1, 45, 15, IIO_VOLTAGE), 327 + MTK_PMIC_IIO_CHAN(MT6363, in2_v, VIN2, 45, 15, IIO_VOLTAGE), 328 + MTK_PMIC_IIO_CHAN(MT6363, in3_v, VIN3, 45, 15, IIO_VOLTAGE), 329 + MTK_PMIC_IIO_CHAN(MT6363, in4_v, VIN4, 45, 15, IIO_VOLTAGE), 330 + MTK_PMIC_IIO_CHAN(MT6363, in5_v, VIN5, 45, 15, IIO_VOLTAGE), 331 + MTK_PMIC_IIO_CHAN(MT6363, in6_v, VIN6, 45, 15, IIO_VOLTAGE), 332 + MTK_PMIC_IIO_CHAN(MT6363, in7_v, VIN7, 45, 15, IIO_VOLTAGE), 333 + }; 334 + 335 + static const struct mtk_pmic_auxadc_chan mt6363_auxadc_ch_desc[] = { 336 + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_ADC0, 15, 64, 4, 1), 337 + MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 338 + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_ADC0, 15, 32, 3, 2), 339 + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 340 + MTK_PMIC_ADC_CHAN(VSYSSNS, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_ADC0, 15, 64, 3, 1), 341 + MTK_PMIC_ADC_CHAN(VTREF, PMIC_AUXADC_RQST1, 3, PMIC_AUXADC_ADC0, 15, 32, 3, 2), 342 + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST3, 0, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 343 + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST3, 1, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 344 + MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST3, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1), 345 + 346 + MTK_PMIC_ADC_EXT_CHAN(VIN1, 347 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 348 + PMIC_AUXADC_SDMADC_CON0, 1, MT6363_PULLUP_RES_100K, 32, 1, 1), 349 + MTK_PMIC_ADC_EXT_CHAN(VIN2, 350 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 351 + PMIC_AUXADC_SDMADC_CON0, 2, MT6363_PULLUP_RES_100K, 32, 1, 1), 352 + MTK_PMIC_ADC_EXT_CHAN(VIN3, 353 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 354 + PMIC_AUXADC_SDMADC_CON0, 3, MT6363_PULLUP_RES_100K, 32, 1, 1), 355 + MTK_PMIC_ADC_EXT_CHAN(VIN4, 356 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 357 + PMIC_AUXADC_SDMADC_CON0, 4, MT6363_PULLUP_RES_100K, 32, 1, 1), 358 + MTK_PMIC_ADC_EXT_CHAN(VIN5, 359 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 360 + PMIC_AUXADC_SDMADC_CON0, 5, MT6363_PULLUP_RES_100K, 32, 1, 1), 361 + MTK_PMIC_ADC_EXT_CHAN(VIN6, 362 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 363 + PMIC_AUXADC_SDMADC_CON0, 6, MT6363_PULLUP_RES_100K, 32, 1, 1), 364 + MTK_PMIC_ADC_EXT_CHAN(VIN7, 365 + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, 366 + PMIC_AUXADC_SDMADC_CON0, 7, MT6363_PULLUP_RES_100K, 32, 1, 1), 367 + }; 368 + 369 + static const u16 mt6363_auxadc_regs[] = { 370 + [PMIC_AUXADC_RQST0] = 0x1108, 371 + [PMIC_AUXADC_RQST1] = 0x1109, 372 + [PMIC_AUXADC_RQST3] = 0x110c, 373 + [PMIC_AUXADC_ADC0] = 0x1088, 374 + [PMIC_AUXADC_IMP0] = 0x1208, 375 + [PMIC_AUXADC_IMP1] = 0x1209, 376 + }; 377 + 351 378 static void mt6358_stop_imp_conv(struct mt6359_auxadc *adc_dev) 352 379 { 353 380 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; ··· 543 442 .vref_mV = 1800, 544 443 }; 545 444 445 + static const struct mtk_pmic_auxadc_info mt6363_chip_info = { 446 + .model_name = "MT6363", 447 + .channels = mt6363_auxadc_channels, 448 + .num_channels = ARRAY_SIZE(mt6363_auxadc_channels), 449 + .desc = mt6363_auxadc_ch_desc, 450 + .regs = mt6363_auxadc_regs, 451 + .is_spmi = true, 452 + .no_reset = true, 453 + .vref_mV = 1840, 454 + }; 455 + 546 456 static void mt6359_auxadc_reset(struct mt6359_auxadc *adc_dev) 547 457 { 548 458 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 549 459 struct regmap *regmap = adc_dev->regmap; 460 + 461 + /* Some PMICs do not support reset */ 462 + if (cinfo->no_reset) 463 + return; 550 464 551 465 /* Unlock HK_TOP writes */ 552 466 if (cinfo->sec_unlock_key) ··· 578 462 regmap_write(regmap, cinfo->regs[PMIC_HK_TOP_WKEY], 0); 579 463 } 580 464 581 - static int mt6359_auxadc_read_adc(struct mt6359_auxadc *adc_dev, 582 - const struct iio_chan_spec *chan, int *out) 465 + /** 466 + * mt6359_auxadc_sample_adc_val() - Start ADC channel sampling and read value 467 + * @adc_dev: Main driver structure 468 + * @chan: IIO Channel spec for requested ADC 469 + * @out: Preallocated variable to store the value read from HW 470 + * 471 + * This function starts the sampling for an ADC channel, waits until all 472 + * of the samples are averaged and then reads the value from the HW. 473 + * 474 + * Note that the caller must stop the ADC sampling on its own, as this 475 + * function *never* stops it. 476 + * 477 + * Return: 478 + * Negative number for error; 479 + * Upon success returns zero and writes the read value to *out. 480 + */ 481 + static int mt6359_auxadc_sample_adc_val(struct mt6359_auxadc *adc_dev, 482 + const struct iio_chan_spec *chan, u32 *out) 583 483 { 584 484 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 585 485 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; 586 486 struct regmap *regmap = adc_dev->regmap; 587 - u32 val; 487 + u32 reg, rdy_mask, val, lval; 588 488 int ret; 589 489 590 490 /* Request to start sampling for ADC channel */ ··· 611 479 /* Wait until all samples are averaged */ 612 480 fsleep(desc->num_samples * AUXADC_AVG_TIME_US); 613 481 614 - ret = regmap_read_poll_timeout(regmap, 615 - cinfo->regs[PMIC_AUXADC_ADC0] + (chan->address << 1), 616 - val, val & PMIC_AUXADC_RDY_BIT, 482 + reg = cinfo->regs[PMIC_AUXADC_ADC0] + (chan->address << 1); 483 + rdy_mask = PMIC_AUXADC_RDY_BIT; 484 + 485 + /* 486 + * Even though for both PWRAP and SPMI cases the ADC HW signals that 487 + * the data is ready by setting AUXADC_RDY_BIT, for SPMI the register 488 + * read is only 8 bits long: for this case, the check has to be done 489 + * on the ADC(x)_H register (high bits) and the rdy_mask needs to be 490 + * shifted to the right by the same 8 bits. 491 + */ 492 + if (cinfo->is_spmi) { 493 + rdy_mask >>= 8; 494 + reg += 1; 495 + } 496 + 497 + ret = regmap_read_poll_timeout(regmap, reg, val, val & rdy_mask, 617 498 AUXADC_POLL_DELAY_US, AUXADC_TIMEOUT_US); 499 + if (ret) { 500 + dev_dbg(adc_dev->dev, "ADC read timeout for chan %lu\n", chan->address); 501 + return ret; 502 + } 503 + 504 + if (cinfo->is_spmi) { 505 + ret = regmap_read(regmap, reg - 1, &lval); 506 + if (ret) 507 + return ret; 508 + 509 + val = (val << 8) | lval; 510 + } 511 + 512 + *out = val; 513 + return 0; 514 + } 515 + 516 + static int mt6359_auxadc_read_adc(struct mt6359_auxadc *adc_dev, 517 + const struct iio_chan_spec *chan, int *out) 518 + { 519 + const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; 520 + const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; 521 + struct regmap *regmap = adc_dev->regmap; 522 + int ret, adc_stop_err; 523 + u8 ext_sel; 524 + u32 val; 525 + 526 + if (desc->ext_sel_idx >= 0) { 527 + ext_sel = FIELD_PREP(MT6363_EXT_PURES_MASK, desc->ext_sel_pu); 528 + ext_sel |= FIELD_PREP(MT6363_EXT_CHAN_MASK, desc->ext_sel_ch); 529 + 530 + ret = regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx], 531 + MT6363_EXT_PURES_MASK | MT6363_EXT_CHAN_MASK, 532 + ext_sel); 533 + if (ret) 534 + return ret; 535 + } 536 + 537 + /* 538 + * Get sampled value, then stop sampling unconditionally; the gathered 539 + * value is good regardless of if the ADC could be stopped. 540 + * 541 + * Note that if the ADC cannot be stopped but sampling was ok, this 542 + * function will not return any error, but will set the timed_out 543 + * status: this is not critical, as the ADC may auto recover and auto 544 + * stop after some time (depending on the PMIC model); if not, the next 545 + * read attempt will return -ETIMEDOUT and, for models that support it, 546 + * reset will be triggered. 547 + */ 548 + ret = mt6359_auxadc_sample_adc_val(adc_dev, chan, &val); 549 + 550 + adc_stop_err = regmap_write(regmap, cinfo->regs[desc->req_idx], 0); 551 + if (adc_stop_err) { 552 + dev_warn(adc_dev->dev, "Could not stop the ADC: %d\n,", adc_stop_err); 553 + adc_dev->timed_out = true; 554 + } 555 + 556 + /* If any sampling error occurred, the retrieved value is invalid */ 618 557 if (ret) 619 558 return ret; 620 559 621 - /* Stop sampling */ 622 - regmap_write(regmap, cinfo->regs[desc->req_idx], 0); 560 + /* ...and deactivate the ADC GPIO if previously done */ 561 + if (desc->ext_sel_idx >= 0) { 562 + ext_sel = FIELD_PREP(MT6363_EXT_PURES_MASK, MT6363_PULLUP_RES_OPEN); 623 563 564 + ret = regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx], 565 + MT6363_EXT_PURES_MASK, ext_sel); 566 + if (ret) 567 + return ret; 568 + } 569 + 570 + /* Everything went fine, give back the ADC reading */ 624 571 *out = val & GENMASK(chan->scan_type.realbits - 1, 0); 625 572 return 0; 626 573 } ··· 733 522 scoped_guard(mutex, &adc_dev->lock) { 734 523 switch (chan->scan_index) { 735 524 case PMIC_AUXADC_CHAN_IBAT: 525 + if (!adc_dev->chip_info->read_imp) 526 + return -EOPNOTSUPP; 527 + 736 528 ret = adc_dev->chip_info->read_imp(adc_dev, chan, NULL, val); 737 529 break; 738 530 case PMIC_AUXADC_CHAN_VBAT: 531 + if (!adc_dev->chip_info->read_imp) 532 + return -EOPNOTSUPP; 533 + 739 534 ret = adc_dev->chip_info->read_imp(adc_dev, chan, val, NULL); 740 535 break; 741 536 default: ··· 776 559 777 560 static int mt6359_auxadc_probe(struct platform_device *pdev) 778 561 { 562 + const struct mtk_pmic_auxadc_info *chip_info; 779 563 struct device *dev = &pdev->dev; 780 - struct device *mt6397_mfd_dev = dev->parent; 564 + struct device *mfd_dev = dev->parent; 781 565 struct mt6359_auxadc *adc_dev; 782 566 struct iio_dev *indio_dev; 567 + struct device *regmap_dev; 783 568 struct regmap *regmap; 784 569 int ret; 785 570 571 + chip_info = device_get_match_data(dev); 572 + if (!chip_info) 573 + return -EINVAL; 574 + /* 575 + * The regmap for this device has to be acquired differently for 576 + * SoC PMIC Wrapper and SPMI PMIC cases: 577 + * 578 + * If this is under SPMI, the regmap comes from the direct parent of 579 + * this driver: this_device->parent(mfd). 580 + * ... or ... 581 + * If this is under the SoC PMIC Wrapper, the regmap comes from the 582 + * parent of the MT6397 MFD: this_device->parent(mfd)->parent(pwrap) 583 + */ 584 + if (chip_info->is_spmi) 585 + regmap_dev = mfd_dev; 586 + else 587 + regmap_dev = mfd_dev->parent; 588 + 589 + 786 590 /* Regmap is from SoC PMIC Wrapper, parent of the mt6397 MFD */ 787 - regmap = dev_get_regmap(mt6397_mfd_dev->parent, NULL); 591 + regmap = dev_get_regmap(regmap_dev, NULL); 788 592 if (!regmap) 789 593 return dev_err_probe(dev, -ENODEV, "Failed to get regmap\n"); 790 594 ··· 816 578 adc_dev = iio_priv(indio_dev); 817 579 adc_dev->regmap = regmap; 818 580 adc_dev->dev = dev; 819 - 820 - adc_dev->chip_info = device_get_match_data(dev); 821 - if (!adc_dev->chip_info) 822 - return -EINVAL; 581 + adc_dev->chip_info = chip_info; 823 582 824 583 mutex_init(&adc_dev->lock); 825 584 ··· 839 604 { .compatible = "mediatek,mt6357-auxadc", .data = &mt6357_chip_info }, 840 605 { .compatible = "mediatek,mt6358-auxadc", .data = &mt6358_chip_info }, 841 606 { .compatible = "mediatek,mt6359-auxadc", .data = &mt6359_chip_info }, 607 + { .compatible = "mediatek,mt6363-auxadc", .data = &mt6363_chip_info }, 842 608 { } 843 609 }; 844 610 MODULE_DEVICE_TABLE(of, mt6359_auxadc_of_match);