+1 -1

Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml

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··· 140 140 the connection between the motherboard and any tiles. Sometimes the 141 141 compatible is placed directly under this node, sometimes it is placed 142 142 in a subnode named "motherboard-bus". Sometimes the compatible includes 143 143 - "arm,vexpress,v2?-p1" sometimes (on software models) is is just 143 143 + "arm,vexpress,v2?-p1" sometimes (on software models) it is just 144 144 "simple-bus". If the compatible is placed in the "motherboard-bus" node, 145 145 it is stricter and always has two compatibles. 146 146 type: object

+1 -1

Documentation/devicetree/bindings/example-schema.yaml

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··· 223 223 # 224 224 # For multiple 'if' schema, group them under an 'allOf'. 225 225 # 226 226 - # If the conditionals become too unweldy, then it may be better to just split 226 226 + # If the conditionals become too unwieldy, then it may be better to just split 227 227 # the binding into separate schema documents. 228 228 allOf: 229 229 - if:

+6 -6

Documentation/devicetree/bindings/gpio/gpio.txt

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··· 35 35 <&gpio1 15 0>; 36 36 37 37 In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is 38 38 - a local offset to the GPIO line and the second cell represent consumer flags, 39 39 - such as if the consumer desire the line to be active low (inverted) or open 38 38 + a local offset to the GPIO line and the second cell represents consumer flags, 39 39 + such as if the consumer desires the line to be active low (inverted) or open 40 40 drain. This is the recommended practice. 41 41 42 42 The exact meaning of each specifier cell is controller specific, and must be ··· 59 59 Optional standard bitfield specifiers for the last cell: 60 60 61 61 - Bit 0: 0 means active high, 1 means active low 62 62 - - Bit 1: 0 mean push-pull wiring, see: 62 62 + - Bit 1: 0 means push-pull wiring, see: 63 63 https://en.wikipedia.org/wiki/Push-pull_output 64 64 1 means single-ended wiring, see: 65 65 https://en.wikipedia.org/wiki/Single-ended_triode ··· 176 176 177 177 In either case placeholders are discouraged: rather use the "" (blank 178 178 string) if the use of the GPIO line is undefined in your design. Ideally, 179 179 - try to add comments to the dts file describing the naming the convention 179 179 + try to add comments to the dts file describing the naming convention 180 180 you have chosen, and specifying from where the names are derived. 181 181 182 182 The names are assigned starting from line offset 0, from left to right, ··· 304 304 It is also possible to use pin groups for gpio ranges when pin groups are the 305 305 easiest and most convenient mapping. 306 306 307 307 - Both both <pinctrl-base> and <count> must set to 0 when using named pin groups 307 307 + Both <pinctrl-base> and <count> must be set to 0 when using named pin groups 308 308 names. 309 309 310 310 The property gpio-ranges-group-names must contain exactly one string for each ··· 313 313 Elements of gpio-ranges-group-names must contain the name of a pin group 314 314 defined in the respective pin controller. The number of pins/GPIO lines in the 315 315 range is the number of pins in that pin group. The number of pins of that 316 316 - group is defined int the implementation and not in the device tree. 316 316 + group is defined in the implementation and not in the device tree. 317 317 318 318 If numerical and named pin groups are mixed, the string corresponding to a 319 319 numerical pin range in gpio-ranges-group-names must be empty.

+1 -1

Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml

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··· 52 52 As above, The Multimedia HW will go through SMI and M4U while it 53 53 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain 54 54 smi local arbiter and smi common. It will control whether the Multimedia 55 55 - HW should go though the m4u for translation or bypass it and talk 55 55 + HW should go through the m4u for translation or bypass it and talk 56 56 directly with EMI. And also SMI help control the power domain and clocks for 57 57 each local arbiter. 58 58

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Documentation/devicetree/bindings/leds/common.yaml

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··· 62 62 default-state: 63 63 description: 64 64 The initial state of the LED. If the LED is already on or off and the 65 65 - default-state property is set the to same value, then no glitch should be 65 65 + default-state property is set to the same value, then no glitch should be 66 66 produced where the LED momentarily turns off (or on). The "keep" setting 67 67 will keep the LED at whatever its current state is, without producing a 68 68 glitch.

+1 -1

Documentation/devicetree/bindings/mfd/ti,lp87524-q1.yaml

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··· 26 26 '#gpio-cells': 27 27 description: 28 28 The first cell is the pin number. 29 29 - The second cell is is used to specify flags. 29 29 + The second cell is used to specify flags. 30 30 See ../gpio/gpio.txt for more information. 31 31 const: 2 32 32

+1 -1

Documentation/devicetree/bindings/mfd/ti,lp87561-q1.yaml

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··· 26 26 '#gpio-cells': 27 27 description: 28 28 The first cell is the pin number. 29 29 - The second cell is is used to specify flags. 29 29 + The second cell is used to specify flags. 30 30 See ../gpio/gpio.txt for more information. 31 31 const: 2 32 32

+1 -1

Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml

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··· 28 28 '#gpio-cells': 29 29 description: 30 30 The first cell is the pin number. 31 31 - The second cell is is used to specify flags. 31 31 + The second cell is used to specify flags. 32 32 See ../gpio/gpio.txt for more information. 33 33 const: 2 34 34

+2 -2

Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml

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··· 57 57 # latter case. We choose to use the XOR logic for GPIO CD and WP 58 58 # lines. This means, the two properties are "superimposed," for 59 59 # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the 60 60 - # respective *-inverted property property results in a 60 60 + # respective *-inverted property results in a 61 61 # double-inversion and actually means the "normal" line polarity is 62 62 # in effect. 63 63 wp-inverted: ··· 264 264 mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay 265 265 waiting for I/O signalling and card power supply to be stable, 266 266 regardless of whether pwrseq-simple is used. Default to 10ms if 267 267 - no available. 267 267 + not available. 268 268 default: 10 269 269 270 270 supports-cqe:

+1 -1

Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml

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··· 149 149 - description: 150 150 The first register range should be the one of the DWMAC controller 151 151 - description: 152 152 - The second range is is for the Amlogic specific configuration 152 152 + The second range is for the Amlogic specific configuration 153 153 (for example the PRG_ETHERNET register range on Meson8b and newer) 154 154 155 155 interrupts:

+1 -1

Documentation/devicetree/bindings/net/ethernet-controller.yaml

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··· 222 222 reg: 223 223 maxItems: 1 224 224 description: 225 225 - This define the LED index in the PHY or the MAC. It's really 225 225 + This defines the LED index in the PHY or the MAC. It's really 226 226 driver dependent and required for ports that define multiple 227 227 LED for the same port. 228 228

+1 -1

Documentation/devicetree/bindings/net/ethernet-phy.yaml

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··· 266 266 reg: 267 267 maxItems: 1 268 268 description: 269 269 - This define the LED index in the PHY or the MAC. It's really 269 269 + This defines the LED index in the PHY or the MAC. It's really 270 270 driver dependent and required for ports that define multiple 271 271 LED for the same port. 272 272

+2 -2

Documentation/devicetree/bindings/net/micrel-ksz90x1.txt

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··· 13 13 14 14 All skew control options are specified in picoseconds. The minimum 15 15 value is 0, the maximum value is 3000, and it can be specified in 200ps 16 16 - steps, *but* these values are in not fact what you get because this chip's 16 16 + steps, *but* these values are in no way what you get because this chip's 17 17 skew values actually increase in 120ps steps, starting from -840ps. The 18 18 incorrect values came from an error in the original KSZ9021 datasheet 19 19 before it was corrected in revision 1.2 (Feb 2014), but it is too late to ··· 153 153 - micrel,force-master: 154 154 Boolean, force phy to master mode. Only set this option if the phy 155 155 reference clock provided at CLK125_NDO pin is used as MAC reference 156 156 - clock because the clock jitter in slave mode is to high (errata#2). 156 156 + clock because the clock jitter in slave mode is too high (errata#2). 157 157 Attention: The link partner must be configurable as slave otherwise 158 158 no link will be established. 159 159

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Documentation/devicetree/bindings/net/micrel.txt

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··· 26 26 Setting the RMII Reference Clock Select bit enables 25 MHz rather 27 27 than 50 MHz clock mode. 28 28 29 29 - Note that this option in only needed for certain PHY revisions with a 29 29 + Note that this option is only needed for certain PHY revisions with a 30 30 non-standard, inverted function of this configuration bit. 31 31 Specifically, a clock reference ("rmii-ref" below) is always needed to 32 32 actually select a mode.

+1 -1

Documentation/devicetree/bindings/submitting-patches.rst

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··· 95 95 For subsystem bindings (anything affecting more than a single device), 96 96 getting a devicetree maintainer to review it is required. 97 97 98 98 - 3) For a series going though multiple trees, the binding patch should be 98 98 + 3) For a series going through multiple trees, the binding patch should be 99 99 kept with the driver using the binding. 100 100 101 101 4) The DTS files should however never be applied via driver subsystem tree,