+3 -1

Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml

reviewed

··· 10 10 - Andrew Jeffery <andrew@aj.id.au> 11 11 12 12 description: 13 13 - This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC, 13 13 + This SGPIO controller is for ASPEED AST2400, AST2500, AST2600 and AST2700 SoC, 14 14 + AST2700 have two sgpio master both with 256 pins, 14 15 AST2600 have two sgpio master one with 128 pins another one with 80 pins, 15 16 AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial 16 17 GPIO pins can be programmed to support the following options ··· 28 27 - aspeed,ast2400-sgpio 29 28 - aspeed,ast2500-sgpio 30 29 - aspeed,ast2600-sgpiom 30 30 + - aspeed,ast2700-sgpiom 31 31 32 32 reg: 33 33 maxItems: 1

+107

Documentation/devicetree/bindings/gpio/gpio-line-mux.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/gpio/gpio-line-mux.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: GPIO line mux 8 8 + 9 9 + maintainers: 10 10 + - Jonas Jelonek <jelonek.jonas@gmail.com> 11 11 + 12 12 + description: | 13 13 + A GPIO controller to provide virtual GPIOs for a 1-to-many input-only mapping 14 14 + backed by a single shared GPIO and a multiplexer. A simple illustrated 15 15 + example is: 16 16 + 17 17 + +----- A 18 18 + IN / 19 19 + <-----o------- B 20 20 + / |\ 21 21 + | | +----- C 22 22 + | | \ 23 23 + | | +--- D 24 24 + | | 25 25 + M1 M0 26 26 + 27 27 + MUX CONTROL 28 28 + 29 29 + M1 M0 IN 30 30 + 0 0 A 31 31 + 0 1 B 32 32 + 1 0 C 33 33 + 1 1 D 34 34 + 35 35 + This can be used in case a real GPIO is connected to multiple inputs and 36 36 + controlled by a multiplexer, and another subsystem/driver does not work 37 37 + directly with the multiplexer subsystem. 38 38 + 39 39 + properties: 40 40 + compatible: 41 41 + const: gpio-line-mux 42 42 + 43 43 + gpio-controller: true 44 44 + 45 45 + "#gpio-cells": 46 46 + const: 2 47 47 + 48 48 + gpio-line-mux-states: 49 49 + description: Mux states corresponding to the virtual GPIOs. 50 50 + $ref: /schemas/types.yaml#/definitions/uint32-array 51 51 + 52 52 + gpio-line-names: true 53 53 + 54 54 + mux-controls: 55 55 + maxItems: 1 56 56 + description: 57 57 + Phandle to the multiplexer to control access to the GPIOs. 58 58 + 59 59 + ngpios: false 60 60 + 61 61 + muxed-gpios: 62 62 + maxItems: 1 63 63 + description: 64 64 + GPIO which is the '1' in 1-to-many and is shared by the virtual GPIOs 65 65 + and controlled via the mux. 66 66 + 67 67 + required: 68 68 + - compatible 69 69 + - gpio-controller 70 70 + - gpio-line-mux-states 71 71 + - mux-controls 72 72 + - muxed-gpios 73 73 + 74 74 + additionalProperties: false 75 75 + 76 76 + examples: 77 77 + - | 78 78 + #include <dt-bindings/gpio/gpio.h> 79 79 + #include <dt-bindings/mux/mux.h> 80 80 + 81 81 + sfp_gpio_mux: mux-controller-1 { 82 82 + compatible = "gpio-mux"; 83 83 + mux-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, 84 84 + <&gpio0 1 GPIO_ACTIVE_HIGH>; 85 85 + #mux-control-cells = <0>; 86 86 + idle-state = <MUX_IDLE_AS_IS>; 87 87 + }; 88 88 + 89 89 + sfp1_gpio: sfp-gpio-1 { 90 90 + compatible = "gpio-line-mux"; 91 91 + gpio-controller; 92 92 + #gpio-cells = <2>; 93 93 + 94 94 + mux-controls = <&sfp_gpio_mux>; 95 95 + muxed-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; 96 96 + 97 97 + gpio-line-mux-states = <0>, <1>, <3>; 98 98 + }; 99 99 + 100 100 + sfp1: sfp-p1 { 101 101 + compatible = "sff,sfp"; 102 102 + 103 103 + i2c-bus = <&sfp1_i2c>; 104 104 + los-gpios = <&sfp1_gpio 0 GPIO_ACTIVE_HIGH>; 105 105 + mod-def0-gpios = <&sfp1_gpio 1 GPIO_ACTIVE_LOW>; 106 106 + tx-fault-gpios = <&sfp1_gpio 2 GPIO_ACTIVE_HIGH>; 107 107 + };

+3 -2

Documentation/devicetree/bindings/gpio/gpio-mmio.yaml

reviewed

··· 20 20 compatible: 21 21 enum: 22 22 - brcm,bcm6345-gpio 23 23 - - ni,169445-nand-gpio 24 24 - - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller 25 23 - intel,ixp4xx-expansion-bus-mmio-gpio 24 24 + - ni,169445-nand-gpio 25 25 + - opencores,gpio 26 26 + - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller 26 27 27 28 big-endian: true 28 29

+2

Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml

reviewed

··· 74 74 - ti,tca9538 75 75 - ti,tca9539 76 76 - ti,tca9554 77 77 + - ti,tcal6408 78 78 + - ti,tcal6416 77 79 78 80 reg: 79 81 maxItems: 1

+22

Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml

reviewed

··· 86 86 - nvidia,tegra234-gpio 87 87 - nvidia,tegra234-gpio-aon 88 88 - nvidia,tegra256-gpio 89 89 + - nvidia,tegra264-gpio 90 90 + - nvidia,tegra264-gpio-uphy 91 91 + - nvidia,tegra264-gpio-aon 89 92 90 93 reg-names: 91 94 items: ··· 112 109 description: The interrupt outputs from the HW block, one per set of 113 110 ports, in the order the HW manual describes them. The number of entries 114 111 required varies depending on compatible value. 112 112 + 113 113 + wakeup-parent: 114 114 + description: Phandle to the parent interrupt controller used for wake-up. On 115 115 + Tegra, this typically references the PMC interrupt controller. 115 116 116 117 gpio-controller: true 117 118 ··· 164 157 - nvidia,tegra194-gpio 165 158 - nvidia,tegra234-gpio 166 159 - nvidia,tegra256-gpio 160 160 + - nvidia,tegra264-gpio 161 161 + - nvidia,tegra264-gpio-uphy 167 162 then: 168 163 properties: 169 164 interrupts: ··· 180 171 - nvidia,tegra186-gpio-aon 181 172 - nvidia,tegra194-gpio-aon 182 173 - nvidia,tegra234-gpio-aon 174 174 + - nvidia,tegra264-gpio-aon 183 175 then: 184 176 properties: 185 177 interrupts: 186 178 minItems: 1 187 179 maxItems: 4 180 180 + 181 181 + - if: 182 182 + properties: 183 183 + compatible: 184 184 + contains: 185 185 + enum: 186 186 + - nvidia,tegra264-gpio 187 187 + - nvidia,tegra264-gpio-uphy 188 188 + - nvidia,tegra264-gpio-aon 189 189 + then: 190 190 + required: 191 191 + - wakeup-parent 188 192 189 193 required: 190 194 - compatible

+3 -1

Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml

reviewed

··· 19 19 pattern: "^gpio@[0-9a-f]+$" 20 20 21 21 compatible: 22 22 - const: spacemit,k1-gpio 22 22 + enum: 23 23 + - spacemit,k1-gpio 24 24 + - spacemit,k3-gpio 23 25 24 26 reg: 25 27 maxItems: 1

+4 -3

Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml

reviewed

··· 10 10 - Matti Vaittinen <mazziesaccount@gmail.com> 11 11 12 12 description: | 13 13 - This module is part of the ROHM BD71828 MFD device. For more details 14 14 - see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml. 13 13 + This module is part of the ROHM BD71828 and BD72720 MFD device. For more 14 14 + details see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml 15 15 + and Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml 15 16 16 17 The LED controller is represented as a sub-node of the PMIC node on the device 17 17 - tree. 18 18 + tree. This should be located under "leds" - node in PMIC node. 18 19 19 20 The device has two LED outputs referred as GRNLED and AMBLED in data-sheet. 20 21

+339

Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/mfd/rohm,bd72720-pmic.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: ROHM BD72720 Power Management Integrated Circuit 8 8 + 9 9 + maintainers: 10 10 + - Matti Vaittinen <mazziesaccount@gmail.com> 11 11 + 12 12 + description: 13 13 + BD72720 is a single-chip power management IC for battery-powered portable 14 14 + devices. The BD72720 integrates 10 bucks and 11 LDOs, and a 3000 mA 15 15 + switching charger. The IC also includes a Coulomb counter, a real-time 16 16 + clock (RTC), GPIOs and a 32.768 kHz clock gate. 17 17 + 18 18 + # In addition to the properties found from the charger node, the ROHM BD72720 19 19 + # uses properties from a static battery node. Please see the: 20 20 + # Documentation/devicetree/bindings/power/supply/battery.yaml 21 21 + # 22 22 + # Following properties are used 23 23 + # when present: 24 24 + # 25 25 + # charge-full-design-microamp-hours: Battry capacity in mAh 26 26 + # voltage-max-design-microvolt: Maximum voltage 27 27 + # voltage-min-design-microvolt: Minimum voltage system is still operating. 28 28 + # degrade-cycle-microamp-hours: Capacity lost due to aging at each full 29 29 + # charge cycle. 30 30 + # ocv-capacity-celsius: Array of OCV table temperatures. 1/table. 31 31 + # ocv-capacity-table-<N>: Table of OCV voltage/SOC pairs. Corresponds 32 32 + # N.th temperature in ocv-capacity-celsius 33 33 + # 34 34 + # volt-drop-thresh-microvolt: Threshold for starting the VDR correction 35 35 + # volt-drop-soc: Table of capacity values matching the 36 36 + # values in VDR tables. 37 37 + # 38 38 + # volt-drop-temperatures-millicelsius: Temperatures corresponding to the volage 39 39 + # drop values given in volt-drop-[0-9]-microvolt 40 40 + # 41 41 + # volt-drop-[0-9]-microvolt: VDR table for a temperature specified in 42 42 + # volt-drop-temperatures-millicelsius 43 43 + # 44 44 + # VDR tables are (usually) determined for a specific battery by ROHM. 45 45 + # The battery node would then be referred from the charger node: 46 46 + # 47 47 + # monitored-battery = <&battery>; 48 48 + 49 49 + properties: 50 50 + compatible: 51 51 + const: rohm,bd72720 52 52 + 53 53 + reg: 54 54 + description: 55 55 + I2C slave address. 56 56 + maxItems: 1 57 57 + 58 58 + interrupts: 59 59 + maxItems: 1 60 60 + 61 61 + gpio-controller: true 62 62 + 63 63 + "#gpio-cells": 64 64 + const: 2 65 65 + description: 66 66 + The first cell is the pin number and the second cell is used to specify 67 67 + flags. See the gpio binding document for more information. 68 68 + 69 69 + clocks: 70 70 + maxItems: 1 71 71 + 72 72 + "#clock-cells": 73 73 + const: 0 74 74 + 75 75 + clock-output-names: 76 76 + const: bd71828-32k-out 77 77 + 78 78 + rohm,clkout-open-drain: 79 79 + description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos". 80 80 + $ref: /schemas/types.yaml#/definitions/uint32 81 81 + maximum: 1 82 82 + 83 83 + rohm,charger-sense-resistor-micro-ohms: 84 84 + minimum: 10000 85 85 + maximum: 50000 86 86 + description: 87 87 + BD72720 has a SAR ADC for measuring charging currents. External sense 88 88 + resistor (RSENSE in data sheet) should be used. If some other but 89 89 + 30 mOhm resistor is used the resistance value should be given here in 90 90 + micro Ohms. 91 91 + 92 92 + regulators: 93 93 + $ref: /schemas/regulator/rohm,bd72720-regulator.yaml 94 94 + description: 95 95 + List of child nodes that specify the regulators. 96 96 + 97 97 + leds: 98 98 + $ref: /schemas/leds/rohm,bd71828-leds.yaml 99 99 + 100 100 + rohm,pin-fault_b: 101 101 + $ref: /schemas/types.yaml#/definitions/string 102 102 + description: 103 103 + BD72720 has an OTP option to use fault_b-pin for different 104 104 + purposes. Set this property accordingly. OTP options are 105 105 + OTP0 - bi-directional FAULT_B or READY indicator depending on a 106 106 + 'sub option' 107 107 + OTP1 - GPO 108 108 + OTP2 - Power sequencer output. 109 109 + enum: 110 110 + - faultb 111 111 + - readyind 112 112 + - gpo 113 113 + - pwrseq 114 114 + 115 115 + patternProperties: 116 116 + "^rohm,pin-dvs[0-1]$": 117 117 + $ref: /schemas/types.yaml#/definitions/string 118 118 + description: 119 119 + BD72720 has 4 different OTP options to determine the use of dvs<X>-pins. 120 120 + OTP0 - regulator RUN state control. 121 121 + OTP1 - GPI. 122 122 + OTP2 - GPO. 123 123 + OTP3 - Power sequencer output. 124 124 + This property specifies the use of the pin. 125 125 + enum: 126 126 + - dvs-input 127 127 + - gpi 128 128 + - gpo 129 129 + - pwrseq 130 130 + 131 131 + "^rohm,pin-exten[0-1]$": 132 132 + $ref: /schemas/types.yaml#/definitions/string 133 133 + description: BD72720 has an OTP option to use exten0-pin for different 134 134 + purposes. Set this property accordingly. 135 135 + OTP0 - GPO 136 136 + OTP1 - Power sequencer output. 137 137 + enum: 138 138 + - gpo 139 139 + - pwrseq 140 140 + 141 141 + required: 142 142 + - compatible 143 143 + - reg 144 144 + - interrupts 145 145 + - clocks 146 146 + - "#clock-cells" 147 147 + - regulators 148 148 + - gpio-controller 149 149 + - "#gpio-cells" 150 150 + 151 151 + additionalProperties: false 152 152 + 153 153 + examples: 154 154 + - | 155 155 + #include <dt-bindings/interrupt-controller/irq.h> 156 156 + #include <dt-bindings/leds/common.h> 157 157 + i2c { 158 158 + #address-cells = <1>; 159 159 + #size-cells = <0>; 160 160 + pmic: pmic@4b { 161 161 + compatible = "rohm,bd72720"; 162 162 + reg = <0x4b>; 163 163 + 164 164 + interrupt-parent = <&gpio1>; 165 165 + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 166 166 + 167 167 + clocks = <&osc 0>; 168 168 + #clock-cells = <0>; 169 169 + clock-output-names = "bd71828-32k-out"; 170 170 + 171 171 + gpio-controller; 172 172 + #gpio-cells = <2>; 173 173 + 174 174 + rohm,pin-dvs0 = "gpi"; 175 175 + rohm,pin-dvs1 = "gpi"; 176 176 + rohm,pin-exten0 = "gpo"; 177 177 + rohm,pin-exten1 = "gpo"; 178 178 + rohm,pin-fault_b = "faultb"; 179 179 + 180 180 + rohm,charger-sense-resistor-micro-ohms = <10000>; 181 181 + 182 182 + regulators { 183 183 + buck1 { 184 184 + regulator-name = "buck1"; 185 185 + regulator-min-microvolt = <500000>; 186 186 + regulator-max-microvolt = <2000000>; 187 187 + regulator-ramp-delay = <2500>; 188 188 + }; 189 189 + buck2 { 190 190 + regulator-name = "buck2"; 191 191 + regulator-min-microvolt = <500000>; 192 192 + regulator-max-microvolt = <2000000>; 193 193 + regulator-ramp-delay = <2500>; 194 194 + }; 195 195 + buck3 { 196 196 + regulator-name = "buck3"; 197 197 + regulator-min-microvolt = <1200000>; 198 198 + regulator-max-microvolt = <2000000>; 199 199 + }; 200 200 + buck4 { 201 201 + regulator-name = "buck4"; 202 202 + regulator-min-microvolt = <1000000>; 203 203 + regulator-max-microvolt = <1800000>; 204 204 + }; 205 205 + buck5 { 206 206 + regulator-name = "buck5"; 207 207 + regulator-min-microvolt = <2500000>; 208 208 + regulator-max-microvolt = <3300000>; 209 209 + }; 210 210 + buck6 { 211 211 + regulator-name = "buck6"; 212 212 + regulator-min-microvolt = <500000>; 213 213 + regulator-max-microvolt = <2000000>; 214 214 + regulator-ramp-delay = <2500>; 215 215 + }; 216 216 + buck7 { 217 217 + regulator-name = "buck7"; 218 218 + regulator-min-microvolt = <500000>; 219 219 + regulator-max-microvolt = <2000000>; 220 220 + regulator-ramp-delay = <2500>; 221 221 + }; 222 222 + buck8 { 223 223 + regulator-name = "buck8"; 224 224 + regulator-min-microvolt = <500000>; 225 225 + regulator-max-microvolt = <1700000>; 226 226 + regulator-ramp-delay = <2500>; 227 227 + rohm,dvs-run-voltage = <1700000>; 228 228 + rohm,dvs-idle-voltage = <1>; 229 229 + rohm,dvs-suspend-voltage = <1>; 230 230 + rohm,dvs-lpsr-voltage = <0>; 231 231 + regulator-boot-on; 232 232 + }; 233 233 + buck9 { 234 234 + regulator-name = "buck9"; 235 235 + regulator-min-microvolt = <500000>; 236 236 + regulator-max-microvolt = <1700000>; 237 237 + regulator-ramp-delay = <2500>; 238 238 + rohm,dvs-run-voltage = <1700000>; 239 239 + rohm,dvs-idle-voltage = <1>; 240 240 + rohm,dvs-suspend-voltage = <1>; 241 241 + rohm,dvs-lpsr-voltage = <0>; 242 242 + regulator-boot-on; 243 243 + }; 244 244 + buck10 { 245 245 + regulator-name = "buck10"; 246 246 + regulator-min-microvolt = <500000>; 247 247 + regulator-max-microvolt = <1700000>; 248 248 + regulator-ramp-delay = <2500>; 249 249 + rohm,dvs-run-voltage = <1700000>; 250 250 + rohm,dvs-idle-voltage = <1>; 251 251 + rohm,dvs-suspend-voltage = <1>; 252 252 + rohm,dvs-lpsr-voltage = <0>; 253 253 + regulator-boot-on; 254 254 + }; 255 255 + ldo1 { 256 256 + regulator-name = "ldo1"; 257 257 + regulator-min-microvolt = <800000>; 258 258 + regulator-max-microvolt = <3300000>; 259 259 + }; 260 260 + ldo2 { 261 261 + regulator-name = "ldo2"; 262 262 + regulator-min-microvolt = <800000>; 263 263 + regulator-max-microvolt = <3300000>; 264 264 + }; 265 265 + ldo3 { 266 266 + regulator-name = "ldo3"; 267 267 + regulator-min-microvolt = <800000>; 268 268 + regulator-max-microvolt = <3300000>; 269 269 + }; 270 270 + ldo4 { 271 271 + regulator-name = "ldo4"; 272 272 + regulator-min-microvolt = <800000>; 273 273 + regulator-max-microvolt = <3300000>; 274 274 + }; 275 275 + ldo5 { 276 276 + regulator-name = "ldo5"; 277 277 + regulator-min-microvolt = <800000>; 278 278 + regulator-max-microvolt = <3300000>; 279 279 + }; 280 280 + ldo6 { 281 281 + regulator-name = "ldo6"; 282 282 + regulator-min-microvolt = <1800000>; 283 283 + regulator-max-microvolt = <1800000>; 284 284 + }; 285 285 + ldo7 { 286 286 + regulator-name = "ldo7"; 287 287 + regulator-min-microvolt = <800000>; 288 288 + regulator-max-microvolt = <3300000>; 289 289 + }; 290 290 + ldo8 { 291 291 + regulator-name = "ldo8"; 292 292 + regulator-min-microvolt = <750000>; 293 293 + regulator-max-microvolt = <3300000>; 294 294 + rohm,dvs-suspend-voltage = <0>; 295 295 + rohm,dvs-lpsr-voltage = <1>; 296 296 + rohm,dvs-run-voltage = <750000>; 297 297 + }; 298 298 + ldo9 { 299 299 + regulator-name = "ldo9"; 300 300 + regulator-min-microvolt = <750000>; 301 301 + regulator-max-microvolt = <3300000>; 302 302 + rohm,dvs-suspend-voltage = <0>; 303 303 + rohm,dvs-lpsr-voltage = <1>; 304 304 + rohm,dvs-run-voltage = <750000>; 305 305 + }; 306 306 + ldo10 { 307 307 + regulator-name = "ldo10"; 308 308 + regulator-min-microvolt = <750000>; 309 309 + regulator-max-microvolt = <3300000>; 310 310 + rohm,dvs-suspend-voltage = <0>; 311 311 + rohm,dvs-lpsr-voltage = <1>; 312 312 + rohm,dvs-run-voltage = <750000>; 313 313 + }; 314 314 + ldo11 { 315 315 + regulator-name = "ldo11"; 316 316 + regulator-min-microvolt = <750000>; 317 317 + regulator-max-microvolt = <3300000>; 318 318 + rohm,dvs-suspend-voltage = <0>; 319 319 + rohm,dvs-lpsr-voltage = <1>; 320 320 + rohm,dvs-run-voltage = <750000>; 321 321 + }; 322 322 + }; 323 323 + 324 324 + leds { 325 325 + compatible = "rohm,bd71828-leds"; 326 326 + 327 327 + led-1 { 328 328 + rohm,led-compatible = "bd71828-grnled"; 329 329 + function = LED_FUNCTION_INDICATOR; 330 330 + color = <LED_COLOR_ID_GREEN>; 331 331 + }; 332 332 + led-2 { 333 333 + rohm,led-compatible = "bd71828-ambled"; 334 334 + function = LED_FUNCTION_CHARGING; 335 335 + color = <LED_COLOR_ID_AMBER>; 336 336 + }; 337 337 + }; 338 338 + }; 339 339 + };

+32 -1

Documentation/devicetree/bindings/power/supply/battery.yaml

reviewed

··· 64 64 description: battery design capacity 65 65 66 66 trickle-charge-current-microamp: 67 67 - description: current for trickle-charge phase 67 67 + description: current for trickle-charge phase. 68 68 + Please note that the trickle-charging here, refers "wake-up" or 69 69 + "pre-pre" -charging, for very empty batteries. Similar term is also 70 70 + used for "maintenance" or "top-off" -charging of batteries (like 71 71 + NiMh bq24400) - that is different and not controlled by this 72 72 + property. 73 73 + 74 74 + tricklecharge-upper-limit-microvolt: 75 75 + description: limit when to change to precharge from trickle charge 76 76 + Trickle-charging here refers "wake-up" or "pre-pre" -charging. 68 77 69 78 precharge-current-microamp: 70 79 description: current for pre-charge phase ··· 128 119 - description: alert when battery temperature is lower than this value 129 120 - description: alert when battery temperature is higher than this value 130 121 122 122 + # The volt-drop* -properties describe voltage-drop for a battery, described 123 123 + # as VDROP in: 124 124 + # https://patentimages.storage.googleapis.com/6c/f5/17/c1d901c220f6a9/US20150032394A1.pdf 125 125 + volt-drop-thresh-microvolt: 126 126 + description: Threshold for starting the VDR correction 127 127 + maximum: 48000000 128 128 + 129 129 + volt-drop-soc-bp: 130 130 + description: Table of capacity values matching the values in VDR tables. 131 131 + The value should be given as basis points, 1/100 of a percent. 132 132 + 133 133 + volt-drop-temperatures-millicelsius: 134 134 + description: An array containing the temperature in milli celsius, for each 135 135 + of the VDR lookup table. 136 136 + 131 137 required: 132 138 - compatible 133 139 ··· 160 136 - description: open circuit voltage (OCV) in microvolts 161 137 - description: battery capacity percent 162 138 maximum: 100 139 139 + 140 140 + '^volt-drop-[0-9]-microvolt': 141 141 + description: Table of the voltage drop rate (VDR) values. Each entry in the 142 142 + table should match a capacity value in the volt-drop-soc table. 143 143 + Furthermore, the values should be obtained for the temperature given in 144 144 + volt-drop-temperatures-millicelsius table at index matching the 145 145 + number in this table's name. 163 146 164 147 additionalProperties: false 165 148

+148

Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/regulator/rohm,bd72720-regulator.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: ROHM BD72720 Power Management Integrated Circuit regulators 8 8 + 9 9 + maintainers: 10 10 + - Matti Vaittinen <mazziesaccount@gmail.com> 11 11 + 12 12 + description: | 13 13 + This module is part of the ROHM BD72720 MFD device. For more details 14 14 + see Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml. 15 15 + 16 16 + The regulator controller is represented as a sub-node of the PMIC node 17 17 + on the device tree. 18 18 + 19 19 + Regulator nodes should be named to BUCK_<number> and LDO_<number>. 20 20 + The valid names for BD72720 regulator nodes are 21 21 + buck1, buck2, buck3, buck4, buck5, buck6, buck7, buck8, buck9, buck10 22 22 + ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldo8, ldo9, ldo10, ldo11 23 23 + 24 24 + patternProperties: 25 25 + "^ldo([1-9]|1[0-1])$": 26 26 + type: object 27 27 + description: 28 28 + Properties for single LDO regulator. 29 29 + $ref: regulator.yaml# 30 30 + 31 31 + properties: 32 32 + regulator-name: 33 33 + pattern: "^ldo([1-9]|1[0-1])$" 34 34 + 35 35 + rohm,dvs-run-voltage: 36 36 + description: 37 37 + PMIC default "RUN" state voltage in uV. See below table for 38 38 + LDOs which support this. 0 means disabled. 39 39 + $ref: /schemas/types.yaml#/definitions/uint32 40 40 + minimum: 0 41 41 + maximum: 3300000 42 42 + 43 43 + rohm,dvs-idle-voltage: 44 44 + description: 45 45 + PMIC default "IDLE" state voltage in uV. See below table for 46 46 + LDOs which support this. 0 means disabled. 47 47 + $ref: /schemas/types.yaml#/definitions/uint32 48 48 + minimum: 0 49 49 + maximum: 3300000 50 50 + 51 51 + rohm,dvs-suspend-voltage: 52 52 + description: 53 53 + PMIC default "SUSPEND" state voltage in uV. See below table for 54 54 + LDOs which support this. 0 means disabled. 55 55 + $ref: /schemas/types.yaml#/definitions/uint32 56 56 + minimum: 0 57 57 + maximum: 3300000 58 58 + 59 59 + rohm,dvs-lpsr-voltage: 60 60 + description: 61 61 + PMIC default "deep-idle" state voltage in uV. See below table for 62 62 + LDOs which support this. 0 means disabled. 63 63 + $ref: /schemas/types.yaml#/definitions/uint32 64 64 + minimum: 0 65 65 + maximum: 3300000 66 66 + 67 67 + # Supported default DVS states: 68 68 + # ldo | run | idle | suspend | lpsr 69 69 + # -------------------------------------------------------------- 70 70 + # 1, 2, 3, and 4 | supported | supported | supported | supported 71 71 + # -------------------------------------------------------------- 72 72 + # 5 - 11 | supported (*) 73 73 + # -------------------------------------------------------------- 74 74 + # 75 75 + # (*) All states use same voltage but have own enable / disable 76 76 + # settings. Voltage 0 can be specified for a state to make 77 77 + # regulator disabled on that state. 78 78 + 79 79 + unevaluatedProperties: false 80 80 + 81 81 + "^buck([1-9]|10)$": 82 82 + type: object 83 83 + description: 84 84 + Properties for single BUCK regulator. 85 85 + $ref: regulator.yaml# 86 86 + 87 87 + properties: 88 88 + regulator-name: 89 89 + pattern: "^buck([1-9]|10)$" 90 90 + 91 91 + rohm,ldon-head-microvolt: 92 92 + description: 93 93 + Set this on boards where BUCK10 is used to supply LDOs 1-4. The bucki 94 94 + voltage will be changed by the PMIC to follow the LDO output voltages 95 95 + with the offset voltage given here. This will improve the LDO efficiency. 96 96 + minimum: 50000 97 97 + maximum: 300000 98 98 + 99 99 + rohm,dvs-run-voltage: 100 100 + description: 101 101 + PMIC default "RUN" state voltage in uV. See below table for 102 102 + bucks which support this. 0 means disabled. 103 103 + $ref: /schemas/types.yaml#/definitions/uint32 104 104 + minimum: 0 105 105 + maximum: 3300000 106 106 + 107 107 + rohm,dvs-idle-voltage: 108 108 + description: 109 109 + PMIC default "IDLE" state voltage in uV. See below table for 110 110 + bucks which support this. 0 means disabled. 111 111 + $ref: /schemas/types.yaml#/definitions/uint32 112 112 + minimum: 0 113 113 + maximum: 3300000 114 114 + 115 115 + rohm,dvs-suspend-voltage: 116 116 + description: 117 117 + PMIC default "SUSPEND" state voltage in uV. See below table for 118 118 + bucks which support this. 0 means disabled. 119 119 + $ref: /schemas/types.yaml#/definitions/uint32 120 120 + minimum: 0 121 121 + maximum: 3300000 122 122 + 123 123 + rohm,dvs-lpsr-voltage: 124 124 + description: 125 125 + PMIC default "deep-idle" state voltage in uV. See below table for 126 126 + bucks which support this. 0 means disabled. 127 127 + $ref: /schemas/types.yaml#/definitions/uint32 128 128 + minimum: 0 129 129 + maximum: 3300000 130 130 + 131 131 + # Supported default DVS states: 132 132 + # buck | run | idle | suspend | lpsr 133 133 + # -------------------------------------------------------------- 134 134 + # 1, 2, 3, and 4 | supported | supported | supported | supported 135 135 + # -------------------------------------------------------------- 136 136 + # 5 - 10 | supported (*) 137 137 + # -------------------------------------------------------------- 138 138 + # 139 139 + # (*) All states use same voltage but have own enable / disable 140 140 + # settings. Voltage 0 can be specified for a state to make 141 141 + # regulator disabled on that state. 142 142 + 143 143 + required: 144 144 + - regulator-name 145 145 + 146 146 + unevaluatedProperties: false 147 147 + 148 148 + additionalProperties: false

+87

Documentation/driver-api/gpio/pca953x.rst

reviewed

··· 178 178 pcal6416 16 yes 00 02 04 06 179 179 pcal9535 16 yes 00 02 04 06 180 180 pcal9555a 16 yes 00 02 04 06 181 181 + tcal6408 8 yes 00 01 02 03 182 182 + tcal6416 16 yes 00 02 04 06 181 183 ========== ===== ========= ===== ====== ====== ========= 182 184 183 185 These chips have several additional features: ··· 198 196 pcal6416 40 44 46 48 4A 4C 4F 199 197 pcal9535 40 44 46 48 4A 4C 4F 200 198 pcal9555a 40 44 46 48 4A 4C 4F 199 199 + tcal6408 40 42 43 44 45 46 4F 200 200 + tcal6416 40 44 46 48 4A 4C 4F 201 201 ========== ============ ======== ======= ======== ======== ========== ======== 202 202 203 203 Currently the driver has support for the input latch, pull-up/pull-down ··· 336 332 - pcal9554b 337 333 - pcal9555a 338 334 - pcal6524 335 335 + - tcal6408 336 336 + - tcal6416 339 337 340 338 2. base offset 0x30, bank 5 and 6, closely packed banks 341 339 - pcal6534 ··· 389 383 Currently the driver enables the latch for each line with interrupt 390 384 enabled. 391 385 386 386 + An interrupt status register records which pins triggered an interrupt. 387 387 + However, the status register and the input port register must be read 388 388 + separately; there is no atomic mechanism to read both simultaneously, so races 389 389 + are possible. Refer to the chapter `Interrupt source detection`_ to understand 390 390 + the implications of this and how the driver still makes use of the latching 391 391 + feature. 392 392 + 392 393 1. base offset 0x40, bank 2, bank offsets of 2^n 393 394 - pcal6408 394 395 - pcal6416 ··· 403 390 - pcal9554b 404 391 - pcal9555a 405 392 - pcal6524 393 393 + - tcal6408 394 394 + - tcal6416 406 395 407 396 2. base offset 0x30, bank 2, closely packed banks 408 397 - pcal6534 ··· 477 462 - pcal9535 478 463 - pcal9554b 479 464 - pcal9555a 465 465 + - tcal6408 466 466 + - tcal6416 480 467 481 468 `PCAL chips with extended interrupt and output configuration functions`_ 482 469 can set this for each line individually. They have the same per-port out_conf ··· 522 505 - pcal9554b 523 506 - pcal9555a 524 507 - pcal6524 508 508 + - tcal6408 509 509 + - tcal6416 525 510 526 511 2. base offset 0x30, bank 0 and 1, closely packed banks 527 512 - pcal6534 528 513 529 514 Currently not supported by the driver. 515 515 + 516 516 + Interrupt source detection 517 517 + ========================== 518 518 + 519 519 + When triggered by the GPIO expander's interrupt, the driver determines which 520 520 + IRQs are pending by reading the input port register. 521 521 + 522 522 + To be able to filter on specific interrupt events for all compatible devices, 523 523 + the driver keeps track of the previous input state of the lines, and emits an 524 524 + IRQ only for the correct edge or level. This system works irrespective of the 525 525 + number of enabled interrupts. Events will not be missed even if they occur 526 526 + between the GPIO expander's interrupt and the actual I2C read. Edges could of 527 527 + course be missed if the related signal level changes back to the value 528 528 + previously saved by the driver before the I2C read. PCAL variants offer input 529 529 + latching for that reason. 530 530 + 531 531 + PCAL input latching 532 532 + ------------------- 533 533 + 534 534 + The PCAL variants have an input latch and the driver enables this for all 535 535 + interrupt-enabled lines. The interrupt is then only cleared when the input port 536 536 + is read out. These variants provide an interrupt status register that records 537 537 + which pins triggered an interrupt, but the status and input registers cannot be 538 538 + read atomically. If another interrupt occurs on a different line after the 539 539 + status register has been read but before the input port register is sampled, 540 540 + that event will not be reflected in the earlier status snapshot, so relying 541 541 + solely on the interrupt status register is insufficient. 542 542 + 543 543 + Thus, the PCAL variants also have to use the existing level-change logic. 544 544 + 545 545 + For short pulses, the first edge is captured when the input register is read, 546 546 + but if the signal returns to its previous level before this read, the second 547 547 + edge is not observed. As a result, successive pulses can produce identical 548 548 + input values at read time and no level change is detected, causing interrupts 549 549 + to be missed. Below timing diagram shows this situation where the top signal is 550 550 + the input pin level and the bottom signal indicates the latched value:: 551 551 + 552 552 + ─────┐ ┌──*───────────────┐ ┌──*─────────────────┐ ┌──*─── 553 553 + │ │ . │ │ . │ │ . 554 554 + │ │ │ │ │ │ │ │ │ 555 555 + └──*──┘ │ └──*──┘ │ └──*──┘ │ 556 556 + Input │ │ │ │ │ │ 557 557 + ▼ │ ▼ │ ▼ │ 558 558 + IRQ │ IRQ │ IRQ │ 559 559 + . . . 560 560 + ─────┐ .┌──────────────┐ .┌────────────────┐ .┌── 561 561 + │ │ │ │ │ │ 562 562 + │ │ │ │ │ │ 563 563 + └────────*┘ └────────*┘ └────────*┘ 564 564 + Latched │ │ │ 565 565 + ▼ ▼ ▼ 566 566 + READ 0 READ 0 READ 0 567 567 + NO CHANGE NO CHANGE 568 568 + 569 569 + To deal with this, events indicated by the interrupt status register are merged 570 570 + with events detected through the existing level-change logic. As a result: 571 571 + 572 572 + - short pulses, whose second edges are invisible, are detected via the 573 573 + interrupt status register, and 574 574 + - interrupts that occur between the status and input reads are still 575 575 + caught by the generic level-change logic. 576 576 + 577 577 + Note that this is still best-effort: the status and input registers are read 578 578 + separately, and short pulses on other lines may occur in between those reads. 579 579 + Such pulses can still be latched as an interrupt without leaving an observable 580 580 + level change at read time, and may not be attributable to a specific edge. This 581 581 + does not reduce detection compared to the generic path, but reflects inherent 582 582 + atomicity limitations. 530 583 531 584 Datasheets 532 585 ==========

+8

MAINTAINERS

reviewed

··· 10816 10816 F: Documentation/devicetree/bindings/leds/irled/gpio-ir-tx.yaml 10817 10817 F: drivers/media/rc/gpio-ir-tx.c 10818 10818 10819 10819 + GPIO LINE MUX 10820 10820 + M: Jonas Jelonek <jelonek.jonas@gmail.com> 10821 10821 + S: Maintained 10822 10822 + F: Documentation/devicetree/bindings/gpio/gpio-line-mux.yaml 10823 10823 + F: drivers/gpio/gpio-line-mux.c 10824 10824 + 10819 10825 GPIO MOCKUP DRIVER 10820 10826 M: Bamvor Jian Zhang <bamv2005@gmail.com> 10821 10827 L: linux-gpio@vger.kernel.org ··· 22842 22836 F: drivers/clk/clk-bd718x7.c 22843 22837 F: drivers/gpio/gpio-bd71815.c 22844 22838 F: drivers/gpio/gpio-bd71828.c 22839 22839 + F: drivers/gpio/gpio-bd72720.c 22845 22840 F: drivers/mfd/rohm-bd71828.c 22846 22841 F: drivers/mfd/rohm-bd718x7.c 22847 22842 F: drivers/mfd/rohm-bd9576.c ··· 22859 22852 F: include/linux/mfd/rohm-bd71815.h 22860 22853 F: include/linux/mfd/rohm-bd71828.h 22861 22854 F: include/linux/mfd/rohm-bd718x7.h 22855 22855 + F: include/linux/mfd/rohm-bd72720.h 22862 22856 F: include/linux/mfd/rohm-bd957x.h 22863 22857 F: include/linux/mfd/rohm-bd96801.h 22864 22858 F: include/linux/mfd/rohm-bd96802.h

+2 -2

drivers/clk/Kconfig

reviewed

··· 475 475 tristate "Clock driver for 32K clk gates on ROHM PMICs" 476 476 depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828 477 477 help 478 478 - This driver supports ROHM BD71837, BD71847, BD71850, BD71815 479 479 - and BD71828 PMICs clock gates. 478 478 + This driver supports ROHM BD71837, BD71847, BD71850, BD71815, 479 479 + BD71828, and BD72720 PMICs clock gates. 480 480 481 481 config COMMON_CLK_FIXED_MMIO 482 482 bool "Clock driver for Memory Mapped Fixed values"

+8 -2

drivers/clk/clk-bd718x7.c

reviewed

··· 19 19 #define BD71828_REG_OUT32K 0x4B 20 20 /* BD71837 and BD71847 */ 21 21 #define BD718XX_REG_OUT32K 0x2E 22 22 - 22 22 + /* BD72720 */ 23 23 + #define BD72720_REG_OUT32K 0x9a 23 24 /* 24 25 * BD71837, BD71847, and BD71828 all use bit [0] to clk output control 25 26 */ ··· 119 118 c->reg = BD71815_REG_OUT32K; 120 119 c->mask = CLK_OUT_EN_MASK; 121 120 break; 121 121 + case ROHM_CHIP_TYPE_BD72720: 122 122 + c->reg = BD72720_REG_OUT32K; 123 123 + c->mask = CLK_OUT_EN_MASK; 124 124 + break; 122 125 default: 123 126 dev_err(&pdev->dev, "Unknown clk chip\n"); 124 127 return -EINVAL; ··· 151 146 { "bd71847-clk", ROHM_CHIP_TYPE_BD71847 }, 152 147 { "bd71828-clk", ROHM_CHIP_TYPE_BD71828 }, 153 148 { "bd71815-clk", ROHM_CHIP_TYPE_BD71815 }, 149 149 + { "bd72720-clk", ROHM_CHIP_TYPE_BD72720 }, 154 150 { }, 155 151 }; 156 152 MODULE_DEVICE_TABLE(platform, bd718x7_clk_id); ··· 167 161 module_platform_driver(bd71837_clk); 168 162 169 163 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 170 170 - MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and chip clk driver"); 164 164 + MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and BD72720 chip clk driver"); 171 165 MODULE_LICENSE("GPL"); 172 166 MODULE_ALIAS("platform:bd718xx-clk");

+21 -3

drivers/gpio/Kconfig

reviewed

··· 600 600 601 601 config GPIO_REALTEK_OTTO 602 602 tristate "Realtek Otto GPIO support" 603 603 - depends on MACH_REALTEK_RTL 603 603 + depends on MACH_REALTEK_RTL || COMPILE_TEST 604 604 default MACH_REALTEK_RTL 605 605 select GPIO_GENERIC 606 606 select GPIOLIB_IRQCHIP ··· 1193 1193 1194 1194 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554, 1195 1195 pca9556, pca9557, pca9574, tca6408, tca9554, xra1202, 1196 1196 - pcal6408, pcal9554b, tca9538 1196 1196 + pcal6408, pcal9554b, tca9538, tcal6408 1197 1197 1198 1198 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575, 1199 1199 tca6416, pca6416, pcal6416, pcal9535, pcal9555a, max7318, 1200 1200 - tca9539 1200 1200 + tca9539, tcal6416 1201 1201 1202 1202 18 bits: tca6418 1203 1203 ··· 1316 1316 1317 1317 This driver can also be built as a module. If so, the module 1318 1318 will be called gpio-bd71828. 1319 1319 + 1320 1320 + config GPIO_BD72720 1321 1321 + tristate "ROHM BD72720 and BD73900 PMIC GPIO support" 1322 1322 + depends on MFD_ROHM_BD71828 1323 1323 + help 1324 1324 + Support for GPIO on ROHM BD72720 and BD73900 PMICs. There are two 1325 1325 + pins which can be configured to GPI or GPO, and three pins which can 1326 1326 + be configured to GPO on the ROHM PMIC. The pin configuration is done 1327 1327 + on OTP at manufacturing. 1319 1328 1320 1329 config GPIO_BD9571MWV 1321 1330 tristate "ROHM BD9571 GPIO support" ··· 2002 1993 help 2003 1994 Say yes here to enable a driver for GPIO multiplexers based on latches 2004 1995 connected to other GPIOs. 1996 1996 + 1997 1997 + config GPIO_LINE_MUX 1998 1998 + tristate "GPIO line mux driver" 1999 1999 + depends on OF_GPIO 2000 2000 + select MULTIPLEXER 2001 2001 + help 2002 2002 + Say Y here to support the GPIO line mux, which can provide virtual 2003 2003 + GPIOs backed by a shared real GPIO and a multiplexer in a 1-to-many 2004 2004 + fashion. 2005 2005 2006 2006 config GPIO_MOCKUP 2007 2007 tristate "GPIO Testing Driver (DEPRECATED)"

+2

drivers/gpio/Makefile

reviewed

··· 46 46 obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o 47 47 obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o 48 48 obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o 49 49 + obj-$(CONFIG_GPIO_BD72720) += gpio-bd72720.o 49 50 obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o 50 51 obj-$(CONFIG_GPIO_BLZP1600) += gpio-blzp1600.o 51 52 obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o ··· 91 90 obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o 92 91 obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o 93 92 obj-$(CONFIG_GPIO_LATCH) += gpio-latch.o 93 93 + obj-$(CONFIG_GPIO_LINE_MUX) += gpio-line-mux.o 94 94 obj-$(CONFIG_GPIO_LJCA) += gpio-ljca.o 95 95 obj-$(CONFIG_GPIO_LOGICVC) += gpio-logicvc.o 96 96 obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o

+4 -4

drivers/gpio/gpio-aggregator.c

reviewed

··· 1226 1226 kfree(line); 1227 1227 } 1228 1228 1229 1229 - static struct configfs_item_operations gpio_aggregator_line_item_ops = { 1229 1229 + static const struct configfs_item_operations gpio_aggregator_line_item_ops = { 1230 1230 .release = gpio_aggregator_line_release, 1231 1231 }; 1232 1232 ··· 1247 1247 gpio_aggregator_free(aggr); 1248 1248 } 1249 1249 1250 1250 - static struct configfs_item_operations gpio_aggregator_device_item_ops = { 1250 1250 + static const struct configfs_item_operations gpio_aggregator_device_item_ops = { 1251 1251 .release = gpio_aggregator_device_release, 1252 1252 }; 1253 1253 ··· 1292 1292 return &line->group; 1293 1293 } 1294 1294 1295 1295 - static struct configfs_group_operations gpio_aggregator_device_group_ops = { 1295 1295 + static const struct configfs_group_operations gpio_aggregator_device_group_ops = { 1296 1296 .make_group = gpio_aggregator_device_make_group, 1297 1297 }; 1298 1298 ··· 1328 1328 return &aggr->group; 1329 1329 } 1330 1330 1331 1331 - static struct configfs_group_operations gpio_aggregator_group_ops = { 1331 1331 + static const struct configfs_group_operations gpio_aggregator_group_ops = { 1332 1332 .make_group = gpio_aggregator_make_group, 1333 1333 }; 1334 1334

+224 -138

drivers/gpio/gpio-aspeed-sgpio.c

reviewed

··· 19 19 #include <linux/spinlock.h> 20 20 #include <linux/string.h> 21 21 22 22 - #define ASPEED_SGPIO_CTRL 0x54 22 22 + #define SGPIO_G7_IRQ_STS_BASE 0x40 23 23 + #define SGPIO_G7_IRQ_STS_OFFSET(x) (SGPIO_G7_IRQ_STS_BASE + (x) * 0x4) 24 24 + #define SGPIO_G7_CTRL_REG_BASE 0x80 25 25 + #define SGPIO_G7_CTRL_REG_OFFSET(x) (SGPIO_G7_CTRL_REG_BASE + (x) * 0x4) 26 26 + #define SGPIO_G7_OUT_DATA BIT(0) 27 27 + #define SGPIO_G7_PARALLEL_OUT_DATA BIT(1) 28 28 + #define SGPIO_G7_IRQ_EN BIT(2) 29 29 + #define SGPIO_G7_IRQ_TYPE0 BIT(3) 30 30 + #define SGPIO_G7_IRQ_TYPE1 BIT(4) 31 31 + #define SGPIO_G7_IRQ_TYPE2 BIT(5) 32 32 + #define SGPIO_G7_RST_TOLERANCE BIT(6) 33 33 + #define SGPIO_G7_INPUT_MASK BIT(9) 34 34 + #define SGPIO_G7_HW_BYPASS_EN BIT(10) 35 35 + #define SGPIO_G7_HW_IN_SEL BIT(11) 36 36 + #define SGPIO_G7_IRQ_STS BIT(12) 37 37 + #define SGPIO_G7_IN_DATA BIT(13) 38 38 + #define SGPIO_G7_PARALLEL_IN_DATA BIT(14) 39 39 + #define SGPIO_G7_SERIAL_OUT_SEL GENMASK(17, 16) 40 40 + #define SGPIO_G7_PARALLEL_OUT_SEL GENMASK(19, 18) 41 41 + #define SELECT_FROM_CSR 0 42 42 + #define SELECT_FROM_PARALLEL_IN 1 43 43 + #define SELECT_FROM_SERIAL_IN 2 44 44 + 45 45 + #define ASPEED_SGPIO_G4_CFG_OFFSET 0x54 46 46 + #define ASPEED_SGPIO_G7_CFG_OFFSET 0x0 23 47 24 48 #define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16) 25 49 #define ASPEED_SGPIO_ENABLE BIT(0) ··· 51 27 52 28 struct aspeed_sgpio_pdata { 53 29 const u32 pin_mask; 30 30 + const struct aspeed_sgpio_llops *llops; 31 31 + const u32 cfg_offset; 54 32 }; 55 33 56 34 struct aspeed_sgpio { ··· 62 36 raw_spinlock_t lock; 63 37 void __iomem *base; 64 38 int irq; 39 39 + const struct aspeed_sgpio_pdata *pdata; 65 40 }; 66 41 67 42 struct aspeed_sgpio_bank { ··· 70 43 u16 rdata_reg; 71 44 u16 irq_regs; 72 45 u16 tolerance_regs; 73 73 - const char names[4][3]; 74 46 }; 75 47 76 48 /* ··· 85 59 .rdata_reg = 0x0070, 86 60 .irq_regs = 0x0004, 87 61 .tolerance_regs = 0x0018, 88 88 - .names = { "A", "B", "C", "D" }, 89 62 }, 90 63 { 91 64 .val_regs = 0x001C, 92 65 .rdata_reg = 0x0074, 93 66 .irq_regs = 0x0020, 94 67 .tolerance_regs = 0x0034, 95 95 - .names = { "E", "F", "G", "H" }, 96 68 }, 97 69 { 98 70 .val_regs = 0x0038, 99 71 .rdata_reg = 0x0078, 100 72 .irq_regs = 0x003C, 101 73 .tolerance_regs = 0x0050, 102 102 - .names = { "I", "J", "K", "L" }, 103 74 }, 104 75 { 105 76 .val_regs = 0x0090, 106 77 .rdata_reg = 0x007C, 107 78 .irq_regs = 0x0094, 108 79 .tolerance_regs = 0x00A8, 109 109 - .names = { "M", "N", "O", "P" }, 110 80 }, 111 81 }; 112 82 ··· 117 95 reg_tolerance, 118 96 }; 119 97 98 98 + struct aspeed_sgpio_llops { 99 99 + void (*reg_bit_set)(struct aspeed_sgpio *gpio, unsigned int offset, 100 100 + const enum aspeed_sgpio_reg reg, bool val); 101 101 + bool (*reg_bit_get)(struct aspeed_sgpio *gpio, unsigned int offset, 102 102 + const enum aspeed_sgpio_reg reg); 103 103 + int (*reg_bank_get)(struct aspeed_sgpio *gpio, unsigned int offset, 104 104 + const enum aspeed_sgpio_reg reg); 105 105 + }; 106 106 + 120 107 #define GPIO_VAL_VALUE 0x00 121 108 #define GPIO_IRQ_ENABLE 0x00 122 109 #define GPIO_IRQ_TYPE0 0x04 ··· 133 102 #define GPIO_IRQ_TYPE2 0x0C 134 103 #define GPIO_IRQ_STATUS 0x10 135 104 136 136 - static void __iomem *bank_reg(struct aspeed_sgpio *gpio, 137 137 - const struct aspeed_sgpio_bank *bank, 138 138 - const enum aspeed_sgpio_reg reg) 105 105 + static void __iomem *aspeed_sgpio_g4_bank_reg(struct aspeed_sgpio *gpio, 106 106 + const struct aspeed_sgpio_bank *bank, 107 107 + const enum aspeed_sgpio_reg reg) 139 108 { 140 109 switch (reg) { 141 110 case reg_val: ··· 157 126 default: 158 127 /* acturally if code runs to here, it's an error case */ 159 128 BUG(); 129 129 + } 130 130 + } 131 131 + 132 132 + static u32 aspeed_sgpio_g7_reg_mask(const enum aspeed_sgpio_reg reg) 133 133 + { 134 134 + switch (reg) { 135 135 + case reg_val: 136 136 + case reg_rdata: 137 137 + return SGPIO_G7_OUT_DATA; 138 138 + case reg_irq_enable: 139 139 + return SGPIO_G7_IRQ_EN; 140 140 + case reg_irq_type0: 141 141 + return SGPIO_G7_IRQ_TYPE0; 142 142 + case reg_irq_type1: 143 143 + return SGPIO_G7_IRQ_TYPE1; 144 144 + case reg_irq_type2: 145 145 + return SGPIO_G7_IRQ_TYPE2; 146 146 + case reg_irq_status: 147 147 + return SGPIO_G7_IRQ_STS; 148 148 + case reg_tolerance: 149 149 + return SGPIO_G7_RST_TOLERANCE; 150 150 + default: 151 151 + WARN_ON_ONCE(1); 152 152 + return 0; 160 153 } 161 154 } 162 155 ··· 225 170 static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset) 226 171 { 227 172 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); 228 228 - const struct aspeed_sgpio_bank *bank = to_bank(offset); 229 173 enum aspeed_sgpio_reg reg; 230 174 int rc = 0; 231 175 232 176 guard(raw_spinlock_irqsave)(&gpio->lock); 233 177 234 178 reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata; 235 235 - rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); 179 179 + rc = gpio->pdata->llops->reg_bit_get(gpio, offset, reg); 236 180 237 181 return rc; 238 182 } ··· 239 185 static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val) 240 186 { 241 187 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); 242 242 - const struct aspeed_sgpio_bank *bank = to_bank(offset); 243 243 - void __iomem *addr_r, *addr_w; 244 244 - u32 reg = 0; 245 188 246 189 if (aspeed_sgpio_is_input(offset)) 247 190 return -EINVAL; 248 191 249 249 - /* Since this is an output, read the cached value from rdata, then 250 250 - * update val. */ 251 251 - addr_r = bank_reg(gpio, bank, reg_rdata); 252 252 - addr_w = bank_reg(gpio, bank, reg_val); 253 253 - 254 254 - reg = ioread32(addr_r); 255 255 - 256 256 - if (val) 257 257 - reg |= GPIO_BIT(offset); 258 258 - else 259 259 - reg &= ~GPIO_BIT(offset); 260 260 - 261 261 - iowrite32(reg, addr_w); 192 192 + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_val, val); 262 193 263 194 return 0; 264 195 } ··· 282 243 return !!aspeed_sgpio_is_input(offset); 283 244 } 284 245 285 285 - static void irqd_to_aspeed_sgpio_data(struct irq_data *d, 286 286 - struct aspeed_sgpio **gpio, 287 287 - const struct aspeed_sgpio_bank **bank, 288 288 - u32 *bit, int *offset) 289 289 - { 290 290 - struct aspeed_sgpio *internal; 291 291 - 292 292 - *offset = irqd_to_hwirq(d); 293 293 - internal = irq_data_get_irq_chip_data(d); 294 294 - WARN_ON(!internal); 295 295 - 296 296 - *gpio = internal; 297 297 - *bank = to_bank(*offset); 298 298 - *bit = GPIO_BIT(*offset); 299 299 - } 300 246 301 247 static void aspeed_sgpio_irq_ack(struct irq_data *d) 302 248 { 303 303 - const struct aspeed_sgpio_bank *bank; 304 304 - struct aspeed_sgpio *gpio; 305 305 - void __iomem *status_addr; 306 306 - int offset; 307 307 - u32 bit; 308 308 - 309 309 - irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); 310 310 - 311 311 - status_addr = bank_reg(gpio, bank, reg_irq_status); 249 249 + struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d); 250 250 + int offset = irqd_to_hwirq(d); 312 251 313 252 guard(raw_spinlock_irqsave)(&gpio->lock); 314 253 315 315 - iowrite32(bit, status_addr); 254 254 + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); 316 255 } 317 256 318 257 static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set) 319 258 { 320 320 - const struct aspeed_sgpio_bank *bank; 321 321 - struct aspeed_sgpio *gpio; 322 322 - u32 reg, bit; 323 323 - void __iomem *addr; 324 324 - int offset; 325 325 - 326 326 - irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); 327 327 - addr = bank_reg(gpio, bank, reg_irq_enable); 259 259 + struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d); 260 260 + int offset = irqd_to_hwirq(d); 328 261 329 262 /* Unmasking the IRQ */ 330 263 if (set) 331 331 - gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); 332 332 - 333 333 - scoped_guard(raw_spinlock_irqsave, &gpio->lock) { 334 334 - reg = ioread32(addr); 335 335 - if (set) 336 336 - reg |= bit; 337 337 - else 338 338 - reg &= ~bit; 339 339 - 340 340 - iowrite32(reg, addr); 264 264 + gpiochip_enable_irq(&gpio->chip, offset); 265 265 + scoped_guard(raw_spinlock_irqsave, &gpio->lock) 266 266 + { 267 267 + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_enable, 268 268 + set); 341 269 } 342 270 343 271 /* Masking the IRQ */ 344 272 if (!set) 345 345 - gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); 346 346 - 347 347 - 273 273 + gpiochip_disable_irq(&gpio->chip, offset); 348 274 } 349 275 350 276 static void aspeed_sgpio_irq_mask(struct irq_data *d) ··· 327 323 u32 type0 = 0; 328 324 u32 type1 = 0; 329 325 u32 type2 = 0; 330 330 - u32 bit, reg; 331 331 - const struct aspeed_sgpio_bank *bank; 332 326 irq_flow_handler_t handler; 333 333 - struct aspeed_sgpio *gpio; 334 334 - void __iomem *addr; 335 335 - int offset; 336 336 - 337 337 - irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); 327 327 + struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d); 328 328 + int offset = irqd_to_hwirq(d); 338 329 339 330 switch (type & IRQ_TYPE_SENSE_MASK) { 340 331 case IRQ_TYPE_EDGE_BOTH: 341 341 - type2 |= bit; 332 332 + type2 = 1; 342 333 fallthrough; 343 334 case IRQ_TYPE_EDGE_RISING: 344 344 - type0 |= bit; 335 335 + type0 = 1; 345 336 fallthrough; 346 337 case IRQ_TYPE_EDGE_FALLING: 347 338 handler = handle_edge_irq; 348 339 break; 349 340 case IRQ_TYPE_LEVEL_HIGH: 350 350 - type0 |= bit; 341 341 + type0 = 1; 351 342 fallthrough; 352 343 case IRQ_TYPE_LEVEL_LOW: 353 353 - type1 |= bit; 344 344 + type1 = 1; 354 345 handler = handle_level_irq; 355 346 break; 356 347 default: ··· 353 354 } 354 355 355 356 scoped_guard(raw_spinlock_irqsave, &gpio->lock) { 356 356 - addr = bank_reg(gpio, bank, reg_irq_type0); 357 357 - reg = ioread32(addr); 358 358 - reg = (reg & ~bit) | type0; 359 359 - iowrite32(reg, addr); 360 360 - 361 361 - addr = bank_reg(gpio, bank, reg_irq_type1); 362 362 - reg = ioread32(addr); 363 363 - reg = (reg & ~bit) | type1; 364 364 - iowrite32(reg, addr); 365 365 - 366 366 - addr = bank_reg(gpio, bank, reg_irq_type2); 367 367 - reg = ioread32(addr); 368 368 - reg = (reg & ~bit) | type2; 369 369 - iowrite32(reg, addr); 357 357 + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type0, type0); 358 358 + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type1, type1); 359 359 + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type2, type2); 370 360 } 371 361 372 362 irq_set_handler_locked(d, handler); ··· 368 380 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 369 381 struct irq_chip *ic = irq_desc_get_chip(desc); 370 382 struct aspeed_sgpio *data = gpiochip_get_data(gc); 371 371 - unsigned int i, p; 383 383 + unsigned int i, p, banks; 372 384 unsigned long reg; 373 385 374 386 chained_irq_enter(ic, desc); 375 387 376 376 - for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) { 377 377 - const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i]; 378 378 - 379 379 - reg = ioread32(bank_reg(data, bank, reg_irq_status)); 388 388 + banks = DIV_ROUND_UP(gc->ngpio, 64); 389 389 + for (i = 0; i < banks; i++) { 390 390 + reg = data->pdata->llops->reg_bank_get(data, i << 6, reg_irq_status); 380 391 381 392 for_each_set_bit(p, &reg, 32) 382 393 generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2); ··· 386 399 387 400 static void aspeed_sgpio_irq_print_chip(struct irq_data *d, struct seq_file *p) 388 401 { 389 389 - const struct aspeed_sgpio_bank *bank; 390 390 - struct aspeed_sgpio *gpio; 391 391 - u32 bit; 392 392 - int offset; 402 402 + struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d); 393 403 394 394 - irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); 395 404 seq_puts(p, dev_name(gpio->dev)); 396 405 } 397 406 ··· 405 422 struct platform_device *pdev) 406 423 { 407 424 int rc, i; 408 408 - const struct aspeed_sgpio_bank *bank; 409 425 struct gpio_irq_chip *irq; 410 426 411 427 rc = platform_get_irq(pdev, 0); ··· 414 432 gpio->irq = rc; 415 433 416 434 /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */ 417 417 - for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) { 418 418 - bank = &aspeed_sgpio_banks[i]; 435 435 + for (i = 0; i < gpio->chip.ngpio; i += 2) { 419 436 /* disable irq enable bits */ 420 420 - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable)); 437 437 + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_enable, 0); 421 438 /* clear status bits */ 422 422 - iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status)); 439 439 + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_status, 1); 423 440 } 424 441 425 442 irq = &gpio->chip.irq; ··· 432 451 irq->num_parents = 1; 433 452 434 453 /* Apply default IRQ settings */ 435 435 - for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) { 436 436 - bank = &aspeed_sgpio_banks[i]; 454 454 + for (i = 0; i < gpio->chip.ngpio; i += 2) { 437 455 /* set falling or level-low irq */ 438 438 - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0)); 456 456 + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type0, 0); 439 457 /* trigger type is edge */ 440 440 - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1)); 458 458 + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type1, 0); 441 459 /* single edge trigger */ 442 442 - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2)); 460 460 + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type2, 0); 443 461 } 444 462 445 463 return 0; 446 464 } 447 465 466 466 + static void aspeed_sgpio_g4_reg_bit_set(struct aspeed_sgpio *gpio, unsigned int offset, 467 467 + const enum aspeed_sgpio_reg reg, bool val) 468 468 + { 469 469 + const struct aspeed_sgpio_bank *bank = to_bank(offset); 470 470 + void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg); 471 471 + u32 temp; 472 472 + 473 473 + if (reg == reg_val) { 474 474 + /* Since this is an output, read the cached value from rdata, then update val. */ 475 475 + addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg_rdata); 476 476 + temp = ioread32(addr); 477 477 + if (val) 478 478 + temp |= GPIO_BIT(offset); 479 479 + else 480 480 + temp &= ~GPIO_BIT(offset); 481 481 + 482 482 + addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg_val); 483 483 + iowrite32(temp, addr); 484 484 + } else if (reg == reg_irq_status) { 485 485 + if (val) 486 486 + iowrite32(GPIO_BIT(offset), addr); 487 487 + } else { 488 488 + /* When setting other registers, we read from the register itself */ 489 489 + temp = ioread32(addr); 490 490 + if (val) 491 491 + temp |= GPIO_BIT(offset); 492 492 + else 493 493 + temp &= ~GPIO_BIT(offset); 494 494 + iowrite32(temp, addr); 495 495 + } 496 496 + } 497 497 + 498 498 + static bool aspeed_sgpio_g4_reg_bit_get(struct aspeed_sgpio *gpio, unsigned int offset, 499 499 + const enum aspeed_sgpio_reg reg) 500 500 + { 501 501 + const struct aspeed_sgpio_bank *bank = to_bank(offset); 502 502 + void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg); 503 503 + 504 504 + return !!(ioread32(addr) & GPIO_BIT(offset)); 505 505 + } 506 506 + 507 507 + static int aspeed_sgpio_g4_reg_bank_get(struct aspeed_sgpio *gpio, unsigned int offset, 508 508 + const enum aspeed_sgpio_reg reg) 509 509 + { 510 510 + const struct aspeed_sgpio_bank *bank = to_bank(offset); 511 511 + void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg); 512 512 + 513 513 + if (reg == reg_irq_status) 514 514 + return ioread32(addr); 515 515 + else 516 516 + return -EOPNOTSUPP; 517 517 + } 518 518 + 519 519 + static const struct aspeed_sgpio_llops aspeed_sgpio_g4_llops = { 520 520 + .reg_bit_set = aspeed_sgpio_g4_reg_bit_set, 521 521 + .reg_bit_get = aspeed_sgpio_g4_reg_bit_get, 522 522 + .reg_bank_get = aspeed_sgpio_g4_reg_bank_get, 523 523 + }; 524 524 + 448 525 static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = { 449 526 .pin_mask = GENMASK(9, 6), 527 527 + .llops = &aspeed_sgpio_g4_llops, 528 528 + .cfg_offset = ASPEED_SGPIO_G4_CFG_OFFSET, 450 529 }; 451 530 452 531 static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip, 453 532 unsigned int offset, bool enable) 454 533 { 455 534 struct aspeed_sgpio *gpio = gpiochip_get_data(chip); 456 456 - void __iomem *reg; 457 457 - u32 val; 458 458 - 459 459 - reg = bank_reg(gpio, to_bank(offset), reg_tolerance); 460 535 461 536 guard(raw_spinlock_irqsave)(&gpio->lock); 462 537 463 463 - val = readl(reg); 464 464 - 465 465 - if (enable) 466 466 - val |= GPIO_BIT(offset); 467 467 - else 468 468 - val &= ~GPIO_BIT(offset); 469 469 - 470 470 - writel(val, reg); 538 538 + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); 471 539 472 540 return 0; 473 541 } ··· 535 505 536 506 static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = { 537 507 .pin_mask = GENMASK(10, 6), 508 508 + .llops = &aspeed_sgpio_g4_llops, 509 509 + .cfg_offset = ASPEED_SGPIO_G4_CFG_OFFSET, 510 510 + }; 511 511 + 512 512 + static void aspeed_sgpio_g7_reg_bit_set(struct aspeed_sgpio *gpio, unsigned int offset, 513 513 + const enum aspeed_sgpio_reg reg, bool val) 514 514 + { 515 515 + u32 mask = aspeed_sgpio_g7_reg_mask(reg); 516 516 + void __iomem *addr = gpio->base + SGPIO_G7_CTRL_REG_OFFSET(offset >> 1); 517 517 + u32 write_val; 518 518 + 519 519 + if (mask) { 520 520 + write_val = (ioread32(addr) & ~(mask)) | field_prep(mask, val); 521 521 + iowrite32(write_val, addr); 522 522 + } 523 523 + } 524 524 + 525 525 + static bool aspeed_sgpio_g7_reg_bit_get(struct aspeed_sgpio *gpio, unsigned int offset, 526 526 + const enum aspeed_sgpio_reg reg) 527 527 + { 528 528 + u32 mask = aspeed_sgpio_g7_reg_mask(reg); 529 529 + void __iomem *addr; 530 530 + 531 531 + addr = gpio->base + SGPIO_G7_CTRL_REG_OFFSET(offset >> 1); 532 532 + if (reg == reg_val) 533 533 + mask = SGPIO_G7_IN_DATA; 534 534 + 535 535 + if (mask) 536 536 + return field_get(mask, ioread32(addr)); 537 537 + else 538 538 + return 0; 539 539 + } 540 540 + 541 541 + static int aspeed_sgpio_g7_reg_bank_get(struct aspeed_sgpio *gpio, unsigned int offset, 542 542 + const enum aspeed_sgpio_reg reg) 543 543 + { 544 544 + void __iomem *addr; 545 545 + 546 546 + if (reg == reg_irq_status) { 547 547 + addr = gpio->base + SGPIO_G7_IRQ_STS_OFFSET(offset >> 6); 548 548 + return ioread32(addr); 549 549 + } else { 550 550 + return -EOPNOTSUPP; 551 551 + } 552 552 + } 553 553 + 554 554 + static const struct aspeed_sgpio_llops aspeed_sgpio_g7_llops = { 555 555 + .reg_bit_set = aspeed_sgpio_g7_reg_bit_set, 556 556 + .reg_bit_get = aspeed_sgpio_g7_reg_bit_get, 557 557 + .reg_bank_get = aspeed_sgpio_g7_reg_bank_get, 558 558 + }; 559 559 + 560 560 + static const struct aspeed_sgpio_pdata ast2700_sgpiom_pdata = { 561 561 + .pin_mask = GENMASK(11, 6), 562 562 + .llops = &aspeed_sgpio_g7_llops, 563 563 + .cfg_offset = ASPEED_SGPIO_G7_CFG_OFFSET, 538 564 }; 539 565 540 566 static const struct of_device_id aspeed_sgpio_of_table[] = { 541 567 { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, }, 542 568 { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, }, 543 569 { .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, }, 570 570 + { .compatible = "aspeed,ast2700-sgpiom", .data = &ast2700_sgpiom_pdata, }, 544 571 {} 545 572 }; 546 573 547 574 MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table); 548 575 549 549 - static int __init aspeed_sgpio_probe(struct platform_device *pdev) 576 576 + static int aspeed_sgpio_probe(struct platform_device *pdev) 550 577 { 551 578 u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask; 552 552 - const struct aspeed_sgpio_pdata *pdata; 553 579 struct aspeed_sgpio *gpio; 554 580 unsigned long apb_freq; 555 581 int rc; ··· 620 534 621 535 gpio->dev = &pdev->dev; 622 536 623 623 - pdata = device_get_match_data(&pdev->dev); 624 624 - if (!pdata) 537 537 + gpio->pdata = device_get_match_data(&pdev->dev); 538 538 + if (!gpio->pdata) 625 539 return -EINVAL; 626 540 627 627 - pin_mask = pdata->pin_mask; 628 628 - 541 541 + pin_mask = gpio->pdata->pin_mask; 629 542 rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios); 630 543 if (rc < 0) { 631 544 dev_err(&pdev->dev, "Could not read ngpios property\n"); ··· 668 583 669 584 gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask; 670 585 iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval | 671 671 - ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL); 586 586 + ASPEED_SGPIO_ENABLE, gpio->base + gpio->pdata->cfg_offset); 672 587 673 588 raw_spin_lock_init(&gpio->lock); 674 589 ··· 696 611 } 697 612 698 613 static struct platform_driver aspeed_sgpio_driver = { 614 614 + .probe = aspeed_sgpio_probe, 699 615 .driver = { 700 616 .name = KBUILD_MODNAME, 701 617 .of_match_table = aspeed_sgpio_of_table, 702 618 }, 703 619 }; 704 620 705 705 - module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe); 621 621 + module_platform_driver(aspeed_sgpio_driver); 706 622 MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");

+2 -5

drivers/gpio/gpio-aspeed.c

reviewed

··· 1302 1302 1303 1303 static int aspeed_gpio_probe(struct platform_device *pdev) 1304 1304 { 1305 1305 - const struct of_device_id *gpio_id; 1306 1305 struct gpio_irq_chip *girq; 1307 1306 struct aspeed_gpio *gpio; 1308 1307 int rc, irq, i, banks, err; ··· 1319 1320 1320 1321 raw_spin_lock_init(&gpio->lock); 1321 1322 1322 1322 - gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); 1323 1323 - if (!gpio_id) 1323 1323 + gpio->config = device_get_match_data(&pdev->dev); 1324 1324 + if (!gpio->config) 1324 1325 return -EINVAL; 1325 1326 1326 1327 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); ··· 1329 1330 "Failed to get clock from devicetree, debouncing disabled\n"); 1330 1331 gpio->clk = NULL; 1331 1332 } 1332 1332 - 1333 1333 - gpio->config = gpio_id->data; 1334 1333 1335 1334 if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bit_get || 1336 1335 !gpio->config->llops->reg_bank_get)

+281

drivers/gpio/gpio-bd72720.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Support to GPIOs on ROHM BD72720 and BD79300 4 4 + * Copyright 2025 ROHM Semiconductors. 5 5 + * Author: Matti Vaittinen <mazziesaccount@gmail.com> 6 6 + */ 7 7 + 8 8 + #include <linux/gpio/driver.h> 9 9 + #include <linux/init.h> 10 10 + #include <linux/irq.h> 11 11 + #include <linux/module.h> 12 12 + #include <linux/of.h> 13 13 + #include <linux/platform_device.h> 14 14 + #include <linux/mfd/rohm-bd72720.h> 15 15 + 16 16 + #define BD72720_GPIO_OPEN_DRAIN 0 17 17 + #define BD72720_GPIO_CMOS BIT(1) 18 18 + #define BD72720_INT_GPIO1_IN_SRC 4 19 19 + /* 20 20 + * The BD72720 has several "one time programmable" (OTP) configurations which 21 21 + * can be set at manufacturing phase. A set of these options allow using pins 22 22 + * as GPIO. The OTP configuration can't be read at run-time, so drivers rely on 23 23 + * device-tree to advertise the correct options. 24 24 + * 25 25 + * Both DVS[0,1] pins can be configured to be used for: 26 26 + * - OTP0: regulator RUN state control 27 27 + * - OTP1: GPI 28 28 + * - OTP2: GPO 29 29 + * - OTP3: Power sequencer output 30 30 + * Data-sheet also states that these PINs can always be used for IRQ but the 31 31 + * driver limits this by allowing them to be used for IRQs with OTP1 only. 32 32 + * 33 33 + * Pins GPIO_EXTEN0 (GPIO3), GPIO_EXTEN1 (GPIO4), GPIO_FAULT_B (GPIO5) have OTP 34 34 + * options for a specific (non GPIO) purposes, but also an option to configure 35 35 + * them to be used as a GPO. 36 36 + * 37 37 + * OTP settings can be separately configured for each pin. 38 38 + * 39 39 + * DT properties: 40 40 + * "rohm,pin-dvs0" and "rohm,pin-dvs1" can be set to one of the values: 41 41 + * "dvs-input", "gpi", "gpo". 42 42 + * 43 43 + * "rohm,pin-exten0", "rohm,pin-exten1" and "rohm,pin-fault_b" can be set to: 44 44 + * "gpo" 45 45 + */ 46 46 + 47 47 + enum bd72720_gpio_state { 48 48 + BD72720_PIN_UNKNOWN, 49 49 + BD72720_PIN_GPI, 50 50 + BD72720_PIN_GPO, 51 51 + }; 52 52 + 53 53 + enum { 54 54 + BD72720_GPIO1, 55 55 + BD72720_GPIO2, 56 56 + BD72720_GPIO3, 57 57 + BD72720_GPIO4, 58 58 + BD72720_GPIO5, 59 59 + BD72720_GPIO_EPDEN, 60 60 + BD72720_NUM_GPIOS 61 61 + }; 62 62 + 63 63 + struct bd72720_gpio { 64 64 + /* chip.parent points the MFD which provides DT node and regmap */ 65 65 + struct gpio_chip chip; 66 66 + /* dev points to the platform device for devm and prints */ 67 67 + struct device *dev; 68 68 + struct regmap *regmap; 69 69 + int gpio_is_input; 70 70 + }; 71 71 + 72 72 + static int bd72720gpi_get(struct bd72720_gpio *bdgpio, unsigned int reg_offset) 73 73 + { 74 74 + int ret, val, shift; 75 75 + 76 76 + ret = regmap_read(bdgpio->regmap, BD72720_REG_INT_ETC1_SRC, &val); 77 77 + if (ret) 78 78 + return ret; 79 79 + 80 80 + shift = BD72720_INT_GPIO1_IN_SRC + reg_offset; 81 81 + 82 82 + return (val >> shift) & 1; 83 83 + } 84 84 + 85 85 + static int bd72720gpo_get(struct bd72720_gpio *bdgpio, 86 86 + unsigned int offset) 87 87 + { 88 88 + const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL, 89 89 + BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL, 90 90 + BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL }; 91 91 + int ret, val; 92 92 + 93 93 + ret = regmap_read(bdgpio->regmap, regs[offset], &val); 94 94 + if (ret) 95 95 + return ret; 96 96 + 97 97 + return val & BD72720_GPIO_HIGH; 98 98 + } 99 99 + 100 100 + static int bd72720gpio_get(struct gpio_chip *chip, unsigned int offset) 101 101 + { 102 102 + struct bd72720_gpio *bdgpio = gpiochip_get_data(chip); 103 103 + 104 104 + if (BIT(offset) & bdgpio->gpio_is_input) 105 105 + return bd72720gpi_get(bdgpio, offset); 106 106 + 107 107 + return bd72720gpo_get(bdgpio, offset); 108 108 + } 109 109 + 110 110 + static int bd72720gpo_set(struct gpio_chip *chip, unsigned int offset, 111 111 + int value) 112 112 + { 113 113 + struct bd72720_gpio *bdgpio = gpiochip_get_data(chip); 114 114 + const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL, 115 115 + BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL, 116 116 + BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL }; 117 117 + 118 118 + if (BIT(offset) & bdgpio->gpio_is_input) { 119 119 + dev_dbg(bdgpio->dev, "pin %d not output.\n", offset); 120 120 + return -EINVAL; 121 121 + } 122 122 + 123 123 + if (value) 124 124 + return regmap_set_bits(bdgpio->regmap, regs[offset], 125 125 + BD72720_GPIO_HIGH); 126 126 + 127 127 + return regmap_clear_bits(bdgpio->regmap, regs[offset], 128 128 + BD72720_GPIO_HIGH); 129 129 + } 130 130 + 131 131 + static int bd72720_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 132 132 + unsigned long config) 133 133 + { 134 134 + struct bd72720_gpio *bdgpio = gpiochip_get_data(chip); 135 135 + const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL, 136 136 + BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL, 137 137 + BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL }; 138 138 + 139 139 + /* 140 140 + * We can only set the output mode, which makes sense only when output 141 141 + * OTP configuration is used. 142 142 + */ 143 143 + if (BIT(offset) & bdgpio->gpio_is_input) 144 144 + return -ENOTSUPP; 145 145 + 146 146 + switch (pinconf_to_config_param(config)) { 147 147 + case PIN_CONFIG_DRIVE_OPEN_DRAIN: 148 148 + return regmap_update_bits(bdgpio->regmap, 149 149 + regs[offset], 150 150 + BD72720_GPIO_DRIVE_MASK, 151 151 + BD72720_GPIO_OPEN_DRAIN); 152 152 + case PIN_CONFIG_DRIVE_PUSH_PULL: 153 153 + return regmap_update_bits(bdgpio->regmap, 154 154 + regs[offset], 155 155 + BD72720_GPIO_DRIVE_MASK, 156 156 + BD72720_GPIO_CMOS); 157 157 + default: 158 158 + break; 159 159 + } 160 160 + 161 161 + return -ENOTSUPP; 162 162 + } 163 163 + 164 164 + static int bd72720gpo_direction_get(struct gpio_chip *chip, 165 165 + unsigned int offset) 166 166 + { 167 167 + struct bd72720_gpio *bdgpio = gpiochip_get_data(chip); 168 168 + 169 169 + if (BIT(offset) & bdgpio->gpio_is_input) 170 170 + return GPIO_LINE_DIRECTION_IN; 171 171 + 172 172 + return GPIO_LINE_DIRECTION_OUT; 173 173 + } 174 174 + 175 175 + static int bd72720_valid_mask(struct gpio_chip *gc, 176 176 + unsigned long *valid_mask, 177 177 + unsigned int ngpios) 178 178 + { 179 179 + static const char * const properties[] = { 180 180 + "rohm,pin-dvs0", "rohm,pin-dvs1", "rohm,pin-exten0", 181 181 + "rohm,pin-exten1", "rohm,pin-fault_b" 182 182 + }; 183 183 + struct bd72720_gpio *g = gpiochip_get_data(gc); 184 184 + const char *val; 185 185 + int i, ret; 186 186 + 187 187 + *valid_mask = BIT(BD72720_GPIO_EPDEN); 188 188 + 189 189 + if (!gc->parent) 190 190 + return 0; 191 191 + 192 192 + for (i = 0; i < ARRAY_SIZE(properties); i++) { 193 193 + ret = fwnode_property_read_string(dev_fwnode(gc->parent), 194 194 + properties[i], &val); 195 195 + 196 196 + if (ret) { 197 197 + if (ret == -EINVAL) 198 198 + continue; 199 199 + 200 200 + dev_err(g->dev, "pin %d (%s), bad configuration\n", i, 201 201 + properties[i]); 202 202 + 203 203 + return ret; 204 204 + } 205 205 + 206 206 + if (strcmp(val, "gpi") == 0) { 207 207 + if (i != BD72720_GPIO1 && i != BD72720_GPIO2) { 208 208 + dev_warn(g->dev, 209 209 + "pin %d (%s) does not support INPUT mode", 210 210 + i, properties[i]); 211 211 + continue; 212 212 + } 213 213 + 214 214 + *valid_mask |= BIT(i); 215 215 + g->gpio_is_input |= BIT(i); 216 216 + } else if (strcmp(val, "gpo") == 0) { 217 217 + *valid_mask |= BIT(i); 218 218 + } 219 219 + } 220 220 + 221 221 + return 0; 222 222 + } 223 223 + 224 224 + /* Template for GPIO chip */ 225 225 + static const struct gpio_chip bd72720gpo_chip = { 226 226 + .label = "bd72720", 227 227 + .owner = THIS_MODULE, 228 228 + .get = bd72720gpio_get, 229 229 + .get_direction = bd72720gpo_direction_get, 230 230 + .set = bd72720gpo_set, 231 231 + .set_config = bd72720_gpio_set_config, 232 232 + .init_valid_mask = bd72720_valid_mask, 233 233 + .can_sleep = true, 234 234 + .ngpio = BD72720_NUM_GPIOS, 235 235 + .base = -1, 236 236 + }; 237 237 + 238 238 + static int gpo_bd72720_probe(struct platform_device *pdev) 239 239 + { 240 240 + struct bd72720_gpio *g; 241 241 + struct device *parent, *dev; 242 242 + 243 243 + /* 244 244 + * Bind devm lifetime to this platform device => use dev for devm. 245 245 + * also the prints should originate from this device. 246 246 + */ 247 247 + dev = &pdev->dev; 248 248 + /* The device-tree and regmap come from MFD => use parent for that */ 249 249 + parent = dev->parent; 250 250 + 251 251 + g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); 252 252 + if (!g) 253 253 + return -ENOMEM; 254 254 + 255 255 + g->chip = bd72720gpo_chip; 256 256 + g->dev = dev; 257 257 + g->chip.parent = parent; 258 258 + g->regmap = dev_get_regmap(parent, NULL); 259 259 + 260 260 + return devm_gpiochip_add_data(dev, &g->chip, g); 261 261 + } 262 262 + 263 263 + static const struct platform_device_id bd72720_gpio_id[] = { 264 264 + { "bd72720-gpio" }, 265 265 + { }, 266 266 + }; 267 267 + MODULE_DEVICE_TABLE(platform, bd72720_gpio_id); 268 268 + 269 269 + static struct platform_driver gpo_bd72720_driver = { 270 270 + .driver = { 271 271 + .name = "bd72720-gpio", 272 272 + .probe_type = PROBE_PREFER_ASYNCHRONOUS, 273 273 + }, 274 274 + .probe = gpo_bd72720_probe, 275 275 + .id_table = bd72720_gpio_id, 276 276 + }; 277 277 + module_platform_driver(gpo_bd72720_driver); 278 278 + 279 279 + MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 280 280 + MODULE_DESCRIPTION("GPIO interface for BD72720 and BD73900"); 281 281 + MODULE_LICENSE("GPL");

+61 -15

drivers/gpio/gpio-cadence.c

reviewed

··· 2 2 3 3 /* 4 4 * Copyright 2017-2018 Cadence 5 5 + * Copyright (C) 2025 Axiado Corporation. 5 6 * 6 7 * Authors: 7 8 * Jan Kotas <jank@cadence.com> ··· 32 31 #define CDNS_GPIO_IRQ_VALUE 0x28 33 32 #define CDNS_GPIO_IRQ_ANY_EDGE 0x2c 34 33 34 34 + struct cdns_gpio_quirks { 35 35 + bool skip_init; 36 36 + }; 37 37 + 35 38 struct cdns_gpio_chip { 36 39 struct gpio_generic_chip gen_gc; 37 40 void __iomem *regs; 38 41 u32 bypass_orig; 42 42 + const struct cdns_gpio_quirks *quirks; 43 43 + }; 44 44 + 45 45 + static const struct cdns_gpio_quirks cdns_default_quirks = { 46 46 + .skip_init = false, 47 47 + }; 48 48 + 49 49 + static const struct cdns_gpio_quirks ax3000_gpio_quirks = { 50 50 + .skip_init = true, 39 51 }; 40 52 41 53 static int cdns_gpio_request(struct gpio_chip *chip, unsigned int offset) ··· 98 84 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip); 99 85 u32 int_value; 100 86 u32 int_type; 87 87 + u32 int_any; 101 88 u32 mask = BIT(d->hwirq); 102 89 int ret = 0; 103 90 ··· 106 91 107 92 int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask; 108 93 int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask; 109 109 - 110 94 /* 111 111 - * The GPIO controller doesn't have an ACK register. 112 112 - * All interrupt statuses are cleared on a status register read. 113 113 - * Don't support edge interrupts for now. 95 95 + * Interrupt polarity and trigger behaviour is configured like this: 96 96 + * 97 97 + * (type, value) 98 98 + * (0, 0) = Falling edge triggered 99 99 + * (0, 1) = Rising edge triggered 100 100 + * (1, 0) = Low level triggered 101 101 + * (1, 1) = High level triggered 114 102 */ 103 103 + int_any = ioread32(cgpio->regs + CDNS_GPIO_IRQ_ANY_EDGE) & ~mask; 115 104 116 105 if (type == IRQ_TYPE_LEVEL_HIGH) { 117 106 int_type |= mask; 118 107 int_value |= mask; 119 108 } else if (type == IRQ_TYPE_LEVEL_LOW) { 120 109 int_type |= mask; 110 110 + } else if (type == IRQ_TYPE_EDGE_RISING) { 111 111 + int_value |= mask; 112 112 + } else if (type == IRQ_TYPE_EDGE_FALLING) { 113 113 + /* edge trigger, int_value remains cleared for falling */ 114 114 + } else if (type == IRQ_TYPE_EDGE_BOTH) { 115 115 + int_any |= mask; 121 116 } else { 122 117 return -EINVAL; 123 118 } 124 119 125 120 iowrite32(int_value, cgpio->regs + CDNS_GPIO_IRQ_VALUE); 126 121 iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE); 122 122 + iowrite32(int_any, cgpio->regs + CDNS_GPIO_IRQ_ANY_EDGE); 127 123 128 124 return ret; 129 125 } ··· 167 141 GPIOCHIP_IRQ_RESOURCE_HELPERS, 168 142 }; 169 143 144 144 + static const struct of_device_id cdns_of_ids[] = { 145 145 + { 146 146 + .compatible = "axiado,ax3000-gpio", 147 147 + .data = &ax3000_gpio_quirks 148 148 + }, 149 149 + { 150 150 + .compatible = "cdns,gpio-r1p02", 151 151 + .data = &cdns_default_quirks 152 152 + }, 153 153 + { /* sentinel */ }, 154 154 + }; 155 155 + MODULE_DEVICE_TABLE(of, cdns_of_ids); 156 156 + 170 157 static int cdns_gpio_probe(struct platform_device *pdev) 171 158 { 172 159 struct gpio_generic_chip_config config = { }; ··· 204 165 return -EINVAL; 205 166 } 206 167 168 168 + cgpio->quirks = device_get_match_data(&pdev->dev); 169 169 + if (!cgpio->quirks) 170 170 + cgpio->quirks = &cdns_default_quirks; 171 171 + 207 172 /* 208 173 * Set all pins as inputs by default, otherwise: 209 174 * gpiochip_lock_as_irq: ··· 216 173 * so it needs to be changed before gpio_generic_chip_init() is called. 217 174 */ 218 175 dir_prev = ioread32(cgpio->regs + CDNS_GPIO_DIRECTION_MODE); 219 219 - iowrite32(GENMASK(num_gpios - 1, 0), 220 220 - cgpio->regs + CDNS_GPIO_DIRECTION_MODE); 176 176 + 177 177 + /* 178 178 + * The AX3000 platform performs the required configuration at boot time 179 179 + * before Linux boots, so this quirk disables pinmux initialization. 180 180 + */ 181 181 + if (!cgpio->quirks->skip_init) { 182 182 + iowrite32(GENMASK(num_gpios - 1, 0), 183 183 + cgpio->regs + CDNS_GPIO_DIRECTION_MODE); 184 184 + } 221 185 222 186 config.dev = &pdev->dev; 223 187 config.sz = 4; ··· 290 240 /* 291 241 * Enable gpio outputs, ignored for input direction 292 242 */ 293 293 - iowrite32(GENMASK(num_gpios - 1, 0), 294 294 - cgpio->regs + CDNS_GPIO_OUTPUT_EN); 295 295 - iowrite32(0, cgpio->regs + CDNS_GPIO_BYPASS_MODE); 243 243 + if (!cgpio->quirks->skip_init) { 244 244 + iowrite32(GENMASK(num_gpios - 1, 0), 245 245 + cgpio->regs + CDNS_GPIO_OUTPUT_EN); 246 246 + iowrite32(0, cgpio->regs + CDNS_GPIO_BYPASS_MODE); 247 247 + } 296 248 297 249 platform_set_drvdata(pdev, cgpio); 298 250 return 0; ··· 311 259 312 260 iowrite32(cgpio->bypass_orig, cgpio->regs + CDNS_GPIO_BYPASS_MODE); 313 261 } 314 314 - 315 315 - static const struct of_device_id cdns_of_ids[] = { 316 316 - { .compatible = "cdns,gpio-r1p02" }, 317 317 - { /* sentinel */ }, 318 318 - }; 319 319 - MODULE_DEVICE_TABLE(of, cdns_of_ids); 320 262 321 263 static struct platform_driver cdns_gpio_driver = { 322 264 .driver = {

+1 -3

drivers/gpio/gpio-creg-snps.c

reviewed

··· 134 134 135 135 static int creg_gpio_probe(struct platform_device *pdev) 136 136 { 137 137 - const struct of_device_id *match; 138 137 struct device *dev = &pdev->dev; 139 138 struct creg_gpio *hcg; 140 139 u32 ngpios; ··· 147 148 if (IS_ERR(hcg->regs)) 148 149 return PTR_ERR(hcg->regs); 149 150 150 150 - match = of_match_node(creg_gpio_ids, pdev->dev.of_node); 151 151 - hcg->layout = match->data; 151 151 + hcg->layout = device_get_match_data(dev); 152 152 if (!hcg->layout) 153 153 return -EINVAL; 154 154

+116

drivers/gpio/gpio-line-mux.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * GPIO line mux which acts as virtual gpiochip and provides a 1-to-many 4 4 + * mapping between virtual GPIOs and a real GPIO + multiplexer. 5 5 + * 6 6 + * Copyright (c) 2025 Jonas Jelonek <jelonek.jonas@gmail.com> 7 7 + */ 8 8 + 9 9 + #include <linux/gpio/consumer.h> 10 10 + #include <linux/gpio/driver.h> 11 11 + #include <linux/mod_devicetable.h> 12 12 + #include <linux/mutex.h> 13 13 + #include <linux/mux/consumer.h> 14 14 + #include <linux/platform_device.h> 15 15 + 16 16 + #define MUX_SELECT_DELAY_US 100 17 17 + 18 18 + struct gpio_lmux { 19 19 + struct gpio_chip gc; 20 20 + struct mux_control *mux; 21 21 + struct gpio_desc *muxed_gpio; 22 22 + 23 23 + u32 num_gpio_mux_states; 24 24 + unsigned int gpio_mux_states[] __counted_by(num_gpio_mux_states); 25 25 + }; 26 26 + 27 27 + static int gpio_lmux_gpio_get(struct gpio_chip *gc, unsigned int offset) 28 28 + { 29 29 + struct gpio_lmux *glm = gpiochip_get_data(gc); 30 30 + int ret; 31 31 + 32 32 + ret = mux_control_select_delay(glm->mux, glm->gpio_mux_states[offset], 33 33 + MUX_SELECT_DELAY_US); 34 34 + if (ret < 0) 35 35 + return ret; 36 36 + 37 37 + ret = gpiod_get_raw_value_cansleep(glm->muxed_gpio); 38 38 + mux_control_deselect(glm->mux); 39 39 + return ret; 40 40 + } 41 41 + 42 42 + static int gpio_lmux_gpio_get_direction(struct gpio_chip *gc, 43 43 + unsigned int offset) 44 44 + { 45 45 + return GPIO_LINE_DIRECTION_IN; 46 46 + } 47 47 + 48 48 + static int gpio_lmux_probe(struct platform_device *pdev) 49 49 + { 50 50 + struct device *dev = &pdev->dev; 51 51 + struct gpio_lmux *glm; 52 52 + unsigned int ngpio; 53 53 + size_t size; 54 54 + int ret; 55 55 + 56 56 + ngpio = device_property_count_u32(dev, "gpio-line-mux-states"); 57 57 + if (!ngpio) 58 58 + return -EINVAL; 59 59 + 60 60 + size = struct_size(glm, gpio_mux_states, ngpio); 61 61 + glm = devm_kzalloc(dev, size, GFP_KERNEL); 62 62 + if (!glm) 63 63 + return -ENOMEM; 64 64 + 65 65 + glm->gc.base = -1; 66 66 + glm->gc.can_sleep = true; 67 67 + glm->gc.fwnode = dev_fwnode(dev); 68 68 + glm->gc.label = dev_name(dev); 69 69 + glm->gc.ngpio = ngpio; 70 70 + glm->gc.owner = THIS_MODULE; 71 71 + glm->gc.parent = dev; 72 72 + 73 73 + glm->gc.get = gpio_lmux_gpio_get; 74 74 + glm->gc.get_direction = gpio_lmux_gpio_get_direction; 75 75 + 76 76 + glm->mux = devm_mux_control_get(dev, NULL); 77 77 + if (IS_ERR(glm->mux)) 78 78 + return dev_err_probe(dev, PTR_ERR(glm->mux), 79 79 + "could not get mux controller\n"); 80 80 + 81 81 + glm->muxed_gpio = devm_gpiod_get(dev, "muxed", GPIOD_IN); 82 82 + if (IS_ERR(glm->muxed_gpio)) 83 83 + return dev_err_probe(dev, PTR_ERR(glm->muxed_gpio), 84 84 + "could not get muxed-gpio\n"); 85 85 + 86 86 + glm->num_gpio_mux_states = ngpio; 87 87 + ret = device_property_read_u32_array(dev, "gpio-line-mux-states", 88 88 + &glm->gpio_mux_states[0], ngpio); 89 89 + if (ret) 90 90 + return dev_err_probe(dev, ret, "could not get mux states\n"); 91 91 + 92 92 + ret = devm_gpiochip_add_data(dev, &glm->gc, glm); 93 93 + if (ret) 94 94 + return dev_err_probe(dev, ret, "failed to add gpiochip\n"); 95 95 + 96 96 + return 0; 97 97 + } 98 98 + 99 99 + static const struct of_device_id gpio_lmux_of_match[] = { 100 100 + { .compatible = "gpio-line-mux" }, 101 101 + { } 102 102 + }; 103 103 + MODULE_DEVICE_TABLE(of, gpio_lmux_of_match); 104 104 + 105 105 + static struct platform_driver gpio_lmux_driver = { 106 106 + .driver = { 107 107 + .name = "gpio-line-mux", 108 108 + .of_match_table = gpio_lmux_of_match, 109 109 + }, 110 110 + .probe = gpio_lmux_probe, 111 111 + }; 112 112 + module_platform_driver(gpio_lmux_driver); 113 113 + 114 114 + MODULE_AUTHOR("Jonas Jelonek <jelonek.jonas@gmail.com>"); 115 115 + MODULE_DESCRIPTION("GPIO line mux driver"); 116 116 + MODULE_LICENSE("GPL");

+19

drivers/gpio/gpio-max77620.c

reviewed

··· 132 132 GPIOCHIP_IRQ_RESOURCE_HELPERS, 133 133 }; 134 134 135 135 + static int max77620_gpio_get_dir(struct gpio_chip *gc, unsigned int offset) 136 136 + { 137 137 + struct max77620_gpio *mgpio = gpiochip_get_data(gc); 138 138 + unsigned int val; 139 139 + int ret; 140 140 + 141 141 + ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val); 142 142 + if (ret < 0) { 143 143 + dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret); 144 144 + return ret; 145 145 + } 146 146 + 147 147 + if (val & MAX77620_CNFG_GPIO_DIR_MASK) 148 148 + return GPIO_LINE_DIRECTION_IN; 149 149 + else 150 150 + return GPIO_LINE_DIRECTION_OUT; 151 151 + } 152 152 + 135 153 static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset) 136 154 { 137 155 struct max77620_gpio *mgpio = gpiochip_get_data(gc); ··· 326 308 327 309 mgpio->gpio_chip.label = pdev->name; 328 310 mgpio->gpio_chip.parent = pdev->dev.parent; 311 311 + mgpio->gpio_chip.get_direction = max77620_gpio_get_dir; 329 312 mgpio->gpio_chip.direction_input = max77620_gpio_dir_input; 330 313 mgpio->gpio_chip.get = max77620_gpio_get; 331 314 mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;

+2 -8

drivers/gpio/gpio-max77759.c

reviewed

··· 435 435 int irq; 436 436 struct gpio_irq_chip *girq; 437 437 int ret; 438 438 - unsigned long irq_flags; 439 439 - struct irq_data *irqd; 440 438 441 439 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 442 440 if (!chip) ··· 484 486 return dev_err_probe(&pdev->dev, ret, 485 487 "Failed to add GPIO chip\n"); 486 488 487 487 - irq_flags = IRQF_ONESHOT | IRQF_SHARED; 488 488 - irqd = irq_get_irq_data(irq); 489 489 - if (irqd) 490 490 - irq_flags |= irqd_get_trigger_type(irqd); 491 491 - 492 489 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 493 493 - max77759_gpio_irqhandler, irq_flags, 490 490 + max77759_gpio_irqhandler, 491 491 + IRQF_ONESHOT | IRQF_SHARED, 494 492 dev_name(&pdev->dev), chip); 495 493 if (ret < 0) 496 494 return dev_err_probe(&pdev->dev, ret,

-1

drivers/gpio/gpio-menz127.c

reviewed

··· 223 223 MODULE_AUTHOR("Andreas Werner <andreas.werner@men.de>"); 224 224 MODULE_DESCRIPTION("MEN GPIO Controller"); 225 225 MODULE_LICENSE("GPL v2"); 226 226 - MODULE_ALIAS("mcb:16z127"); 227 226 MODULE_IMPORT_NS("MCB");

+1

drivers/gpio/gpio-mmio.c

reviewed

··· 724 724 { .compatible = "wd,mbl-gpio" }, 725 725 { .compatible = "ni,169445-nand-gpio" }, 726 726 { .compatible = "intel,ixp4xx-expansion-bus-mmio-gpio" }, 727 727 + { .compatible = "opencores,gpio" }, 727 728 { } 728 729 }; 729 730 MODULE_DEVICE_TABLE(of, gpio_mmio_of_match);

+6

drivers/gpio/gpio-pca953x.c

reviewed

··· 126 126 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 127 127 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 128 128 { "xra1202", 8 | PCA953X_TYPE }, 129 129 + 130 130 + { "tcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 131 131 + { "tcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 129 132 { } 130 133 }; 131 134 MODULE_DEVICE_TABLE(i2c, pca953x_id); ··· 1471 1468 { .compatible = "ti,tca9535", .data = OF_953X(16, PCA_INT), }, 1472 1469 { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), }, 1473 1470 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1471 1471 + 1472 1472 + { .compatible = "ti,tcal6408", .data = OF_953X( 8, PCA_LATCH_INT), }, 1473 1473 + { .compatible = "ti,tcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1474 1474 1475 1475 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1476 1476 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },

+13 -6

drivers/gpio/gpio-pca9570.c

reviewed

··· 9 9 * Andrew F. Davis <afd@ti.com> 10 10 */ 11 11 12 12 + #include <linux/bits.h> 13 13 + #include <linux/cleanup.h> 14 14 + #include <linux/device/devres.h> 15 15 + #include <linux/errno.h> 12 16 #include <linux/gpio/driver.h> 13 17 #include <linux/i2c.h> 14 18 #include <linux/module.h> 15 19 #include <linux/mutex.h> 16 20 #include <linux/property.h> 21 21 + #include <linux/types.h> 17 22 18 23 #define SLG7XL45106_GPO_REG 0xDB 19 24 ··· 99 94 u8 buffer; 100 95 int ret; 101 96 102 102 - mutex_lock(&gpio->lock); 97 97 + guard(mutex)(&gpio->lock); 103 98 104 99 buffer = gpio->out; 105 100 if (value) ··· 109 104 110 105 ret = pca9570_write(gpio, buffer); 111 106 if (ret) 112 112 - goto out; 107 107 + return ret; 113 108 114 109 gpio->out = buffer; 115 110 116 116 - out: 117 117 - mutex_unlock(&gpio->lock); 118 118 - return ret; 111 111 + return 0; 119 112 } 120 113 121 114 static int pca9570_probe(struct i2c_client *client) 122 115 { 116 116 + struct device *dev = &client->dev; 123 117 struct pca9570 *gpio; 118 118 + int ret; 124 119 125 120 gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL); 126 121 if (!gpio) ··· 137 132 gpio->chip.ngpio = gpio->chip_data->ngpio; 138 133 gpio->chip.can_sleep = true; 139 134 140 140 - mutex_init(&gpio->lock); 135 135 + ret = devm_mutex_init(dev, &gpio->lock); 136 136 + if (ret) 137 137 + return ret; 141 138 142 139 /* Read the current output level */ 143 140 pca9570_read(gpio, &gpio->out);

+2 -3

drivers/gpio/gpio-realtek-otto.c

reviewed

··· 359 359 { 360 360 struct gpio_generic_chip_config config; 361 361 struct device *dev = &pdev->dev; 362 362 - unsigned long gen_gc_flags; 363 363 - unsigned int dev_flags; 362 362 + unsigned long gen_gc_flags, dev_flags; 364 363 struct gpio_irq_chip *girq; 365 364 struct realtek_gpio_ctrl *ctrl; 366 365 struct resource *res; ··· 371 372 if (!ctrl) 372 373 return -ENOMEM; 373 374 374 374 - dev_flags = (unsigned int) device_get_match_data(dev); 375 375 + dev_flags = (uintptr_t)device_get_match_data(dev); 375 376 376 377 ngpios = REALTEK_GPIO_MAX; 377 378 device_property_read_u32(dev, "ngpios", &ngpios);

+8 -8

drivers/gpio/gpio-sim.c

reviewed

··· 1384 1384 kfree(hog); 1385 1385 } 1386 1386 1387 1387 - static struct configfs_item_operations gpio_sim_hog_config_item_ops = { 1387 1387 + static const struct configfs_item_operations gpio_sim_hog_config_item_ops = { 1388 1388 .release = gpio_sim_hog_config_item_release, 1389 1389 }; 1390 1390 ··· 1433 1433 kfree(line); 1434 1434 } 1435 1435 1436 1436 - static struct configfs_item_operations gpio_sim_line_config_item_ops = { 1436 1436 + static const struct configfs_item_operations gpio_sim_line_config_item_ops = { 1437 1437 .release = gpio_sim_line_config_group_release, 1438 1438 }; 1439 1439 1440 1440 - static struct configfs_group_operations gpio_sim_line_config_group_ops = { 1440 1440 + static const struct configfs_group_operations gpio_sim_line_config_group_ops = { 1441 1441 .make_item = gpio_sim_line_config_make_hog_item, 1442 1442 }; 1443 1443 ··· 1494 1494 kfree(bank); 1495 1495 } 1496 1496 1497 1497 - static struct configfs_item_operations gpio_sim_bank_config_item_ops = { 1497 1497 + static const struct configfs_item_operations gpio_sim_bank_config_item_ops = { 1498 1498 .release = gpio_sim_bank_config_group_release, 1499 1499 }; 1500 1500 1501 1501 - static struct configfs_group_operations gpio_sim_bank_config_group_ops = { 1501 1501 + static const struct configfs_group_operations gpio_sim_bank_config_group_ops = { 1502 1502 .make_group = gpio_sim_bank_config_make_line_group, 1503 1503 }; 1504 1504 ··· 1549 1549 kfree(dev); 1550 1550 } 1551 1551 1552 1552 - static struct configfs_item_operations gpio_sim_device_config_item_ops = { 1552 1552 + static const struct configfs_item_operations gpio_sim_device_config_item_ops = { 1553 1553 .release = gpio_sim_device_config_group_release, 1554 1554 }; 1555 1555 1556 1556 - static struct configfs_group_operations gpio_sim_device_config_group_ops = { 1556 1556 + static const struct configfs_group_operations gpio_sim_device_config_group_ops = { 1557 1557 .make_group = gpio_sim_device_config_make_bank_group, 1558 1558 }; 1559 1559 ··· 1589 1589 return &no_free_ptr(dev)->group; 1590 1590 } 1591 1591 1592 1592 - static struct configfs_group_operations gpio_sim_config_group_ops = { 1592 1592 + static const struct configfs_group_operations gpio_sim_config_group_ops = { 1593 1593 .make_group = gpio_sim_config_make_device_group, 1594 1594 }; 1595 1595

+118 -50

drivers/gpio/gpio-spacemit-k1.c

reviewed

··· 15 15 #include <linux/platform_device.h> 16 16 #include <linux/seq_file.h> 17 17 18 18 - /* register offset */ 19 19 - #define SPACEMIT_GPLR 0x00 /* port level - R */ 20 20 - #define SPACEMIT_GPDR 0x0c /* port direction - R/W */ 21 21 - #define SPACEMIT_GPSR 0x18 /* port set - W */ 22 22 - #define SPACEMIT_GPCR 0x24 /* port clear - W */ 23 23 - #define SPACEMIT_GRER 0x30 /* port rising edge R/W */ 24 24 - #define SPACEMIT_GFER 0x3c /* port falling edge R/W */ 25 25 - #define SPACEMIT_GEDR 0x48 /* edge detect status - R/W1C */ 26 26 - #define SPACEMIT_GSDR 0x54 /* (set) direction - W */ 27 27 - #define SPACEMIT_GCDR 0x60 /* (clear) direction - W */ 28 28 - #define SPACEMIT_GSRER 0x6c /* (set) rising edge detect enable - W */ 29 29 - #define SPACEMIT_GCRER 0x78 /* (clear) rising edge detect enable - W */ 30 30 - #define SPACEMIT_GSFER 0x84 /* (set) falling edge detect enable - W */ 31 31 - #define SPACEMIT_GCFER 0x90 /* (clear) falling edge detect enable - W */ 32 32 - #define SPACEMIT_GAPMASK 0x9c /* interrupt mask , 0 disable, 1 enable - R/W */ 33 33 - 34 18 #define SPACEMIT_NR_BANKS 4 35 19 #define SPACEMIT_NR_GPIOS_PER_BANK 32 36 20 37 21 #define to_spacemit_gpio_bank(x) container_of((x), struct spacemit_gpio_bank, gc) 22 22 + #define to_spacemit_gpio_regs(gb) ((gb)->sg->data->offsets) 23 23 + 24 24 + enum spacemit_gpio_registers { 25 25 + SPACEMIT_GPLR, /* port level - R */ 26 26 + SPACEMIT_GPDR, /* port direction - R/W */ 27 27 + SPACEMIT_GPSR, /* port set - W */ 28 28 + SPACEMIT_GPCR, /* port clear - W */ 29 29 + SPACEMIT_GRER, /* port rising edge R/W */ 30 30 + SPACEMIT_GFER, /* port falling edge R/W */ 31 31 + SPACEMIT_GEDR, /* edge detect status - R/W1C */ 32 32 + SPACEMIT_GSDR, /* (set) direction - W */ 33 33 + SPACEMIT_GCDR, /* (clear) direction - W */ 34 34 + SPACEMIT_GSRER, /* (set) rising edge detect enable - W */ 35 35 + SPACEMIT_GCRER, /* (clear) rising edge detect enable - W */ 36 36 + SPACEMIT_GSFER, /* (set) falling edge detect enable - W */ 37 37 + SPACEMIT_GCFER, /* (clear) falling edge detect enable - W */ 38 38 + SPACEMIT_GAPMASK, /* interrupt mask , 0 disable, 1 enable - R/W */ 39 39 + SPACEMIT_GCPMASK, /* interrupt mask for K3 */ 40 40 + }; 38 41 39 42 struct spacemit_gpio; 43 43 + 44 44 + struct spacemit_gpio_data { 45 45 + const unsigned int *offsets; 46 46 + u32 bank_offsets[SPACEMIT_NR_BANKS]; 47 47 + }; 40 48 41 49 struct spacemit_gpio_bank { 42 50 struct gpio_generic_chip chip; ··· 57 49 58 50 struct spacemit_gpio { 59 51 struct device *dev; 52 52 + const struct spacemit_gpio_data *data; 60 53 struct spacemit_gpio_bank sgb[SPACEMIT_NR_BANKS]; 61 54 }; 55 55 + 56 56 + static u32 spacemit_gpio_read(struct spacemit_gpio_bank *gb, 57 57 + enum spacemit_gpio_registers reg) 58 58 + { 59 59 + return readl(gb->base + to_spacemit_gpio_regs(gb)[reg]); 60 60 + } 61 61 + 62 62 + static void spacemit_gpio_write(struct spacemit_gpio_bank *gb, 63 63 + enum spacemit_gpio_registers reg, u32 val) 64 64 + { 65 65 + writel(val, gb->base + to_spacemit_gpio_regs(gb)[reg]); 66 66 + } 62 67 63 68 static u32 spacemit_gpio_bank_index(struct spacemit_gpio_bank *gb) 64 69 { ··· 84 63 unsigned long pending; 85 64 u32 n, gedr; 86 65 87 87 - gedr = readl(gb->base + SPACEMIT_GEDR); 66 66 + gedr = spacemit_gpio_read(gb, SPACEMIT_GEDR); 88 67 if (!gedr) 89 68 return IRQ_NONE; 90 90 - writel(gedr, gb->base + SPACEMIT_GEDR); 69 69 + spacemit_gpio_write(gb, SPACEMIT_GEDR, gedr); 91 70 92 71 pending = gedr & gb->irq_mask; 93 72 if (!pending) ··· 103 82 { 104 83 struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d); 105 84 106 106 - writel(BIT(irqd_to_hwirq(d)), gb->base + SPACEMIT_GEDR); 85 85 + spacemit_gpio_write(gb, SPACEMIT_GEDR, BIT(irqd_to_hwirq(d))); 107 86 } 108 87 109 88 static void spacemit_gpio_irq_mask(struct irq_data *d) ··· 112 91 u32 bit = BIT(irqd_to_hwirq(d)); 113 92 114 93 gb->irq_mask &= ~bit; 115 115 - writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); 94 94 + spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask); 116 95 117 96 if (bit & gb->irq_rising_edge) 118 118 - writel(bit, gb->base + SPACEMIT_GCRER); 97 97 + spacemit_gpio_write(gb, SPACEMIT_GCRER, bit); 119 98 120 99 if (bit & gb->irq_falling_edge) 121 121 - writel(bit, gb->base + SPACEMIT_GCFER); 100 100 + spacemit_gpio_write(gb, SPACEMIT_GCFER, bit); 122 101 } 123 102 124 103 static void spacemit_gpio_irq_unmask(struct irq_data *d) ··· 129 108 gb->irq_mask |= bit; 130 109 131 110 if (bit & gb->irq_rising_edge) 132 132 - writel(bit, gb->base + SPACEMIT_GSRER); 111 111 + spacemit_gpio_write(gb, SPACEMIT_GSRER, bit); 133 112 134 113 if (bit & gb->irq_falling_edge) 135 135 - writel(bit, gb->base + SPACEMIT_GSFER); 114 114 + spacemit_gpio_write(gb, SPACEMIT_GSFER, bit); 136 115 137 137 - writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); 116 116 + spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask); 138 117 } 139 118 140 119 static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type) ··· 144 123 145 124 if (type & IRQ_TYPE_EDGE_RISING) { 146 125 gb->irq_rising_edge |= bit; 147 147 - writel(bit, gb->base + SPACEMIT_GSRER); 126 126 + spacemit_gpio_write(gb, SPACEMIT_GSRER, bit); 148 127 } else { 149 128 gb->irq_rising_edge &= ~bit; 150 150 - writel(bit, gb->base + SPACEMIT_GCRER); 129 129 + spacemit_gpio_write(gb, SPACEMIT_GCRER, bit); 151 130 } 152 131 153 132 if (type & IRQ_TYPE_EDGE_FALLING) { 154 133 gb->irq_falling_edge |= bit; 155 155 - writel(bit, gb->base + SPACEMIT_GSFER); 134 134 + spacemit_gpio_write(gb, SPACEMIT_GSFER, bit); 156 135 } else { 157 136 gb->irq_falling_edge &= ~bit; 158 158 - writel(bit, gb->base + SPACEMIT_GCFER); 137 137 + spacemit_gpio_write(gb, SPACEMIT_GCFER, bit); 159 138 } 160 139 161 140 return 0; ··· 199 178 struct gpio_chip *gc = &gb->chip.gc; 200 179 struct device *dev = sg->dev; 201 180 struct gpio_irq_chip *girq; 202 202 - void __iomem *dat, *set, *clr, *dirin, *dirout; 203 203 - int ret, bank_base[] = { 0x0, 0x4, 0x8, 0x100 }; 181 181 + void __iomem *dat, *set, *clr, *dirout; 182 182 + int ret; 204 183 205 205 - gb->base = regs + bank_base[index]; 184 184 + gb->base = regs + sg->data->bank_offsets[index]; 185 185 + gb->sg = sg; 206 186 207 207 - dat = gb->base + SPACEMIT_GPLR; 208 208 - set = gb->base + SPACEMIT_GPSR; 209 209 - clr = gb->base + SPACEMIT_GPCR; 210 210 - dirin = gb->base + SPACEMIT_GCDR; 211 211 - dirout = gb->base + SPACEMIT_GSDR; 187 187 + dat = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPLR]; 188 188 + set = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPSR]; 189 189 + clr = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPCR]; 190 190 + dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPDR]; 212 191 213 192 config = (struct gpio_generic_chip_config) { 214 193 .dev = dev, ··· 217 196 .set = set, 218 197 .clr = clr, 219 198 .dirout = dirout, 220 220 - .dirin = dirin, 221 221 - .flags = GPIO_GENERIC_UNREADABLE_REG_SET | 222 222 - GPIO_GENERIC_UNREADABLE_REG_DIR, 199 199 + .flags = GPIO_GENERIC_UNREADABLE_REG_SET, 223 200 }; 224 201 225 202 /* This registers 32 GPIO lines per bank */ 226 203 ret = gpio_generic_chip_init(&gb->chip, &config); 227 204 if (ret) 228 205 return dev_err_probe(dev, ret, "failed to init gpio chip\n"); 229 229 - 230 230 - gb->sg = sg; 231 206 232 207 gc->label = dev_name(dev); 233 208 gc->request = gpiochip_generic_request; ··· 240 223 gpio_irq_chip_set_chip(girq, &spacemit_gpio_chip); 241 224 242 225 /* Disable Interrupt */ 243 243 - writel(0, gb->base + SPACEMIT_GAPMASK); 226 226 + spacemit_gpio_write(gb, SPACEMIT_GAPMASK, 0); 244 227 /* Disable Edge Detection Settings */ 245 245 - writel(0x0, gb->base + SPACEMIT_GRER); 246 246 - writel(0x0, gb->base + SPACEMIT_GFER); 228 228 + spacemit_gpio_write(gb, SPACEMIT_GRER, 0x0); 229 229 + spacemit_gpio_write(gb, SPACEMIT_GFER, 0x0); 247 230 /* Clear Interrupt */ 248 248 - writel(0xffffffff, gb->base + SPACEMIT_GCRER); 249 249 - writel(0xffffffff, gb->base + SPACEMIT_GCFER); 231 231 + spacemit_gpio_write(gb, SPACEMIT_GCRER, 0xffffffff); 232 232 + spacemit_gpio_write(gb, SPACEMIT_GCFER, 0xffffffff); 250 233 251 234 ret = devm_request_threaded_irq(dev, irq, NULL, 252 235 spacemit_gpio_irq_handler, ··· 277 260 if (!sg) 278 261 return -ENOMEM; 279 262 263 263 + sg->data = of_device_get_match_data(dev); 264 264 + if (!sg->data) 265 265 + return dev_err_probe(dev, -EINVAL, "No available compatible data."); 266 266 + 280 267 regs = devm_platform_ioremap_resource(pdev, 0); 281 268 if (IS_ERR(regs)) 282 269 return PTR_ERR(regs); ··· 308 287 return 0; 309 288 } 310 289 290 290 + static const unsigned int spacemit_gpio_k1_offsets[] = { 291 291 + [SPACEMIT_GPLR] = 0x00, 292 292 + [SPACEMIT_GPDR] = 0x0c, 293 293 + [SPACEMIT_GPSR] = 0x18, 294 294 + [SPACEMIT_GPCR] = 0x24, 295 295 + [SPACEMIT_GRER] = 0x30, 296 296 + [SPACEMIT_GFER] = 0x3c, 297 297 + [SPACEMIT_GEDR] = 0x48, 298 298 + [SPACEMIT_GSDR] = 0x54, 299 299 + [SPACEMIT_GCDR] = 0x60, 300 300 + [SPACEMIT_GSRER] = 0x6c, 301 301 + [SPACEMIT_GCRER] = 0x78, 302 302 + [SPACEMIT_GSFER] = 0x84, 303 303 + [SPACEMIT_GCFER] = 0x90, 304 304 + [SPACEMIT_GAPMASK] = 0x9c, 305 305 + [SPACEMIT_GCPMASK] = 0xA8, 306 306 + }; 307 307 + 308 308 + static const unsigned int spacemit_gpio_k3_offsets[] = { 309 309 + [SPACEMIT_GPLR] = 0x0, 310 310 + [SPACEMIT_GPDR] = 0x4, 311 311 + [SPACEMIT_GPSR] = 0x8, 312 312 + [SPACEMIT_GPCR] = 0xc, 313 313 + [SPACEMIT_GRER] = 0x10, 314 314 + [SPACEMIT_GFER] = 0x14, 315 315 + [SPACEMIT_GEDR] = 0x18, 316 316 + [SPACEMIT_GSDR] = 0x1c, 317 317 + [SPACEMIT_GCDR] = 0x20, 318 318 + [SPACEMIT_GSRER] = 0x24, 319 319 + [SPACEMIT_GCRER] = 0x28, 320 320 + [SPACEMIT_GSFER] = 0x2c, 321 321 + [SPACEMIT_GCFER] = 0x30, 322 322 + [SPACEMIT_GAPMASK] = 0x34, 323 323 + [SPACEMIT_GCPMASK] = 0x38, 324 324 + }; 325 325 + 326 326 + static const struct spacemit_gpio_data k1_gpio_data = { 327 327 + .offsets = spacemit_gpio_k1_offsets, 328 328 + .bank_offsets = { 0x0, 0x4, 0x8, 0x100 }, 329 329 + }; 330 330 + 331 331 + static const struct spacemit_gpio_data k3_gpio_data = { 332 332 + .offsets = spacemit_gpio_k3_offsets, 333 333 + .bank_offsets = { 0x0, 0x40, 0x80, 0x100 }, 334 334 + }; 335 335 + 311 336 static const struct of_device_id spacemit_gpio_dt_ids[] = { 312 312 - { .compatible = "spacemit,k1-gpio" }, 337 337 + { .compatible = "spacemit,k1-gpio", .data = &k1_gpio_data }, 338 338 + { .compatible = "spacemit,k3-gpio", .data = &k3_gpio_data }, 313 339 { /* sentinel */ } 314 340 }; 315 341 MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids); ··· 364 296 static struct platform_driver spacemit_gpio_driver = { 365 297 .probe = spacemit_gpio_probe, 366 298 .driver = { 367 367 - .name = "k1-gpio", 299 299 + .name = "spacemit-gpio", 368 300 .of_match_table = spacemit_gpio_dt_ids, 369 301 }, 370 302 }; 371 303 module_platform_driver(spacemit_gpio_driver); 372 304 373 305 MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>"); 374 374 - MODULE_DESCRIPTION("GPIO driver for SpacemiT K1 SoC"); 306 306 + MODULE_DESCRIPTION("GPIO driver for SpacemiT K1/K3 SoC"); 375 307 MODULE_LICENSE("GPL");

+88 -2

drivers/gpio/gpio-tegra186.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 3 - * Copyright (c) 2016-2025 NVIDIA Corporation 3 3 + * Copyright (c) 2016-2026 NVIDIA Corporation 4 4 * 5 5 * Author: Thierry Reding <treding@nvidia.com> 6 6 * Dipen Patel <dpatel@nvidia.com> ··· 21 21 #include <dt-bindings/gpio/tegra234-gpio.h> 22 22 #include <dt-bindings/gpio/tegra241-gpio.h> 23 23 #include <dt-bindings/gpio/tegra256-gpio.h> 24 24 + #include <dt-bindings/gpio/nvidia,tegra264-gpio.h> 24 25 25 26 /* security registers */ 26 27 #define TEGRA186_GPIO_CTL_SCR 0x0c ··· 1002 1001 if (gpio->soc->num_irqs_per_bank > 1) 1003 1002 tegra186_gpio_init_route_mapping(gpio); 1004 1003 1005 1005 - np = of_find_matching_node(NULL, tegra186_pmc_of_match); 1004 1004 + np = of_parse_phandle(pdev->dev.of_node, "wakeup-parent", 0); 1005 1005 + if (!np) 1006 1006 + np = of_find_matching_node(NULL, tegra186_pmc_of_match); 1006 1007 if (np) { 1007 1008 if (of_device_is_available(np)) { 1008 1009 irq->parent_domain = irq_find_host(np); ··· 1280 1277 .has_vm_support = false, 1281 1278 }; 1282 1279 1280 1280 + #define TEGRA264_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1281 1281 + TEGRA_GPIO_PORT(TEGRA264_MAIN, _name, _bank, _port, _pins) 1282 1282 + 1283 1283 + static const struct tegra_gpio_port tegra264_main_ports[] = { 1284 1284 + TEGRA264_MAIN_GPIO_PORT(F, 3, 0, 8), 1285 1285 + TEGRA264_MAIN_GPIO_PORT(G, 3, 1, 5), 1286 1286 + TEGRA264_MAIN_GPIO_PORT(H, 1, 0, 8), 1287 1287 + TEGRA264_MAIN_GPIO_PORT(J, 1, 1, 8), 1288 1288 + TEGRA264_MAIN_GPIO_PORT(K, 1, 2, 8), 1289 1289 + TEGRA264_MAIN_GPIO_PORT(L, 1, 3, 8), 1290 1290 + TEGRA264_MAIN_GPIO_PORT(M, 1, 4, 6), 1291 1291 + TEGRA264_MAIN_GPIO_PORT(P, 2, 0, 8), 1292 1292 + TEGRA264_MAIN_GPIO_PORT(Q, 2, 1, 8), 1293 1293 + TEGRA264_MAIN_GPIO_PORT(R, 2, 2, 8), 1294 1294 + TEGRA264_MAIN_GPIO_PORT(S, 2, 3, 2), 1295 1295 + TEGRA264_MAIN_GPIO_PORT(T, 0, 0, 7), 1296 1296 + TEGRA264_MAIN_GPIO_PORT(U, 0, 1, 8), 1297 1297 + TEGRA264_MAIN_GPIO_PORT(V, 0, 2, 8), 1298 1298 + TEGRA264_MAIN_GPIO_PORT(W, 0, 3, 8), 1299 1299 + TEGRA264_MAIN_GPIO_PORT(X, 0, 7, 6), 1300 1300 + TEGRA264_MAIN_GPIO_PORT(Y, 0, 5, 8), 1301 1301 + TEGRA264_MAIN_GPIO_PORT(Z, 0, 6, 8), 1302 1302 + TEGRA264_MAIN_GPIO_PORT(AL, 0, 4, 3), 1303 1303 + }; 1304 1304 + 1305 1305 + static const struct tegra_gpio_soc tegra264_main_soc = { 1306 1306 + .num_ports = ARRAY_SIZE(tegra264_main_ports), 1307 1307 + .ports = tegra264_main_ports, 1308 1308 + .name = "tegra264-gpio", 1309 1309 + .instance = 0, 1310 1310 + .num_irqs_per_bank = 8, 1311 1311 + .has_vm_support = true, 1312 1312 + }; 1313 1313 + 1314 1314 + #define TEGRA264_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1315 1315 + TEGRA_GPIO_PORT(TEGRA264_AON, _name, _bank, _port, _pins) 1316 1316 + 1317 1317 + static const struct tegra_gpio_port tegra264_aon_ports[] = { 1318 1318 + TEGRA264_AON_GPIO_PORT(AA, 0, 0, 8), 1319 1319 + TEGRA264_AON_GPIO_PORT(BB, 0, 1, 2), 1320 1320 + TEGRA264_AON_GPIO_PORT(CC, 0, 2, 8), 1321 1321 + TEGRA264_AON_GPIO_PORT(DD, 0, 3, 8), 1322 1322 + TEGRA264_AON_GPIO_PORT(EE, 0, 4, 4) 1323 1323 + }; 1324 1324 + 1325 1325 + static const struct tegra_gpio_soc tegra264_aon_soc = { 1326 1326 + .num_ports = ARRAY_SIZE(tegra264_aon_ports), 1327 1327 + .ports = tegra264_aon_ports, 1328 1328 + .name = "tegra264-gpio-aon", 1329 1329 + .instance = 1, 1330 1330 + .num_irqs_per_bank = 8, 1331 1331 + .has_vm_support = true, 1332 1332 + }; 1333 1333 + 1334 1334 + #define TEGRA264_UPHY_GPIO_PORT(_name, _bank, _port, _pins) \ 1335 1335 + TEGRA_GPIO_PORT(TEGRA264_UPHY, _name, _bank, _port, _pins) 1336 1336 + 1337 1337 + static const struct tegra_gpio_port tegra264_uphy_ports[] = { 1338 1338 + TEGRA264_UPHY_GPIO_PORT(A, 0, 0, 6), 1339 1339 + TEGRA264_UPHY_GPIO_PORT(B, 0, 1, 8), 1340 1340 + TEGRA264_UPHY_GPIO_PORT(C, 0, 2, 3), 1341 1341 + TEGRA264_UPHY_GPIO_PORT(D, 1, 0, 8), 1342 1342 + TEGRA264_UPHY_GPIO_PORT(E, 1, 1, 4), 1343 1343 + }; 1344 1344 + 1345 1345 + static const struct tegra_gpio_soc tegra264_uphy_soc = { 1346 1346 + .num_ports = ARRAY_SIZE(tegra264_uphy_ports), 1347 1347 + .ports = tegra264_uphy_ports, 1348 1348 + .name = "tegra264-gpio-uphy", 1349 1349 + .instance = 2, 1350 1350 + .num_irqs_per_bank = 8, 1351 1351 + .has_vm_support = true, 1352 1352 + }; 1353 1353 + 1283 1354 #define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1284 1355 TEGRA_GPIO_PORT(TEGRA256_MAIN, _name, _bank, _port, _pins) 1285 1356 ··· 1445 1368 }, { 1446 1369 .compatible = "nvidia,tegra256-gpio", 1447 1370 .data = &tegra256_main_soc 1371 1371 + }, { 1372 1372 + .compatible = "nvidia,tegra264-gpio", 1373 1373 + .data = &tegra264_main_soc 1374 1374 + }, { 1375 1375 + .compatible = "nvidia,tegra264-gpio-aon", 1376 1376 + .data = &tegra264_aon_soc 1377 1377 + }, { 1378 1378 + .compatible = "nvidia,tegra264-gpio-uphy", 1379 1379 + .data = &tegra264_uphy_soc 1448 1380 }, { 1449 1381 /* sentinel */ 1450 1382 }

+4 -4

drivers/gpio/gpio-virtuser.c

reviewed

··· 1631 1631 kfree(lookup); 1632 1632 } 1633 1633 1634 1634 - static struct configfs_item_operations gpio_virtuser_lookup_config_item_ops = { 1634 1634 + static const struct configfs_item_operations gpio_virtuser_lookup_config_item_ops = { 1635 1635 .release = gpio_virtuser_lookup_config_group_release, 1636 1636 }; 1637 1637 ··· 1692 1692 kfree(dev); 1693 1693 } 1694 1694 1695 1695 - static struct configfs_item_operations gpio_virtuser_device_config_item_ops = { 1695 1695 + static const struct configfs_item_operations gpio_virtuser_device_config_item_ops = { 1696 1696 .release = gpio_virtuser_device_config_group_release, 1697 1697 }; 1698 1698 1699 1699 - static struct configfs_group_operations gpio_virtuser_device_config_group_ops = { 1699 1699 + static const struct configfs_group_operations gpio_virtuser_device_config_group_ops = { 1700 1700 .make_group = gpio_virtuser_make_lookup_group, 1701 1701 }; 1702 1702 ··· 1729 1729 return &no_free_ptr(dev)->group; 1730 1730 } 1731 1731 1732 1732 - static struct configfs_group_operations gpio_virtuser_config_group_ops = { 1732 1732 + static const struct configfs_group_operations gpio_virtuser_config_group_ops = { 1733 1733 .make_group = gpio_virtuser_config_make_device_group, 1734 1734 }; 1735 1735

+5 -7

drivers/gpio/gpio-zynq.c

reviewed

··· 903 903 struct zynq_gpio *gpio; 904 904 struct gpio_chip *chip; 905 905 struct gpio_irq_chip *girq; 906 906 - const struct of_device_id *match; 907 906 908 907 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 909 908 if (!gpio) 910 909 return -ENOMEM; 911 910 912 912 - match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); 913 913 - if (!match) { 914 914 - dev_err(&pdev->dev, "of_match_node() failed\n"); 915 915 - return -EINVAL; 916 916 - } 917 917 - gpio->p_data = match->data; 911 911 + gpio->p_data = device_get_match_data(&pdev->dev); 912 912 + if (!gpio->p_data) 913 913 + return dev_err_probe(&pdev->dev, -EINVAL, 914 914 + "device_get_match_data() failed\n"); 915 915 + 918 916 platform_set_drvdata(pdev, gpio); 919 917 920 918 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);

+4

drivers/gpio/gpiolib-of.c

reviewed

··· 634 634 return ERR_PTR(-ENOENT); 635 635 } 636 636 637 637 + #if IS_ENABLED(CONFIG_SND_SOC_MT2701_CS42448) 637 638 static struct gpio_desc *of_find_mt2701_gpio(struct device_node *np, 638 639 const char *con_id, 639 640 unsigned int idx, ··· 666 665 667 666 return desc; 668 667 } 668 668 + #endif 669 669 670 670 /* 671 671 * Trigger sources are special, they allow us to use any GPIO as a LED trigger ··· 701 699 enum of_gpio_flags *of_flags); 702 700 static const of_find_gpio_quirk of_find_gpio_quirks[] = { 703 701 of_find_gpio_rename, 702 702 + #if IS_ENABLED(CONFIG_SND_SOC_MT2701_CS42448) 704 703 of_find_mt2701_gpio, 704 704 + #endif 705 705 of_find_trigger_gpio, 706 706 NULL 707 707 };

+1 -6

drivers/gpio/gpiolib-shared.c

reviewed

··· 455 455 list_for_each_entry(ref, &entry->refs, list) { 456 456 guard(mutex)(&ref->lock); 457 457 458 458 - /* 459 459 - * FIXME: use device_is_compatible() once the reset-gpio 460 460 - * drivers gains a compatible string which it currently 461 461 - * does not have. 462 462 - */ 463 463 - if (!ref->fwnode && strstarts(dev_name(consumer), "reset.gpio.")) { 458 458 + if (!ref->fwnode && device_is_compatible(consumer, "reset-gpio")) { 464 459 if (!gpio_shared_dev_is_reset_gpio(consumer, entry, ref)) 465 460 continue; 466 461 } else if (!device_match_fwnode(consumer, ref->fwnode)) {

+4 -5

drivers/gpio/gpiolib-swnode.c

reviewed

··· 18 18 19 19 #include <linux/gpio/consumer.h> 20 20 #include <linux/gpio/driver.h> 21 21 + #include <linux/gpio/property.h> 21 22 22 23 #include "gpiolib.h" 23 24 #include "gpiolib-swnode.h" 24 24 - 25 25 - #define GPIOLIB_SWNODE_UNDEFINED_NAME "swnode-gpio-undefined" 26 25 27 26 static struct gpio_device *swnode_get_gpio_device(struct fwnode_handle *fwnode) 28 27 { ··· 29 30 struct gpio_device *gdev; 30 31 31 32 gdev_node = to_software_node(fwnode); 32 32 - if (!gdev_node || !gdev_node->name) 33 33 + if (!gdev_node) 33 34 goto fwnode_lookup; 34 35 35 36 /* ··· 37 38 * primarily used as a key for internal chip selects in SPI bindings. 38 39 */ 39 40 if (IS_ENABLED(CONFIG_GPIO_SWNODE_UNDEFINED) && 40 40 - !strcmp(gdev_node->name, GPIOLIB_SWNODE_UNDEFINED_NAME)) 41 41 + gdev_node == &swnode_gpio_undefined) 41 42 return ERR_PTR(-ENOENT); 42 43 43 44 fwnode_lookup: ··· 139 140 * a key for internal chip selects in SPI bindings. 140 141 */ 141 142 const struct software_node swnode_gpio_undefined = { 142 142 - .name = GPIOLIB_SWNODE_UNDEFINED_NAME, 143 143 + .name = "swnode-gpio-undefined", 143 144 }; 144 145 EXPORT_SYMBOL_NS_GPL(swnode_gpio_undefined, "GPIO_SWNODE"); 145 146

+12 -18

drivers/gpio/gpiolib.c

reviewed

··· 5261 5261 } 5262 5262 EXPORT_SYMBOL_GPL(gpiod_put_array); 5263 5263 5264 5264 - static int gpio_stub_drv_probe(struct device *dev) 5265 5265 - { 5266 5266 - /* 5267 5267 - * The DT node of some GPIO chips have a "compatible" property, but 5268 5268 - * never have a struct device added and probed by a driver to register 5269 5269 - * the GPIO chip with gpiolib. In such cases, fw_devlink=on will cause 5270 5270 - * the consumers of the GPIO chip to get probe deferred forever because 5271 5271 - * they will be waiting for a device associated with the GPIO chip 5272 5272 - * firmware node to get added and bound to a driver. 5273 5273 - * 5274 5274 - * To allow these consumers to probe, we associate the struct 5275 5275 - * gpio_device of the GPIO chip with the firmware node and then simply 5276 5276 - * bind it to this stub driver. 5277 5277 - */ 5278 5278 - return 0; 5279 5279 - } 5280 5280 - 5264 5264 + /* 5265 5265 + * The DT node of some GPIO chips have a "compatible" property, but 5266 5266 + * never have a struct device added and probed by a driver to register 5267 5267 + * the GPIO chip with gpiolib. In such cases, fw_devlink=on will cause 5268 5268 + * the consumers of the GPIO chip to get probe deferred forever because 5269 5269 + * they will be waiting for a device associated with the GPIO chip 5270 5270 + * firmware node to get added and bound to a driver. 5271 5271 + * 5272 5272 + * To allow these consumers to probe, we associate the struct 5273 5273 + * gpio_device of the GPIO chip with the firmware node and then simply 5274 5274 + * bind it to this stub driver. 5275 5275 + */ 5281 5276 static struct device_driver gpio_stub_drv = { 5282 5277 .name = "gpio_stub_drv", 5283 5278 .bus = &gpio_bus_type, 5284 5284 - .probe = gpio_stub_drv_probe, 5285 5279 }; 5286 5280 5287 5281 static int __init gpiolib_dev_init(void)

+10 -8

drivers/mfd/Kconfig

reviewed

··· 2217 2217 and emergency shut down as well as 32,768KHz clock output. 2218 2218 2219 2219 config MFD_ROHM_BD71828 2220 2220 - tristate "ROHM BD71828 and BD71815 Power Management IC" 2220 2220 + tristate "ROHM BD718[15/28/79], BD72720 and BD73900 PMICs" 2221 2221 depends on I2C=y 2222 2222 depends on OF 2223 2223 select REGMAP_I2C 2224 2224 select REGMAP_IRQ 2225 2225 select MFD_CORE 2226 2226 help 2227 2227 - Select this option to get support for the ROHM BD71828 and BD71815 2228 2228 - Power Management ICs. BD71828GW and BD71815AGW are single-chip power 2229 2229 - management ICs mainly for battery-powered portable devices. 2230 2230 - The BD71828 integrates 7 buck converters and 7 LDOs. The BD71815 2231 2231 - has 5 bucks, 7 LDOs, and a boost for driving LEDs. Both ICs provide 2232 2232 - also a single-cell linear charger, a Coulomb counter, a real-time 2233 2233 - clock (RTC), GPIOs and a 32.768 kHz clock gate. 2227 2227 + Select this option to get support for the ROHM BD71815, BD71828, 2228 2228 + BD71879, BD72720 and BD73900 Power Management ICs (PMICs). These are 2229 2229 + single-chip Power Management ICs (PMIC), mainly for battery-powered 2230 2230 + portable devices. 2231 2231 + The BD71815 has 5 bucks, 7 LDOs, and a boost for driving LEDs. 2232 2232 + The BD718[28/79] have 7 buck converters and 7 LDOs. 2233 2233 + The BD72720 and the BD73900 have 10 bucks and 11 LDOs. 2234 2234 + All ICs provide a single-cell linear charger, a Coulomb counter, 2235 2235 + a Real-Time Clock (RTC), GPIOs and a 32.768 kHz clock gate. 2234 2236 2235 2237 config MFD_ROHM_BD957XMUF 2236 2238 tristate "ROHM BD9576MUF and BD9573MUF Power Management ICs"

+503 -52

drivers/mfd/rohm-bd71828.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 - // 3 3 - // Copyright (C) 2019 ROHM Semiconductors 4 4 - // 5 5 - // ROHM BD71828/BD71815 PMIC driver 2 2 + /* 3 3 + * Copyright (C) 2019 ROHM Semiconductors 4 4 + * 5 5 + * ROHM BD718[15/28/79] and BD72720 PMIC driver 6 6 + */ 6 7 7 8 #include <linux/gpio_keys.h> 8 9 #include <linux/i2c.h> ··· 14 13 #include <linux/mfd/core.h> 15 14 #include <linux/mfd/rohm-bd71815.h> 16 15 #include <linux/mfd/rohm-bd71828.h> 16 16 + #include <linux/mfd/rohm-bd72720.h> 17 17 #include <linux/mfd/rohm-generic.h> 18 18 #include <linux/module.h> 19 19 #include <linux/of.h> 20 20 #include <linux/regmap.h> 21 21 #include <linux/types.h> 22 22 + 23 23 + #define BD72720_TYPED_IRQ_REG(_irq, _stat_offset, _mask, _type_offset) \ 24 24 + [_irq] = { \ 25 25 + .reg_offset = (_stat_offset), \ 26 26 + .mask = (_mask), \ 27 27 + { \ 28 28 + .type_reg_offset = (_type_offset), \ 29 29 + .type_reg_mask = BD72720_GPIO_IRQ_TYPE_MASK, \ 30 30 + .type_rising_val = BD72720_GPIO_IRQ_TYPE_RISING, \ 31 31 + .type_falling_val = BD72720_GPIO_IRQ_TYPE_FALLING, \ 32 32 + .type_level_low_val = BD72720_GPIO_IRQ_TYPE_LOW, \ 33 33 + .type_level_high_val = BD72720_GPIO_IRQ_TYPE_HIGH, \ 34 34 + .types_supported = IRQ_TYPE_EDGE_BOTH | \ 35 35 + IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW, \ 36 36 + }, \ 37 37 + } 22 38 23 39 static struct gpio_keys_button button = { 24 40 .code = KEY_POWER, ··· 59 41 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd70528-rtc-alm-0"), 60 42 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd70528-rtc-alm-1"), 61 43 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"), 44 44 + }; 45 45 + 46 46 + static const struct resource bd72720_rtc_irqs[] = { 47 47 + DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC0, "bd70528-rtc-alm-0"), 48 48 + DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC1, "bd70528-rtc-alm-1"), 49 49 + DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC2, "bd70528-rtc-alm-2"), 62 50 }; 63 51 64 52 static const struct resource bd71815_power_irqs[] = { ··· 180 156 }, 181 157 }; 182 158 183 183 - static const struct regmap_range bd71815_volatile_ranges[] = { 159 159 + static const struct resource bd72720_power_irqs[] = { 160 160 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_RMV, "bd72720_int_vbus_rmv"), 161 161 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_DET, "bd72720_int_vbus_det"), 162 162 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_RES, "bd72720_int_vbus_mon_res"), 163 163 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_DET, "bd72720_int_vbus_mon_det"), 164 164 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_RES, "bd72720_int_vsys_mon_res"), 165 165 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_DET, "bd72720_int_vsys_mon_det"), 166 166 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_RES, "bd72720_int_vsys_uv_res"), 167 167 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_DET, "bd72720_int_vsys_uv_det"), 168 168 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_RES, "bd72720_int_vsys_lo_res"), 169 169 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_DET, "bd72720_int_vsys_lo_det"), 170 170 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_RES, "bd72720_int_vsys_ov_res"), 171 171 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_DET, "bd72720_int_vsys_ov_det"), 172 172 + DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_ILIM, "bd72720_int_bat_ilim"), 173 173 + DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_DONE, "bd72720_int_chg_done"), 174 174 + DEFINE_RES_IRQ_NAMED(BD72720_INT_EXTEMP_TOUT, "bd72720_int_extemp_tout"), 175 175 + DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_WDT_EXP, "bd72720_int_chg_wdt_exp"), 176 176 + DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_OUT, "bd72720_int_bat_mnt_out"), 177 177 + DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_IN, "bd72720_int_bat_mnt_in"), 178 178 + DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_TRNS, "bd72720_int_chg_trns"), 179 179 + 180 180 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_RES, "bd72720_int_vbat_mon_res"), 181 181 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_DET, "bd72720_int_vbat_mon_det"), 182 182 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_RES, "bd72720_int_vbat_sht_res"), 183 183 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_DET, "bd72720_int_vbat_sht_det"), 184 184 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_RES, "bd72720_int_vbat_lo_res"), 185 185 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_DET, "bd72720_int_vbat_lo_det"), 186 186 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_RES, "bd72720_int_vbat_ov_res"), 187 187 + DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_DET, "bd72720_int_vbat_ov_det"), 188 188 + DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_RMV, "bd72720_int_bat_rmv"), 189 189 + DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_DET, "bd72720_int_bat_det"), 190 190 + DEFINE_RES_IRQ_NAMED(BD72720_INT_DBAT_DET, "bd72720_int_dbat_det"), 191 191 + DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_TEMP_TRNS, "bd72720_int_bat_temp_trns"), 192 192 + DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_RES, "bd72720_int_lobtmp_res"), 193 193 + DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_DET, "bd72720_int_lobtmp_det"), 194 194 + DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_RES, "bd72720_int_ovbtmp_res"), 195 195 + DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_DET, "bd72720_int_ovbtmp_det"), 196 196 + DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_RES, "bd72720_int_ocur1_res"), 197 197 + DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_DET, "bd72720_int_ocur1_det"), 198 198 + DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_RES, "bd72720_int_ocur2_res"), 199 199 + DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_DET, "bd72720_int_ocur2_det"), 200 200 + DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_RES, "bd72720_int_ocur3_res"), 201 201 + DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_DET, "bd72720_int_ocur3_det"), 202 202 + DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON1_DET, "bd72720_int_cc_mon1_det"), 203 203 + DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON2_DET, "bd72720_int_cc_mon2_det"), 204 204 + DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON3_DET, "bd72720_int_cc_mon3_det"), 205 205 + }; 206 206 + 207 207 + static const struct mfd_cell bd72720_mfd_cells[] = { 208 208 + { .name = "bd72720-pmic", }, 209 209 + { .name = "bd72720-gpio", }, 210 210 + { .name = "bd72720-led", }, 211 211 + { .name = "bd72720-clk", }, 184 212 { 185 185 - .range_min = BD71815_REG_SEC, 186 186 - .range_max = BD71815_REG_YEAR, 213 213 + .name = "bd72720-power", 214 214 + .resources = bd72720_power_irqs, 215 215 + .num_resources = ARRAY_SIZE(bd72720_power_irqs), 187 216 }, { 188 188 - .range_min = BD71815_REG_CONF, 189 189 - .range_max = BD71815_REG_BAT_TEMP, 217 217 + .name = "bd72720-rtc", 218 218 + .resources = bd72720_rtc_irqs, 219 219 + .num_resources = ARRAY_SIZE(bd72720_rtc_irqs), 190 220 }, { 191 191 - .range_min = BD71815_REG_VM_IBAT_U, 192 192 - .range_max = BD71815_REG_CC_CTRL, 193 193 - }, { 194 194 - .range_min = BD71815_REG_CC_STAT, 195 195 - .range_max = BD71815_REG_CC_CURCD_L, 196 196 - }, { 197 197 - .range_min = BD71815_REG_VM_BTMP_MON, 198 198 - .range_max = BD71815_REG_VM_BTMP_MON, 199 199 - }, { 200 200 - .range_min = BD71815_REG_INT_STAT, 201 201 - .range_max = BD71815_REG_INT_UPDATE, 202 202 - }, { 203 203 - .range_min = BD71815_REG_VM_VSYS_U, 204 204 - .range_max = BD71815_REG_REX_CTRL_1, 205 205 - }, { 206 206 - .range_min = BD71815_REG_FULL_CCNTD_3, 207 207 - .range_max = BD71815_REG_CCNTD_CHG_2, 221 221 + .name = "gpio-keys", 222 222 + .platform_data = &bd71828_powerkey_data, 223 223 + .pdata_size = sizeof(bd71828_powerkey_data), 208 224 }, 209 225 }; 210 226 227 227 + static const struct regmap_range bd71815_volatile_ranges[] = { 228 228 + regmap_reg_range(BD71815_REG_SEC, BD71815_REG_YEAR), 229 229 + regmap_reg_range(BD71815_REG_CONF, BD71815_REG_BAT_TEMP), 230 230 + regmap_reg_range(BD71815_REG_VM_IBAT_U, BD71815_REG_CC_CTRL), 231 231 + regmap_reg_range(BD71815_REG_CC_STAT, BD71815_REG_CC_CURCD_L), 232 232 + regmap_reg_range(BD71815_REG_VM_BTMP_MON, BD71815_REG_VM_BTMP_MON), 233 233 + regmap_reg_range(BD71815_REG_INT_STAT, BD71815_REG_INT_UPDATE), 234 234 + regmap_reg_range(BD71815_REG_VM_VSYS_U, BD71815_REG_REX_CTRL_1), 235 235 + regmap_reg_range(BD71815_REG_FULL_CCNTD_3, BD71815_REG_CCNTD_CHG_2), 236 236 + }; 237 237 + 211 238 static const struct regmap_range bd71828_volatile_ranges[] = { 212 212 - { 213 213 - .range_min = BD71828_REG_PS_CTRL_1, 214 214 - .range_max = BD71828_REG_PS_CTRL_1, 215 215 - }, { 216 216 - .range_min = BD71828_REG_PS_CTRL_3, 217 217 - .range_max = BD71828_REG_PS_CTRL_3, 218 218 - }, { 219 219 - .range_min = BD71828_REG_RTC_SEC, 220 220 - .range_max = BD71828_REG_RTC_YEAR, 221 221 - }, { 222 222 - /* 223 223 - * For now make all charger registers volatile because many 224 224 - * needs to be and because the charger block is not that 225 225 - * performance critical. 226 226 - */ 227 227 - .range_min = BD71828_REG_CHG_STATE, 228 228 - .range_max = BD71828_REG_CHG_FULL, 229 229 - }, { 230 230 - .range_min = BD71828_REG_INT_MAIN, 231 231 - .range_max = BD71828_REG_IO_STAT, 232 232 - }, 239 239 + regmap_reg_range(BD71828_REG_PS_CTRL_1, BD71828_REG_PS_CTRL_1), 240 240 + regmap_reg_range(BD71828_REG_PS_CTRL_3, BD71828_REG_PS_CTRL_3), 241 241 + regmap_reg_range(BD71828_REG_RTC_SEC, BD71828_REG_RTC_YEAR), 242 242 + /* 243 243 + * For now make all charger registers volatile because many 244 244 + * needs to be and because the charger block is not that 245 245 + * performance critical. 246 246 + */ 247 247 + regmap_reg_range(BD71828_REG_CHG_STATE, BD71828_REG_CHG_FULL), 248 248 + regmap_reg_range(BD71828_REG_INT_MAIN, BD71828_REG_IO_STAT), 249 249 + }; 250 250 + 251 251 + static const struct regmap_range bd72720_volatile_ranges_4b[] = { 252 252 + regmap_reg_range(BD72720_REG_RESETSRC_1, BD72720_REG_RESETSRC_2), 253 253 + regmap_reg_range(BD72720_REG_POWER_STATE, BD72720_REG_POWER_STATE), 254 254 + /* The state indicator bit changes when new state is reached */ 255 255 + regmap_reg_range(BD72720_REG_PS_CTRL_1, BD72720_REG_PS_CTRL_1), 256 256 + regmap_reg_range(BD72720_REG_RCVNUM, BD72720_REG_RCVNUM), 257 257 + regmap_reg_range(BD72720_REG_CONF, BD72720_REG_HALL_STAT), 258 258 + regmap_reg_range(BD72720_REG_RTC_SEC, BD72720_REG_RTC_YEAR), 259 259 + regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_SRC), 260 260 + }; 261 261 + 262 262 + static const struct regmap_range bd72720_precious_ranges_4b[] = { 263 263 + regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_STAT), 264 264 + }; 265 265 + 266 266 + /* 267 267 + * The BD72720 is an odd beast in that it contains two separate sets of 268 268 + * registers, both starting from address 0x0. The twist is that these "pages" 269 269 + * are behind different I2C slave addresses. Most of the registers are behind 270 270 + * a slave address 0x4b, which will be used as the "main" address for this 271 271 + * device. 272 272 + * 273 273 + * Most of the charger related registers are located behind slave address 0x4c. 274 274 + * It is tempting to push the dealing with the charger registers and the extra 275 275 + * 0x4c device in power-supply driver - but perhaps it's better for the sake of 276 276 + * the cleaner re-use to deal with setting up all of the regmaps here. 277 277 + * Furthermore, the LED stuff may need access to both of these devices. 278 278 + * 279 279 + * Instead of providing one of the regmaps to sub-devices in MFD platform data, 280 280 + * we create one more 'wrapper regmap' with custom read/write operations. These 281 281 + * custom accessors will select which of the 'real' regmaps to use, based on 282 282 + * the register address. 283 283 + * 284 284 + * The register addresses are 8-bit, so we add offset 0x100 to the addresses 285 285 + * behind the secondary slave 0x4c. The 'wrapper' regmap can then detect the 286 286 + * correct slave address based on the register address and call regmap_write() 287 287 + * and regmap_read() using correct 'real' regmap. This way the registers of 288 288 + * both of the slaves can be accessed using one 'wrapper' regmap. 289 289 + * 290 290 + * NOTE: The added offsets mean that the defined addresses for slave 0x4c must 291 291 + * be used through the 'wrapper' regmap because the offset must be stripped 292 292 + * from the register addresses. The 0x4b can be accessed both indirectly using 293 293 + * the 'wrapper' regmap, and directly using the 'real' regmap. 294 294 + */ 295 295 + #define BD72720_SECONDARY_I2C_SLAVE 0x4c 296 296 + #define BD72720_SECONDARY_I2C_REG_OFFSET 0x100 297 297 + 298 298 + struct bd72720_regmaps { 299 299 + struct regmap *map1_4b; 300 300 + struct regmap *map2_4c; 301 301 + }; 302 302 + 303 303 + /* Translate the slave 0x4c wrapper register address to a real one */ 304 304 + #define BD72720_REG_UNWRAP(reg) ((reg) - BD72720_SECONDARY_I2C_REG_OFFSET) 305 305 + 306 306 + /* Ranges given to 'real' 0x4c regmap must use unwrapped addresses. */ 307 307 + #define BD72720_UNWRAP_REG_RANGE(startreg, endreg) \ 308 308 + regmap_reg_range(BD72720_REG_UNWRAP(startreg), BD72720_REG_UNWRAP(endreg)) 309 309 + 310 310 + static const struct regmap_range bd72720_volatile_ranges_4c[] = { 311 311 + /* Status information */ 312 312 + BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_STATE, BD72720_REG_CHG_EN), 313 313 + /* 314 314 + * Under certain circumstances, write to some bits may be 315 315 + * ignored 316 316 + */ 317 317 + BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_CTRL, BD72720_REG_CHG_CTRL), 318 318 + /* 319 319 + * TODO: Ensure this is used to advertise state, not (only?) to 320 320 + * control it. 321 321 + */ 322 322 + BD72720_UNWRAP_REG_RANGE(BD72720_REG_VSYS_STATE_STAT, BD72720_REG_VSYS_STATE_STAT), 323 323 + /* Measured data */ 324 324 + BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VBAT_U, BD72720_REG_VM_VF_L), 325 325 + /* Self clearing bits */ 326 326 + BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VSYS_SA_MINMAX_CTRL, 327 327 + BD72720_REG_VM_VSYS_SA_MINMAX_CTRL), 328 328 + /* Counters, self clearing bits */ 329 329 + BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CURCD_U, BD72720_REG_CC_CTRL), 330 330 + /* Self clearing bits */ 331 331 + BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CCNTD_CTRL, BD72720_REG_CC_CCNTD_CTRL), 332 332 + /* Self clearing bits */ 333 333 + BD72720_UNWRAP_REG_RANGE(BD72720_REG_IMPCHK_CTRL, BD72720_REG_IMPCHK_CTRL), 233 334 }; 234 335 235 336 static const struct regmap_access_table bd71815_volatile_regs = { ··· 365 216 static const struct regmap_access_table bd71828_volatile_regs = { 366 217 .yes_ranges = &bd71828_volatile_ranges[0], 367 218 .n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges), 219 219 + }; 220 220 + 221 221 + static const struct regmap_access_table bd72720_volatile_regs_4b = { 222 222 + .yes_ranges = &bd72720_volatile_ranges_4b[0], 223 223 + .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4b), 224 224 + }; 225 225 + 226 226 + static const struct regmap_access_table bd72720_precious_regs_4b = { 227 227 + .yes_ranges = &bd72720_precious_ranges_4b[0], 228 228 + .n_yes_ranges = ARRAY_SIZE(bd72720_precious_ranges_4b), 229 229 + }; 230 230 + 231 231 + static const struct regmap_access_table bd72720_volatile_regs_4c = { 232 232 + .yes_ranges = &bd72720_volatile_ranges_4c[0], 233 233 + .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4c), 368 234 }; 369 235 370 236 static const struct regmap_config bd71815_regmap = { ··· 398 234 .cache_type = REGCACHE_MAPLE, 399 235 }; 400 236 237 237 + static int regmap_write_wrapper(void *context, unsigned int reg, unsigned int val) 238 238 + { 239 239 + struct bd72720_regmaps *maps = context; 240 240 + 241 241 + if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 242 242 + return regmap_write(maps->map1_4b, reg, val); 243 243 + 244 244 + reg = BD72720_REG_UNWRAP(reg); 245 245 + 246 246 + return regmap_write(maps->map2_4c, reg, val); 247 247 + } 248 248 + 249 249 + static int regmap_read_wrapper(void *context, unsigned int reg, unsigned int *val) 250 250 + { 251 251 + struct bd72720_regmaps *maps = context; 252 252 + 253 253 + if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 254 254 + return regmap_read(maps->map1_4b, reg, val); 255 255 + 256 256 + reg = BD72720_REG_UNWRAP(reg); 257 257 + 258 258 + return regmap_read(maps->map2_4c, reg, val); 259 259 + } 260 260 + 261 261 + static const struct regmap_config bd72720_wrapper_map_config = { 262 262 + .name = "wrap-map", 263 263 + .reg_bits = 9, 264 264 + .val_bits = 8, 265 265 + .max_register = BD72720_REG_IMPCHK_CTRL, 266 266 + /* 267 267 + * We don't want to duplicate caches. It would be a bit faster to 268 268 + * have the cache in this 'wrapper regmap', and not in the 'real 269 269 + * regmaps' bd72720_regmap_4b and bd72720_regmap_4c below. This would 270 270 + * require all the subdevices to use the wrapper-map in order to be 271 271 + * able to benefit from the cache. 272 272 + * Currently most of the sub-devices use only the same slave-address 273 273 + * as this MFD driver. Now, because we don't add the offset to the 274 274 + * registers belonging to this slave, those devices can use either the 275 275 + * wrapper map, or the bd72720_regmap_4b directly. This means majority 276 276 + * of our sub devices don't need to care which regmap they get using 277 277 + * the dev_get_regmap(). This unifies the code between the BD72720 and 278 278 + * those variants which don't have this 'multiple slave addresses' 279 279 + * -hassle. 280 280 + * So, for a small performance penalty, we simplify the code for the 281 281 + * sub-devices by having the caches in the wrapped regmaps and not here. 282 282 + */ 283 283 + .cache_type = REGCACHE_NONE, 284 284 + .reg_write = regmap_write_wrapper, 285 285 + .reg_read = regmap_read_wrapper, 286 286 + }; 287 287 + 288 288 + static const struct regmap_config bd72720_regmap_4b = { 289 289 + .reg_bits = 8, 290 290 + .val_bits = 8, 291 291 + .volatile_table = &bd72720_volatile_regs_4b, 292 292 + .precious_table = &bd72720_precious_regs_4b, 293 293 + .max_register = BD72720_REG_INT_ETC2_SRC, 294 294 + .cache_type = REGCACHE_MAPLE, 295 295 + }; 296 296 + 297 297 + static const struct regmap_config bd72720_regmap_4c = { 298 298 + .reg_bits = 8, 299 299 + .val_bits = 8, 300 300 + .volatile_table = &bd72720_volatile_regs_4c, 301 301 + .max_register = BD72720_REG_UNWRAP(BD72720_REG_IMPCHK_CTRL), 302 302 + .cache_type = REGCACHE_MAPLE, 303 303 + }; 304 304 + 401 305 /* 402 306 * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can 403 307 * access corect sub-IRQ registers based on bits that are set in main IRQ 404 404 - * register. BD71815 and BD71828 have same sub-register-block offests. 308 308 + * register. BD71815 and BD71828 have same sub-register-block offests, the 309 309 + * BD72720 has a different one. 405 310 */ 406 311 407 312 static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */ ··· 482 249 static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */ 483 250 static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */ 484 251 252 252 + static unsigned int bd72720_bit0_offsets[] = {0, 1}; /* PS1 and PS2 */ 253 253 + static unsigned int bd72720_bit1_offsets[] = {2, 3}; /* DVS1 and DVS2 */ 254 254 + static unsigned int bd72720_bit2_offsets[] = {4}; /* VBUS */ 255 255 + static unsigned int bd72720_bit3_offsets[] = {5}; /* VSYS */ 256 256 + static unsigned int bd72720_bit4_offsets[] = {6}; /* CHG */ 257 257 + static unsigned int bd72720_bit5_offsets[] = {7, 8}; /* BAT1 and BAT2 */ 258 258 + static unsigned int bd72720_bit6_offsets[] = {9}; /* IBAT */ 259 259 + static unsigned int bd72720_bit7_offsets[] = {10, 11}; /* ETC1 and ETC2 */ 260 260 + 485 261 static const struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = { 486 262 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 487 263 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), ··· 500 258 REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), 501 259 REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), 502 260 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 261 261 + }; 262 262 + 263 263 + static const struct regmap_irq_sub_irq_map bd72720_sub_irq_offsets[] = { 264 264 + REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit0_offsets), 265 265 + REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit1_offsets), 266 266 + REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit2_offsets), 267 267 + REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit3_offsets), 268 268 + REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit4_offsets), 269 269 + REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit5_offsets), 270 270 + REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit6_offsets), 271 271 + REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit7_offsets), 503 272 }; 504 273 505 274 static const struct regmap_irq bd71815_irqs[] = { ··· 686 433 REGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK), 687 434 }; 688 435 436 436 + static const struct regmap_irq bd72720_irqs[] = { 437 437 + REGMAP_IRQ_REG(BD72720_INT_LONGPUSH, 0, BD72720_INT_LONGPUSH_MASK), 438 438 + REGMAP_IRQ_REG(BD72720_INT_MIDPUSH, 0, BD72720_INT_MIDPUSH_MASK), 439 439 + REGMAP_IRQ_REG(BD72720_INT_SHORTPUSH, 0, BD72720_INT_SHORTPUSH_MASK), 440 440 + REGMAP_IRQ_REG(BD72720_INT_PUSH, 0, BD72720_INT_PUSH_MASK), 441 441 + REGMAP_IRQ_REG(BD72720_INT_HALL_DET, 0, BD72720_INT_HALL_DET_MASK), 442 442 + REGMAP_IRQ_REG(BD72720_INT_HALL_TGL, 0, BD72720_INT_HALL_TGL_MASK), 443 443 + REGMAP_IRQ_REG(BD72720_INT_WDOG, 0, BD72720_INT_WDOG_MASK), 444 444 + REGMAP_IRQ_REG(BD72720_INT_SWRESET, 0, BD72720_INT_SWRESET_MASK), 445 445 + REGMAP_IRQ_REG(BD72720_INT_SEQ_DONE, 1, BD72720_INT_SEQ_DONE_MASK), 446 446 + REGMAP_IRQ_REG(BD72720_INT_PGFAULT, 1, BD72720_INT_PGFAULT_MASK), 447 447 + REGMAP_IRQ_REG(BD72720_INT_BUCK1_DVS, 2, BD72720_INT_BUCK1_DVS_MASK), 448 448 + REGMAP_IRQ_REG(BD72720_INT_BUCK2_DVS, 2, BD72720_INT_BUCK2_DVS_MASK), 449 449 + REGMAP_IRQ_REG(BD72720_INT_BUCK3_DVS, 2, BD72720_INT_BUCK3_DVS_MASK), 450 450 + REGMAP_IRQ_REG(BD72720_INT_BUCK4_DVS, 2, BD72720_INT_BUCK4_DVS_MASK), 451 451 + REGMAP_IRQ_REG(BD72720_INT_BUCK5_DVS, 2, BD72720_INT_BUCK5_DVS_MASK), 452 452 + REGMAP_IRQ_REG(BD72720_INT_BUCK6_DVS, 2, BD72720_INT_BUCK6_DVS_MASK), 453 453 + REGMAP_IRQ_REG(BD72720_INT_BUCK7_DVS, 2, BD72720_INT_BUCK7_DVS_MASK), 454 454 + REGMAP_IRQ_REG(BD72720_INT_BUCK8_DVS, 2, BD72720_INT_BUCK8_DVS_MASK), 455 455 + REGMAP_IRQ_REG(BD72720_INT_BUCK9_DVS, 3, BD72720_INT_BUCK9_DVS_MASK), 456 456 + REGMAP_IRQ_REG(BD72720_INT_BUCK10_DVS, 3, BD72720_INT_BUCK10_DVS_MASK), 457 457 + REGMAP_IRQ_REG(BD72720_INT_LDO1_DVS, 3, BD72720_INT_LDO1_DVS_MASK), 458 458 + REGMAP_IRQ_REG(BD72720_INT_LDO2_DVS, 3, BD72720_INT_LDO2_DVS_MASK), 459 459 + REGMAP_IRQ_REG(BD72720_INT_LDO3_DVS, 3, BD72720_INT_LDO3_DVS_MASK), 460 460 + REGMAP_IRQ_REG(BD72720_INT_LDO4_DVS, 3, BD72720_INT_LDO4_DVS_MASK), 461 461 + 462 462 + REGMAP_IRQ_REG(BD72720_INT_VBUS_RMV, 4, BD72720_INT_VBUS_RMV_MASK), 463 463 + REGMAP_IRQ_REG(BD72720_INT_VBUS_DET, 4, BD72720_INT_VBUS_DET_MASK), 464 464 + REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_RES, 4, BD72720_INT_VBUS_MON_RES_MASK), 465 465 + REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_DET, 4, BD72720_INT_VBUS_MON_DET_MASK), 466 466 + REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_RES, 5, BD72720_INT_VSYS_MON_RES_MASK), 467 467 + REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_DET, 5, BD72720_INT_VSYS_MON_DET_MASK), 468 468 + REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_RES, 5, BD72720_INT_VSYS_UV_RES_MASK), 469 469 + REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_DET, 5, BD72720_INT_VSYS_UV_DET_MASK), 470 470 + REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_RES, 5, BD72720_INT_VSYS_LO_RES_MASK), 471 471 + REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_DET, 5, BD72720_INT_VSYS_LO_DET_MASK), 472 472 + REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_RES, 5, BD72720_INT_VSYS_OV_RES_MASK), 473 473 + REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_DET, 5, BD72720_INT_VSYS_OV_DET_MASK), 474 474 + REGMAP_IRQ_REG(BD72720_INT_BAT_ILIM, 6, BD72720_INT_BAT_ILIM_MASK), 475 475 + REGMAP_IRQ_REG(BD72720_INT_CHG_DONE, 6, BD72720_INT_CHG_DONE_MASK), 476 476 + REGMAP_IRQ_REG(BD72720_INT_EXTEMP_TOUT, 6, BD72720_INT_EXTEMP_TOUT_MASK), 477 477 + REGMAP_IRQ_REG(BD72720_INT_CHG_WDT_EXP, 6, BD72720_INT_CHG_WDT_EXP_MASK), 478 478 + REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_OUT, 6, BD72720_INT_BAT_MNT_OUT_MASK), 479 479 + REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_IN, 6, BD72720_INT_BAT_MNT_IN_MASK), 480 480 + REGMAP_IRQ_REG(BD72720_INT_CHG_TRNS, 6, BD72720_INT_CHG_TRNS_MASK), 481 481 + 482 482 + REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_RES, 7, BD72720_INT_VBAT_MON_RES_MASK), 483 483 + REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_DET, 7, BD72720_INT_VBAT_MON_DET_MASK), 484 484 + REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_RES, 7, BD72720_INT_VBAT_SHT_RES_MASK), 485 485 + REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_DET, 7, BD72720_INT_VBAT_SHT_DET_MASK), 486 486 + REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_RES, 7, BD72720_INT_VBAT_LO_RES_MASK), 487 487 + REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_DET, 7, BD72720_INT_VBAT_LO_DET_MASK), 488 488 + REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_RES, 7, BD72720_INT_VBAT_OV_RES_MASK), 489 489 + REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_DET, 7, BD72720_INT_VBAT_OV_DET_MASK), 490 490 + REGMAP_IRQ_REG(BD72720_INT_BAT_RMV, 8, BD72720_INT_BAT_RMV_MASK), 491 491 + REGMAP_IRQ_REG(BD72720_INT_BAT_DET, 8, BD72720_INT_BAT_DET_MASK), 492 492 + REGMAP_IRQ_REG(BD72720_INT_DBAT_DET, 8, BD72720_INT_DBAT_DET_MASK), 493 493 + REGMAP_IRQ_REG(BD72720_INT_BAT_TEMP_TRNS, 8, BD72720_INT_BAT_TEMP_TRNS_MASK), 494 494 + REGMAP_IRQ_REG(BD72720_INT_LOBTMP_RES, 8, BD72720_INT_LOBTMP_RES_MASK), 495 495 + REGMAP_IRQ_REG(BD72720_INT_LOBTMP_DET, 8, BD72720_INT_LOBTMP_DET_MASK), 496 496 + REGMAP_IRQ_REG(BD72720_INT_OVBTMP_RES, 8, BD72720_INT_OVBTMP_RES_MASK), 497 497 + REGMAP_IRQ_REG(BD72720_INT_OVBTMP_DET, 8, BD72720_INT_OVBTMP_DET_MASK), 498 498 + REGMAP_IRQ_REG(BD72720_INT_OCUR1_RES, 9, BD72720_INT_OCUR1_RES_MASK), 499 499 + REGMAP_IRQ_REG(BD72720_INT_OCUR1_DET, 9, BD72720_INT_OCUR1_DET_MASK), 500 500 + REGMAP_IRQ_REG(BD72720_INT_OCUR2_RES, 9, BD72720_INT_OCUR2_RES_MASK), 501 501 + REGMAP_IRQ_REG(BD72720_INT_OCUR2_DET, 9, BD72720_INT_OCUR2_DET_MASK), 502 502 + REGMAP_IRQ_REG(BD72720_INT_OCUR3_RES, 9, BD72720_INT_OCUR3_RES_MASK), 503 503 + REGMAP_IRQ_REG(BD72720_INT_OCUR3_DET, 9, BD72720_INT_OCUR3_DET_MASK), 504 504 + REGMAP_IRQ_REG(BD72720_INT_CC_MON1_DET, 10, BD72720_INT_CC_MON1_DET_MASK), 505 505 + REGMAP_IRQ_REG(BD72720_INT_CC_MON2_DET, 10, BD72720_INT_CC_MON2_DET_MASK), 506 506 + REGMAP_IRQ_REG(BD72720_INT_CC_MON3_DET, 10, BD72720_INT_CC_MON3_DET_MASK), 507 507 + /* 508 508 + * The GPIO1_IN and GPIO2_IN IRQs are generated from the PMIC's GPIO1 and GPIO2 509 509 + * pins. Eg, they may be wired to other devices which can then use the PMIC as 510 510 + * an interrupt controller. The GPIO1 and GPIO2 can have the IRQ type 511 511 + * specified. All of the types (falling, rising, and both edges as well as low 512 512 + * and high levels) are supported. 513 513 + */ 514 514 + BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO1_IN, 10, BD72720_INT_GPIO1_IN_MASK, 0), 515 515 + BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO2_IN, 10, BD72720_INT_GPIO2_IN_MASK, 1), 516 516 + REGMAP_IRQ_REG(BD72720_INT_VF125_RES, 11, BD72720_INT_VF125_RES_MASK), 517 517 + REGMAP_IRQ_REG(BD72720_INT_VF125_DET, 11, BD72720_INT_VF125_DET_MASK), 518 518 + REGMAP_IRQ_REG(BD72720_INT_VF_RES, 11, BD72720_INT_VF_RES_MASK), 519 519 + REGMAP_IRQ_REG(BD72720_INT_VF_DET, 11, BD72720_INT_VF_DET_MASK), 520 520 + REGMAP_IRQ_REG(BD72720_INT_RTC0, 11, BD72720_INT_RTC0_MASK), 521 521 + REGMAP_IRQ_REG(BD72720_INT_RTC1, 11, BD72720_INT_RTC1_MASK), 522 522 + REGMAP_IRQ_REG(BD72720_INT_RTC2, 11, BD72720_INT_RTC2_MASK), 523 523 + }; 524 524 + 525 525 + static int bd72720_set_type_config(unsigned int **buf, unsigned int type, 526 526 + const struct regmap_irq *irq_data, 527 527 + int idx, void *irq_drv_data) 528 528 + { 529 529 + const struct regmap_irq_type *t = &irq_data->type; 530 530 + 531 531 + /* 532 532 + * The regmap IRQ ecpects IRQ_TYPE_EDGE_BOTH to be written to register 533 533 + * as logical OR of the type_falling_val and type_rising_val. This is 534 534 + * not how the BD72720 implements this configuration, hence we need 535 535 + * to handle this specific case separately. 536 536 + */ 537 537 + if (type == IRQ_TYPE_EDGE_BOTH) { 538 538 + buf[0][idx] &= ~t->type_reg_mask; 539 539 + buf[0][idx] |= BD72720_GPIO_IRQ_TYPE_BOTH; 540 540 + 541 541 + return 0; 542 542 + } 543 543 + 544 544 + return regmap_irq_set_type_config_simple(buf, type, irq_data, idx, irq_drv_data); 545 545 + } 546 546 + 689 547 static const struct regmap_irq_chip bd71828_irq_chip = { 690 548 .name = "bd71828_irq", 691 549 .main_status = BD71828_REG_INT_MAIN, ··· 825 461 .num_regs = 12, 826 462 .num_main_regs = 1, 827 463 .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], 464 464 + .num_main_status_bits = 8, 465 465 + .irq_reg_stride = 1, 466 466 + }; 467 467 + 468 468 + static const unsigned int bd72720_irq_type_base[] = { BD72720_REG_GPIO1_CTRL }; 469 469 + 470 470 + static const struct regmap_irq_chip bd72720_irq_chip = { 471 471 + .name = "bd72720_irq", 472 472 + .main_status = BD72720_REG_INT_LVL1_STAT, 473 473 + .irqs = &bd72720_irqs[0], 474 474 + .num_irqs = ARRAY_SIZE(bd72720_irqs), 475 475 + .status_base = BD72720_REG_INT_PS1_STAT, 476 476 + .unmask_base = BD72720_REG_INT_PS1_EN, 477 477 + .config_base = &bd72720_irq_type_base[0], 478 478 + .num_config_bases = 1, 479 479 + .num_config_regs = 2, 480 480 + .set_type_config = bd72720_set_type_config, 481 481 + .ack_base = BD72720_REG_INT_PS1_STAT, 482 482 + .init_ack_masked = true, 483 483 + .num_regs = 12, 484 484 + .num_main_regs = 1, 485 485 + .sub_reg_offsets = &bd72720_sub_irq_offsets[0], 828 486 .num_main_status_bits = 8, 829 487 .irq_reg_stride = 1, 830 488 }; ··· 897 511 pm_power_off = NULL; 898 512 } 899 513 514 514 + static struct regmap *bd72720_do_regmaps(struct i2c_client *i2c) 515 515 + { 516 516 + struct bd72720_regmaps *maps; 517 517 + struct i2c_client *secondary_i2c; 518 518 + 519 519 + secondary_i2c = devm_i2c_new_dummy_device(&i2c->dev, i2c->adapter, 520 520 + BD72720_SECONDARY_I2C_SLAVE); 521 521 + if (IS_ERR(secondary_i2c)) { 522 522 + dev_err_probe(&i2c->dev, PTR_ERR(secondary_i2c), "Failed to get secondary I2C\n"); 523 523 + 524 524 + return ERR_CAST(secondary_i2c); 525 525 + } 526 526 + 527 527 + maps = devm_kzalloc(&i2c->dev, sizeof(*maps), GFP_KERNEL); 528 528 + if (!maps) 529 529 + return ERR_PTR(-ENOMEM); 530 530 + 531 531 + maps->map1_4b = devm_regmap_init_i2c(i2c, &bd72720_regmap_4b); 532 532 + if (IS_ERR(maps->map1_4b)) 533 533 + return maps->map1_4b; 534 534 + 535 535 + maps->map2_4c = devm_regmap_init_i2c(secondary_i2c, &bd72720_regmap_4c); 536 536 + if (IS_ERR(maps->map2_4c)) 537 537 + return maps->map2_4c; 538 538 + 539 539 + return devm_regmap_init(&i2c->dev, NULL, maps, &bd72720_wrapper_map_config); 540 540 + } 541 541 + 900 542 static int bd71828_i2c_probe(struct i2c_client *i2c) 901 543 { 902 544 struct regmap_irq_chip_data *irq_data; 903 545 int ret; 904 904 - struct regmap *regmap; 546 546 + struct regmap *regmap = NULL; 905 547 const struct regmap_config *regmap_config; 906 548 const struct regmap_irq_chip *irqchip; 907 549 unsigned int chip_type; ··· 937 523 int cells; 938 524 int button_irq; 939 525 int clkmode_reg; 526 526 + int main_lvl_mask_reg = 0, main_lvl_val = 0; 940 527 941 528 if (!i2c->irq) { 942 529 dev_err(&i2c->dev, "No IRQ configured\n"); ··· 969 554 */ 970 555 button_irq = 0; 971 556 break; 557 557 + case ROHM_CHIP_TYPE_BD72720: 558 558 + { 559 559 + mfd = bd72720_mfd_cells; 560 560 + cells = ARRAY_SIZE(bd72720_mfd_cells); 561 561 + 562 562 + regmap = bd72720_do_regmaps(i2c); 563 563 + if (IS_ERR(regmap)) 564 564 + return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 565 565 + "Failed to initialize Regmap\n"); 566 566 + 567 567 + irqchip = &bd72720_irq_chip; 568 568 + clkmode_reg = BD72720_REG_OUT32K; 569 569 + button_irq = BD72720_INT_SHORTPUSH; 570 570 + main_lvl_mask_reg = BD72720_REG_INT_LVL1_EN; 571 571 + main_lvl_val = BD72720_MASK_LVL1_EN_ALL; 572 572 + break; 573 573 + } 972 574 default: 973 575 dev_err(&i2c->dev, "Unknown device type"); 974 576 return -EINVAL; 975 577 } 976 578 977 977 - regmap = devm_regmap_init_i2c(i2c, regmap_config); 978 978 - if (IS_ERR(regmap)) 979 979 - return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 579 579 + if (!regmap) { 580 580 + regmap = devm_regmap_init_i2c(i2c, regmap_config); 581 581 + if (IS_ERR(regmap)) 582 582 + return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 980 583 "Failed to initialize Regmap\n"); 584 584 + } 981 585 982 586 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq, 983 587 IRQF_ONESHOT, 0, irqchip, &irq_data); ··· 1007 573 dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n", 1008 574 irqchip->num_irqs); 1009 575 576 576 + /* 577 577 + * On some ICs the main IRQ register has corresponding mask register. 578 578 + * This is not handled by the regmap IRQ. Let's enable all the main 579 579 + * level IRQs here. Further writes to the main level MASK is not 580 580 + * needed because masking is handled by the per IRQ 2.nd level MASK 581 581 + * registers. 2.nd level masks are handled by the regmap IRQ. 582 582 + */ 583 583 + if (main_lvl_mask_reg) { 584 584 + ret = regmap_write(regmap, main_lvl_mask_reg, main_lvl_val); 585 585 + if (ret) { 586 586 + return dev_err_probe(&i2c->dev, ret, 587 587 + "Failed to enable main level IRQs\n"); 588 588 + } 589 589 + } 1010 590 if (button_irq) { 1011 591 ret = regmap_irq_get_virq(irq_data, button_irq); 1012 592 if (ret < 0) ··· 1062 614 }, { 1063 615 .compatible = "rohm,bd71815", 1064 616 .data = (void *)ROHM_CHIP_TYPE_BD71815, 617 617 + }, { 618 618 + .compatible = "rohm,bd72720", 619 619 + .data = (void *)ROHM_CHIP_TYPE_BD72720, 1065 620 }, 1066 621 { }, 1067 622 };

+129 -31

drivers/power/supply/bd71828-power.c

reviewed

··· 5 5 #include <linux/kernel.h> 6 6 #include <linux/mfd/rohm-bd71815.h> 7 7 #include <linux/mfd/rohm-bd71828.h> 8 8 + #include <linux/mfd/rohm-bd72720.h> 8 9 #include <linux/module.h> 9 10 #include <linux/mod_devicetable.h> 10 11 #include <linux/platform_device.h> ··· 45 44 #define VBAT_LOW_TH 0x00D4 46 45 47 46 struct pwr_regs { 48 48 - u8 vbat_avg; 49 49 - u8 ibat; 50 50 - u8 ibat_avg; 51 51 - u8 btemp_vth; 52 52 - u8 chg_state; 53 53 - u8 bat_temp; 54 54 - u8 dcin_stat; 55 55 - u8 dcin_collapse_limit; 56 56 - u8 chg_set1; 57 57 - u8 chg_en; 58 58 - u8 vbat_alm_limit_u; 59 59 - u8 conf; 60 60 - u8 vdcin; 47 47 + unsigned int vbat_avg; 48 48 + unsigned int ibat; 49 49 + unsigned int ibat_avg; 50 50 + unsigned int btemp_vth; 51 51 + unsigned int chg_state; 52 52 + unsigned int bat_temp; 53 53 + unsigned int dcin_stat; 54 54 + unsigned int dcin_online_mask; 55 55 + unsigned int dcin_collapse_limit; 56 56 + unsigned int chg_set1; 57 57 + unsigned int chg_en; 58 58 + unsigned int vbat_alm_limit_u; 59 59 + unsigned int conf; 60 60 + unsigned int vdcin; 61 61 + unsigned int vdcin_himask; 61 62 }; 62 63 63 64 static const struct pwr_regs pwr_regs_bd71828 = { ··· 70 67 .chg_state = BD71828_REG_CHG_STATE, 71 68 .bat_temp = BD71828_REG_BAT_TEMP, 72 69 .dcin_stat = BD71828_REG_DCIN_STAT, 70 70 + .dcin_online_mask = BD7182x_MASK_DCIN_DET, 73 71 .dcin_collapse_limit = BD71828_REG_DCIN_CLPS, 74 72 .chg_set1 = BD71828_REG_CHG_SET1, 75 73 .chg_en = BD71828_REG_CHG_EN, 76 74 .vbat_alm_limit_u = BD71828_REG_ALM_VBAT_LIMIT_U, 77 75 .conf = BD71828_REG_CONF, 78 76 .vdcin = BD71828_REG_VDCIN_U, 77 77 + .vdcin_himask = BD7182x_MASK_VDCIN_U, 79 78 }; 80 79 81 80 static const struct pwr_regs pwr_regs_bd71815 = { ··· 90 85 .chg_state = BD71815_REG_CHG_STATE, 91 86 .bat_temp = BD71815_REG_BAT_TEMP, 92 87 .dcin_stat = BD71815_REG_DCIN_STAT, 88 88 + .dcin_online_mask = BD7182x_MASK_DCIN_DET, 93 89 .dcin_collapse_limit = BD71815_REG_DCIN_CLPS, 94 90 .chg_set1 = BD71815_REG_CHG_SET1, 95 91 .chg_en = BD71815_REG_CHG_SET1, ··· 98 92 .conf = BD71815_REG_CONF, 99 93 100 94 .vdcin = BD71815_REG_VM_DCIN_U, 95 95 + .vdcin_himask = BD7182x_MASK_VDCIN_U, 96 96 + }; 97 97 + 98 98 + static struct pwr_regs pwr_regs_bd72720 = { 99 99 + .vbat_avg = BD72720_REG_VM_SA_VBAT_U, 100 100 + .ibat = BD72720_REG_CC_CURCD_U, 101 101 + .ibat_avg = BD72720_REG_CC_SA_CURCD_U, 102 102 + .btemp_vth = BD72720_REG_VM_BTMP_U, 103 103 + /* 104 104 + * Note, state 0x40 IMP_CHK. not documented 105 105 + * on other variants but was still handled in 106 106 + * existing code. No memory traces as to why. 107 107 + */ 108 108 + .chg_state = BD72720_REG_CHG_STATE, 109 109 + .bat_temp = BD72720_REG_CHG_BAT_TEMP_STAT, 110 110 + .dcin_stat = BD72720_REG_INT_VBUS_SRC, 111 111 + .dcin_online_mask = BD72720_MASK_DCIN_DET, 112 112 + .dcin_collapse_limit = -1, /* Automatic. Setting not supported */ 113 113 + .chg_set1 = BD72720_REG_CHG_SET_1, 114 114 + .chg_en = BD72720_REG_CHG_EN, 115 115 + /* 15mV note in data-sheet */ 116 116 + .vbat_alm_limit_u = BD72720_REG_ALM_VBAT_TH_U, 117 117 + .conf = BD72720_REG_CONF, /* o XSTB, only PON. Seprate slave addr */ 118 118 + .vdcin = BD72720_REG_VM_VBUS_U, /* 10 bits not 11 as with other ICs */ 119 119 + .vdcin_himask = BD72720_MASK_VDCIN_U, 101 120 }; 102 121 103 122 struct bd71828_power { ··· 329 298 dev_err(pwr->dev, "Failed to read DCIN status\n"); 330 299 return ret; 331 300 } 332 332 - *chg_online = ((r & BD7182x_MASK_DCIN_DET) != 0); 301 301 + *chg_online = ((r & pwr->regs->dcin_online_mask) != 0); 333 302 334 303 return 0; 335 304 } ··· 360 329 ret = val & BD7182x_MASK_CONF_PON; 361 330 362 331 if (ret) 363 363 - regmap_update_bits(pwr->regmap, pwr->regs->conf, 364 364 - BD7182x_MASK_CONF_PON, 0); 332 332 + if (regmap_update_bits(pwr->regmap, pwr->regs->conf, BD7182x_MASK_CONF_PON, 0)) 333 333 + dev_err(pwr->dev, "Failed to write CONF register\n"); 365 334 366 335 return ret; 367 336 } ··· 389 358 int ret; 390 359 391 360 /* TODO: Collapse limit should come from device-tree ? */ 392 392 - ret = regmap_write(pwr->regmap, pwr->regs->dcin_collapse_limit, 393 393 - BD7182x_DCIN_COLLAPSE_DEFAULT); 394 394 - if (ret) { 395 395 - dev_err(pwr->dev, "Failed to write DCIN collapse limit\n"); 396 396 - return ret; 361 361 + if (pwr->regs->dcin_collapse_limit != (unsigned int)-1) { 362 362 + ret = regmap_write(pwr->regmap, pwr->regs->dcin_collapse_limit, 363 363 + BD7182x_DCIN_COLLAPSE_DEFAULT); 364 364 + if (ret) { 365 365 + dev_err(pwr->dev, "Failed to write DCIN collapse limit\n"); 366 366 + return ret; 367 367 + } 397 368 } 398 369 399 370 ret = pwr->bat_inserted(pwr); ··· 452 419 break; 453 420 case POWER_SUPPLY_PROP_VOLTAGE_NOW: 454 421 ret = bd7182x_read16_himask(pwr, pwr->regs->vdcin, 455 455 - BD7182x_MASK_VDCIN_U, &tmp); 422 422 + pwr->regs->vdcin_himask, &tmp); 456 423 if (ret) 457 424 return ret; 458 425 ··· 663 630 BD_ISR_DUMMY(dcin_mon_det, "DCIN voltage below threshold") 664 631 BD_ISR_DUMMY(dcin_mon_res, "DCIN voltage above threshold") 665 632 633 633 + BD_ISR_DUMMY(vbus_curr_limit, "VBUS current limited") 634 634 + BD_ISR_DUMMY(vsys_ov_res, "VSYS over-voltage cleared") 635 635 + BD_ISR_DUMMY(vsys_ov_det, "VSYS over-voltage") 666 636 BD_ISR_DUMMY(vsys_uv_res, "VSYS under-voltage cleared") 667 637 BD_ISR_DUMMY(vsys_uv_det, "VSYS under-voltage") 668 638 BD_ISR_DUMMY(vsys_low_res, "'VSYS low' cleared") ··· 914 878 BDIRQ("bd71828-temp-125-over", bd71828_temp_vf125_det), 915 879 BDIRQ("bd71828-temp-125-under", bd71828_temp_vf125_res), 916 880 }; 881 881 + static const struct bd7182x_irq_res bd72720_irqs[] = { 882 882 + BDIRQ("bd72720_int_vbus_rmv", BD_ISR_NAME(dcin_removed)), 883 883 + BDIRQ("bd72720_int_vbus_det", bd7182x_dcin_detected), 884 884 + BDIRQ("bd72720_int_vbus_mon_res", BD_ISR_NAME(dcin_mon_res)), 885 885 + BDIRQ("bd72720_int_vbus_mon_det", BD_ISR_NAME(dcin_mon_det)), 886 886 + BDIRQ("bd72720_int_vsys_mon_res", BD_ISR_NAME(vsys_mon_res)), 887 887 + BDIRQ("bd72720_int_vsys_mon_det", BD_ISR_NAME(vsys_mon_det)), 888 888 + BDIRQ("bd72720_int_vsys_uv_res", BD_ISR_NAME(vsys_uv_res)), 889 889 + BDIRQ("bd72720_int_vsys_uv_det", BD_ISR_NAME(vsys_uv_det)), 890 890 + BDIRQ("bd72720_int_vsys_lo_res", BD_ISR_NAME(vsys_low_res)), 891 891 + BDIRQ("bd72720_int_vsys_lo_det", BD_ISR_NAME(vsys_low_det)), 892 892 + BDIRQ("bd72720_int_vsys_ov_res", BD_ISR_NAME(vsys_ov_res)), 893 893 + BDIRQ("bd72720_int_vsys_ov_det", BD_ISR_NAME(vsys_ov_det)), 894 894 + BDIRQ("bd72720_int_bat_ilim", BD_ISR_NAME(vbus_curr_limit)), 895 895 + BDIRQ("bd72720_int_chg_done", bd718x7_chg_done), 896 896 + BDIRQ("bd72720_int_extemp_tout", BD_ISR_NAME(chg_wdg_temp)), 897 897 + BDIRQ("bd72720_int_chg_wdt_exp", BD_ISR_NAME(chg_wdg)), 898 898 + BDIRQ("bd72720_int_bat_mnt_out", BD_ISR_NAME(rechg_res)), 899 899 + BDIRQ("bd72720_int_bat_mnt_in", BD_ISR_NAME(rechg_det)), 900 900 + BDIRQ("bd72720_int_chg_trns", BD_ISR_NAME(chg_state_changed)), 901 901 + 902 902 + BDIRQ("bd72720_int_vbat_mon_res", BD_ISR_NAME(bat_mon_res)), 903 903 + BDIRQ("bd72720_int_vbat_mon_det", BD_ISR_NAME(bat_mon)), 904 904 + BDIRQ("bd72720_int_vbat_sht_res", BD_ISR_NAME(bat_short_res)), 905 905 + BDIRQ("bd72720_int_vbat_sht_det", BD_ISR_NAME(bat_short)), 906 906 + BDIRQ("bd72720_int_vbat_lo_res", BD_ISR_NAME(bat_low_res)), 907 907 + BDIRQ("bd72720_int_vbat_lo_det", BD_ISR_NAME(bat_low)), 908 908 + BDIRQ("bd72720_int_vbat_ov_res", BD_ISR_NAME(bat_ov_res)), 909 909 + BDIRQ("bd72720_int_vbat_ov_det", BD_ISR_NAME(bat_ov)), 910 910 + BDIRQ("bd72720_int_bat_rmv", BD_ISR_NAME(bat_removed)), 911 911 + BDIRQ("bd72720_int_bat_det", BD_ISR_NAME(bat_det)), 912 912 + BDIRQ("bd72720_int_dbat_det", BD_ISR_NAME(bat_dead)), 913 913 + BDIRQ("bd72720_int_bat_temp_trns", BD_ISR_NAME(temp_transit)), 914 914 + BDIRQ("bd72720_int_lobtmp_res", BD_ISR_NAME(temp_bat_low_res)), 915 915 + BDIRQ("bd72720_int_lobtmp_det", BD_ISR_NAME(temp_bat_low)), 916 916 + BDIRQ("bd72720_int_ovbtmp_res", BD_ISR_NAME(temp_bat_hi_res)), 917 917 + BDIRQ("bd72720_int_ovbtmp_det", BD_ISR_NAME(temp_bat_hi)), 918 918 + BDIRQ("bd72720_int_ocur1_res", BD_ISR_NAME(bat_oc1_res)), 919 919 + BDIRQ("bd72720_int_ocur1_det", BD_ISR_NAME(bat_oc1)), 920 920 + BDIRQ("bd72720_int_ocur2_res", BD_ISR_NAME(bat_oc2_res)), 921 921 + BDIRQ("bd72720_int_ocur2_det", BD_ISR_NAME(bat_oc2)), 922 922 + BDIRQ("bd72720_int_ocur3_res", BD_ISR_NAME(bat_oc3_res)), 923 923 + BDIRQ("bd72720_int_ocur3_det", BD_ISR_NAME(bat_oc3)), 924 924 + BDIRQ("bd72720_int_cc_mon2_det", BD_ISR_NAME(bat_cc_mon)), 925 925 + }; 917 926 int num_irqs; 918 927 const struct bd7182x_irq_res *irqs; 919 928 ··· 970 889 case ROHM_CHIP_TYPE_BD71815: 971 890 irqs = &bd71815_irqs[0]; 972 891 num_irqs = ARRAY_SIZE(bd71815_irqs); 892 892 + break; 893 893 + case ROHM_CHIP_TYPE_BD72720: 894 894 + irqs = &bd72720_irqs[0]; 895 895 + num_irqs = ARRAY_SIZE(bd72720_irqs); 973 896 break; 974 897 default: 975 898 return -EINVAL; ··· 1043 958 struct power_supply_config ac_cfg = {}; 1044 959 struct power_supply_config bat_cfg = {}; 1045 960 int ret; 1046 1046 - struct regmap *regmap; 1047 1047 - 1048 1048 - regmap = dev_get_regmap(pdev->dev.parent, NULL); 1049 1049 - if (!regmap) { 1050 1050 - dev_err(&pdev->dev, "No parent regmap\n"); 1051 1051 - return -EINVAL; 1052 1052 - } 1053 961 1054 962 pwr = devm_kzalloc(&pdev->dev, sizeof(*pwr), GFP_KERNEL); 1055 963 if (!pwr) 1056 964 return -ENOMEM; 1057 965 1058 1058 - pwr->regmap = regmap; 1059 1059 - pwr->dev = &pdev->dev; 966 966 + /* 967 967 + * The BD72720 MFD device registers two regmaps. Power-supply driver 968 968 + * uses the "wrap-map", which provides access to both of the I2C slave 969 969 + * addresses used by the BD72720 970 970 + */ 1060 971 pwr->chip_type = platform_get_device_id(pdev)->driver_data; 972 972 + if (pwr->chip_type != ROHM_CHIP_TYPE_BD72720) 973 973 + pwr->regmap = dev_get_regmap(pdev->dev.parent, NULL); 974 974 + else 975 975 + pwr->regmap = dev_get_regmap(pdev->dev.parent, "wrap-map"); 976 976 + if (!pwr->regmap) { 977 977 + dev_err(&pdev->dev, "No parent regmap\n"); 978 978 + return -EINVAL; 979 979 + } 980 980 + 981 981 + pwr->dev = &pdev->dev; 1061 982 1062 983 switch (pwr->chip_type) { 1063 984 case ROHM_CHIP_TYPE_BD71828: ··· 1075 984 pwr->bat_inserted = bd71815_bat_inserted; 1076 985 pwr->get_temp = bd71815_get_temp; 1077 986 pwr->regs = &pwr_regs_bd71815; 987 987 + break; 988 988 + case ROHM_CHIP_TYPE_BD72720: 989 989 + pwr->bat_inserted = bd71828_bat_inserted; 990 990 + pwr->regs = &pwr_regs_bd72720; 991 991 + pwr->get_temp = bd71828_get_temp; 992 992 + dev_dbg(pwr->dev, "Found ROHM BD72720\n"); 1078 993 break; 1079 994 default: 1080 995 dev_err(pwr->dev, "Unknown PMIC\n"); ··· 1127 1030 static const struct platform_device_id bd71828_charger_id[] = { 1128 1031 { "bd71815-power", ROHM_CHIP_TYPE_BD71815 }, 1129 1032 { "bd71828-power", ROHM_CHIP_TYPE_BD71828 }, 1033 1033 + { "bd72720-power", ROHM_CHIP_TYPE_BD72720 }, 1130 1034 { }, 1131 1035 }; 1132 1036 MODULE_DEVICE_TABLE(platform, bd71828_charger_id);

+4 -4

drivers/regulator/Kconfig

reviewed

··· 241 241 will be called bd71815-regulator. 242 242 243 243 config REGULATOR_BD71828 244 244 - tristate "ROHM BD71828 Power Regulator" 244 244 + tristate "ROHM BD71828, BD72720 and BD73900 Power Regulators" 245 245 depends on MFD_ROHM_BD71828 246 246 select REGULATOR_ROHM 247 247 help 248 248 - This driver supports voltage regulators on ROHM BD71828 PMIC. 249 249 - This will enable support for the software controllable buck 250 250 - and LDO regulators. 248 248 + This driver supports voltage regulators on ROHM BD71828, 249 249 + BD71879, BD72720 and BD73900 PMICs. This will enable 250 250 + support for the software controllable buck and LDO regulators. 251 251 252 252 This driver can also be built as a module. If so, the module 253 253 will be called bd71828-regulator.

+6 -9

drivers/regulator/bd71815-regulator.c

reviewed

··· 571 571 return -ENODEV; 572 572 } 573 573 574 574 - ldo4_en = devm_fwnode_gpiod_get(&pdev->dev, 575 575 - dev_fwnode(pdev->dev.parent), 576 576 - "rohm,vsel", GPIOD_ASIS, "ldo4-en"); 577 577 - if (IS_ERR(ldo4_en)) { 578 578 - ret = PTR_ERR(ldo4_en); 579 579 - if (ret != -ENOENT) 580 580 - return ret; 581 581 - ldo4_en = NULL; 582 582 - } 574 574 + ldo4_en = devm_fwnode_gpiod_get_optional(&pdev->dev, 575 575 + dev_fwnode(pdev->dev.parent), 576 576 + "rohm,vsel", GPIOD_ASIS, 577 577 + "ldo4-en"); 578 578 + if (IS_ERR(ldo4_en)) 579 579 + return PTR_ERR(ldo4_en); 583 580 584 581 /* Disable to go to ship-mode */ 585 582 ret = regmap_update_bits(regmap, BD71815_REG_PWRCTRL, RESTARTEN, 0);

+1005 -22

drivers/regulator/bd71828-regulator.c

reviewed

··· 3 3 // bd71828-regulator.c ROHM BD71828GW-DS1 regulator driver 4 4 // 5 5 6 6 + #include <linux/cleanup.h> 6 7 #include <linux/delay.h> 7 8 #include <linux/err.h> 8 9 #include <linux/interrupt.h> 9 10 #include <linux/kernel.h> 10 11 #include <linux/mfd/rohm-bd71828.h> 12 12 + #include <linux/mfd/rohm-bd72720.h> 11 13 #include <linux/module.h> 14 14 + #include <linux/mod_devicetable.h> 12 15 #include <linux/of.h> 13 16 #include <linux/platform_device.h> 14 17 #include <linux/regmap.h> ··· 19 16 #include <linux/regulator/machine.h> 20 17 #include <linux/regulator/of_regulator.h> 21 18 19 19 + #define BD72720_MASK_LDON_HEAD GENMASK(2, 0) 22 20 struct reg_init { 23 21 unsigned int reg; 24 22 unsigned int mask; ··· 32 28 int reg_init_amnt; 33 29 }; 34 30 35 35 - static const struct reg_init buck1_inits[] = { 31 31 + static const struct reg_init bd71828_buck1_inits[] = { 36 32 /* 37 33 * DVS Buck voltages can be changed by register values or via GPIO. 38 34 * Use register accesses by default. ··· 44 40 }, 45 41 }; 46 42 47 47 - static const struct reg_init buck2_inits[] = { 43 43 + static const struct reg_init bd71828_buck2_inits[] = { 48 44 { 49 45 .reg = BD71828_REG_PS_CTRL_1, 50 46 .mask = BD71828_MASK_DVS_BUCK2_CTRL, ··· 52 48 }, 53 49 }; 54 50 55 55 - static const struct reg_init buck6_inits[] = { 51 51 + static const struct reg_init bd71828_buck6_inits[] = { 56 52 { 57 53 .reg = BD71828_REG_PS_CTRL_1, 58 54 .mask = BD71828_MASK_DVS_BUCK6_CTRL, ··· 60 56 }, 61 57 }; 62 58 63 63 - static const struct reg_init buck7_inits[] = { 59 59 + static const struct reg_init bd71828_buck7_inits[] = { 64 60 { 65 61 .reg = BD71828_REG_PS_CTRL_1, 66 62 .mask = BD71828_MASK_DVS_BUCK7_CTRL, ··· 68 64 }, 69 65 }; 70 66 67 67 + #define BD72720_MASK_DVS_BUCK1_CTRL BIT(4) 68 68 + #define BD72720_MASK_DVS_LDO1_CTRL BIT(5) 69 69 + 70 70 + static const struct reg_init bd72720_buck1_inits[] = { 71 71 + { 72 72 + .reg = BD72720_REG_PS_CTRL_2, 73 73 + .mask = BD72720_MASK_DVS_BUCK1_CTRL, 74 74 + .val = 0, /* Disable "run-level" control */ 75 75 + }, 76 76 + }; 77 77 + 78 78 + static const struct reg_init bd72720_ldo1_inits[] = { 79 79 + { 80 80 + .reg = BD72720_REG_PS_CTRL_2, 81 81 + .mask = BD72720_MASK_DVS_LDO1_CTRL, 82 82 + .val = 0, /* Disable "run-level" control */ 83 83 + }, 84 84 + }; 85 85 + 86 86 + /* BD71828 Buck voltages */ 71 87 static const struct linear_range bd71828_buck1267_volts[] = { 72 88 REGULATOR_LINEAR_RANGE(500000, 0x00, 0xef, 6250), 73 89 REGULATOR_LINEAR_RANGE(2000000, 0xf0, 0xff, 0), ··· 108 84 REGULATOR_LINEAR_RANGE(3300000, 0x10, 0x1f, 0), 109 85 }; 110 86 87 87 + /* BD71828 LDO voltages */ 111 88 static const struct linear_range bd71828_ldo_volts[] = { 112 89 REGULATOR_LINEAR_RANGE(800000, 0x00, 0x31, 50000), 113 90 REGULATOR_LINEAR_RANGE(3300000, 0x32, 0x3f, 0), 114 91 }; 115 92 93 93 + /* BD72720 Buck voltages */ 94 94 + static const struct linear_range bd72720_buck1234_volts[] = { 95 95 + REGULATOR_LINEAR_RANGE(500000, 0x00, 0xc0, 6250), 96 96 + REGULATOR_LINEAR_RANGE(1700000, 0xc1, 0xff, 0), 97 97 + }; 98 98 + 99 99 + static const struct linear_range bd72720_buck589_volts[] = { 100 100 + REGULATOR_LINEAR_RANGE(500000, 0x00, 0x78, 10000), 101 101 + REGULATOR_LINEAR_RANGE(1700000, 0x79, 0xff, 0), 102 102 + }; 103 103 + 104 104 + static const struct linear_range bd72720_buck67_volts[] = { 105 105 + REGULATOR_LINEAR_RANGE(1500000, 0x00, 0xb4, 10000), 106 106 + REGULATOR_LINEAR_RANGE(3300000, 0xb5, 0xff, 0), 107 107 + }; 108 108 + 109 109 + /* 110 110 + * The BUCK10 on BD72720 has two modes of operation, depending on a LDON_HEAD 111 111 + * setting. When LDON_HEAD is 0x0, the behaviour is as with other bucks, eg. 112 112 + * voltage can be set to a values indicated below using the VSEL register. 113 113 + * 114 114 + * However, when LDON_HEAD is set to 0x1 ... 0x7, BUCK 10 voltage is, according 115 115 + * to the data-sheet, "automatically adjusted following LDON_HEAD setting and 116 116 + * clamped to BUCK10_VID setting". 117 117 + * 118 118 + * Again, reading the data-sheet shows a "typical connection" where the BUCK10 119 119 + * is used to supply the LDOs 1-4. My assumption is that in practice, this 120 120 + * means that the BUCK10 voltage will be adjusted based on the maximum output 121 121 + * of the LDO 1-4 (to minimize power loss). This makes sense. 122 122 + * 123 123 + * Auto-adjusting regulators aren't something I really like to model in the 124 124 + * driver though - and, if the auto-adjustment works as intended, then there 125 125 + * should really be no need to software to care about the buck10 voltages. 126 126 + * If enable/disable control is still needed, we can implement buck10 as a 127 127 + * regulator with only the enable/disable ops - and device-tree can be used 128 128 + * to model the supply-relations. I believe this could allow the regulator 129 129 + * framework to automagically disable the BUCK10 if all LDOs that are being 130 130 + * supplied by it are disabled. 131 131 + */ 132 132 + static const struct linear_range bd72720_buck10_volts[] = { 133 133 + REGULATOR_LINEAR_RANGE(500000, 0x00, 0xc0, 6250), 134 134 + REGULATOR_LINEAR_RANGE(1700000, 0xc1, 0xff, 0), 135 135 + }; 136 136 + 137 137 + /* BD72720 LDO voltages */ 138 138 + static const struct linear_range bd72720_ldo1234_volts[] = { 139 139 + REGULATOR_LINEAR_RANGE(500000, 0x00, 0x50, 6250), 140 140 + REGULATOR_LINEAR_RANGE(1000000, 0x51, 0x7f, 0), 141 141 + }; 142 142 + 143 143 + static const struct linear_range bd72720_ldo57891011_volts[] = { 144 144 + REGULATOR_LINEAR_RANGE(750000, 0x00, 0xff, 10000), 145 145 + }; 146 146 + 147 147 + static const struct linear_range bd72720_ldo6_volts[] = { 148 148 + REGULATOR_LINEAR_RANGE(600000, 0x00, 0x78, 10000), 149 149 + REGULATOR_LINEAR_RANGE(1800000, 0x79, 0x7f, 0), 150 150 + }; 151 151 + 116 152 static const unsigned int bd71828_ramp_delay[] = { 2500, 5000, 10000, 20000 }; 153 153 + 154 154 + /* 155 155 + * BD72720 supports setting both the ramp-up and ramp-down values 156 156 + * separately. Do we need to support ramp-down setting? 157 157 + */ 158 158 + static const unsigned int bd72720_ramp_delay[] = { 5000, 7500, 10000, 12500 }; 117 159 118 160 static int buck_set_hw_dvs_levels(struct device_node *np, 119 161 const struct regulator_desc *desc, ··· 192 102 return rohm_regulator_set_dvs_levels(&data->dvs, np, desc, cfg->regmap); 193 103 } 194 104 195 195 - static int ldo6_parse_dt(struct device_node *np, 196 196 - const struct regulator_desc *desc, 197 197 - struct regulator_config *cfg) 105 105 + static int bd71828_ldo6_parse_dt(struct device_node *np, 106 106 + const struct regulator_desc *desc, 107 107 + struct regulator_config *cfg) 198 108 { 199 109 int ret, i; 200 110 uint32_t uv = 0; ··· 261 171 .is_enabled = regulator_is_enabled_regmap, 262 172 }; 263 173 174 174 + static const struct regulator_ops bd72720_regulator_ops = { 175 175 + .enable = regulator_enable_regmap, 176 176 + .disable = regulator_disable_regmap, 177 177 + .is_enabled = regulator_is_enabled_regmap, 178 178 + .list_voltage = regulator_list_voltage_linear_range, 179 179 + .set_voltage_sel = regulator_set_voltage_sel_regmap, 180 180 + .get_voltage_sel = regulator_get_voltage_sel_regmap, 181 181 + .set_voltage_time_sel = regulator_set_voltage_time_sel, 182 182 + .set_ramp_delay = regulator_set_ramp_delay_regmap, 183 183 + }; 184 184 + 185 185 + static const struct regulator_ops bd72720_buck10_ldon_head_op = { 186 186 + .enable = regulator_enable_regmap, 187 187 + .disable = regulator_disable_regmap, 188 188 + .is_enabled = regulator_is_enabled_regmap, 189 189 + .set_ramp_delay = regulator_set_ramp_delay_regmap, 190 190 + }; 191 191 + 264 192 static const struct bd71828_regulator_data bd71828_rdata[] = { 265 193 { 266 194 .desc = { ··· 320 212 */ 321 213 .lpsr_on_mask = BD71828_MASK_LPSR_EN, 322 214 }, 323 323 - .reg_inits = buck1_inits, 324 324 - .reg_init_amnt = ARRAY_SIZE(buck1_inits), 215 215 + .reg_inits = bd71828_buck1_inits, 216 216 + .reg_init_amnt = ARRAY_SIZE(bd71828_buck1_inits), 325 217 }, 326 218 { 327 219 .desc = { ··· 361 253 .lpsr_reg = BD71828_REG_BUCK2_SUSP_VOLT, 362 254 .lpsr_mask = BD71828_MASK_BUCK1267_VOLT, 363 255 }, 364 364 - .reg_inits = buck2_inits, 365 365 - .reg_init_amnt = ARRAY_SIZE(buck2_inits), 256 256 + .reg_inits = bd71828_buck2_inits, 257 257 + .reg_init_amnt = ARRAY_SIZE(bd71828_buck2_inits), 366 258 }, 367 259 { 368 260 .desc = { ··· 507 399 .lpsr_reg = BD71828_REG_BUCK6_SUSP_VOLT, 508 400 .lpsr_mask = BD71828_MASK_BUCK1267_VOLT, 509 401 }, 510 510 - .reg_inits = buck6_inits, 511 511 - .reg_init_amnt = ARRAY_SIZE(buck6_inits), 402 402 + .reg_inits = bd71828_buck6_inits, 403 403 + .reg_init_amnt = ARRAY_SIZE(bd71828_buck6_inits), 512 404 }, 513 405 { 514 406 .desc = { ··· 548 440 .lpsr_reg = BD71828_REG_BUCK7_SUSP_VOLT, 549 441 .lpsr_mask = BD71828_MASK_BUCK1267_VOLT, 550 442 }, 551 551 - .reg_inits = buck7_inits, 552 552 - .reg_init_amnt = ARRAY_SIZE(buck7_inits), 443 443 + .reg_inits = bd71828_buck7_inits, 444 444 + .reg_init_amnt = ARRAY_SIZE(bd71828_buck7_inits), 553 445 }, 554 446 { 555 447 .desc = { ··· 741 633 * LDO6 only supports enable/disable for all states. 742 634 * Voltage for LDO6 is fixed. 743 635 */ 744 744 - .of_parse_cb = ldo6_parse_dt, 636 636 + .of_parse_cb = bd71828_ldo6_parse_dt, 745 637 }, 746 638 }, { 747 639 .desc = { ··· 785 677 }, 786 678 }; 787 679 680 680 + #define BD72720_BUCK10_DESC_INDEX 10 681 681 + #define BD72720_NUM_BUCK_VOLTS 0x100 682 682 + #define BD72720_NUM_LDO_VOLTS 0x100 683 683 + #define BD72720_NUM_LDO12346_VOLTS 0x80 684 684 + 685 685 + static const struct bd71828_regulator_data bd72720_rdata[] = { 686 686 + { 687 687 + .desc = { 688 688 + .name = "buck1", 689 689 + .of_match = of_match_ptr("buck1"), 690 690 + .regulators_node = of_match_ptr("regulators"), 691 691 + .id = BD72720_BUCK1, 692 692 + .type = REGULATOR_VOLTAGE, 693 693 + 694 694 + /* 695 695 + * The BD72720 BUCK1 and LDO1 support GPIO toggled 696 696 + * sub-RUN states called RUN0, RUN1, RUN2 and RUN3. 697 697 + * The "operating mode" (sub-RUN states or normal) 698 698 + * can be changed by a register. 699 699 + * 700 700 + * When the sub-RUN states are used, the voltage and 701 701 + * enable state depend on a state specific 702 702 + * configuration. The voltage and enable configuration 703 703 + * for BUCK1 and LDO1 can be defined for each sub-RUN 704 704 + * state using BD72720_REG_[BUCK,LDO]1_VSEL_R[0,1,2,3] 705 705 + * voltage selection registers and the bits 706 706 + * BD72720_MASK_RUN_[0,1,2,3]_EN in the enable registers. 707 707 + * The PMIC will change both the BUCK1 and LDO1 voltages 708 708 + * to the states defined in these registers when 709 709 + * "DVS GPIOs" are toggled. 710 710 + * 711 711 + * If RUN 0 .. RUN 4 states are to be used, the normal 712 712 + * voltage configuration mechanisms do not apply 713 713 + * and we should overwrite the ops and ignore the 714 714 + * voltage setting/getting registers which are setup 715 715 + * here. This is not supported for now. If you need 716 716 + * this functionality, you may try merging functionality 717 717 + * from a downstream driver: 718 718 + * https://rohmsemiconductor.github.io/Linux-Kernel-PMIC-Drivers/BD72720/ 719 719 + */ 720 720 + .ops = &bd72720_regulator_ops, 721 721 + .linear_ranges = bd72720_buck1234_volts, 722 722 + .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts), 723 723 + .n_voltages = BD72720_NUM_BUCK_VOLTS, 724 724 + .enable_reg = BD72720_REG_BUCK1_ON, 725 725 + .enable_mask = BD72720_MASK_RUN_B_EN, 726 726 + .vsel_reg = BD72720_REG_BUCK1_VSEL_RB, 727 727 + .vsel_mask = BD72720_MASK_BUCK_VSEL, 728 728 + 729 729 + .ramp_delay_table = bd72720_ramp_delay, 730 730 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 731 731 + .ramp_reg = BD72720_REG_BUCK1_MODE, 732 732 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 733 733 + .owner = THIS_MODULE, 734 734 + .of_parse_cb = buck_set_hw_dvs_levels, 735 735 + }, 736 736 + .dvs = { 737 737 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 738 738 + ROHM_DVS_LEVEL_SUSPEND | 739 739 + ROHM_DVS_LEVEL_LPSR, /* Deep idle in data-sheet */ 740 740 + .run_reg = BD72720_REG_BUCK1_VSEL_RB, 741 741 + .run_mask = BD72720_MASK_BUCK_VSEL, 742 742 + .idle_reg = BD72720_REG_BUCK1_VSEL_I, 743 743 + .idle_mask = BD72720_MASK_BUCK_VSEL, 744 744 + .idle_on_mask = BD72720_MASK_IDLE_EN, 745 745 + .suspend_reg = BD72720_REG_BUCK1_VSEL_S, 746 746 + .suspend_mask = BD72720_MASK_BUCK_VSEL, 747 747 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 748 748 + .lpsr_reg = BD72720_REG_BUCK1_VSEL_DI, 749 749 + .lpsr_mask = BD72720_MASK_BUCK_VSEL, 750 750 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 751 751 + }, 752 752 + .reg_inits = bd72720_buck1_inits, 753 753 + .reg_init_amnt = ARRAY_SIZE(bd72720_buck1_inits), 754 754 + }, { 755 755 + .desc = { 756 756 + .name = "buck2", 757 757 + .of_match = of_match_ptr("buck2"), 758 758 + .regulators_node = of_match_ptr("regulators"), 759 759 + .id = BD72720_BUCK2, 760 760 + .type = REGULATOR_VOLTAGE, 761 761 + .ops = &bd72720_regulator_ops, 762 762 + .linear_ranges = bd72720_buck1234_volts, 763 763 + .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts), 764 764 + .n_voltages = BD72720_NUM_BUCK_VOLTS, 765 765 + .enable_reg = BD72720_REG_BUCK2_ON, 766 766 + .enable_mask = BD72720_MASK_RUN_B_EN, 767 767 + .vsel_reg = BD72720_REG_BUCK2_VSEL_R, 768 768 + .vsel_mask = BD72720_MASK_BUCK_VSEL, 769 769 + 770 770 + .ramp_delay_table = bd72720_ramp_delay, 771 771 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 772 772 + .ramp_reg = BD72720_REG_BUCK2_MODE, 773 773 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 774 774 + .owner = THIS_MODULE, 775 775 + .of_parse_cb = buck_set_hw_dvs_levels, 776 776 + }, 777 777 + .dvs = { 778 778 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 779 779 + ROHM_DVS_LEVEL_SUSPEND | 780 780 + ROHM_DVS_LEVEL_LPSR, 781 781 + .run_reg = BD72720_REG_BUCK2_VSEL_R, 782 782 + .run_mask = BD72720_MASK_BUCK_VSEL, 783 783 + .idle_reg = BD72720_REG_BUCK2_VSEL_I, 784 784 + .idle_mask = BD72720_MASK_BUCK_VSEL, 785 785 + .idle_on_mask = BD72720_MASK_IDLE_EN, 786 786 + .suspend_reg = BD72720_REG_BUCK2_VSEL_S, 787 787 + .suspend_mask = BD72720_MASK_BUCK_VSEL, 788 788 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 789 789 + .lpsr_reg = BD72720_REG_BUCK2_VSEL_DI, 790 790 + .lpsr_mask = BD72720_MASK_BUCK_VSEL, 791 791 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 792 792 + }, 793 793 + }, { 794 794 + .desc = { 795 795 + .name = "buck3", 796 796 + .of_match = of_match_ptr("buck3"), 797 797 + .regulators_node = of_match_ptr("regulators"), 798 798 + .id = BD72720_BUCK3, 799 799 + .type = REGULATOR_VOLTAGE, 800 800 + .ops = &bd72720_regulator_ops, 801 801 + .linear_ranges = bd72720_buck1234_volts, 802 802 + .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts), 803 803 + .n_voltages = BD72720_NUM_BUCK_VOLTS, 804 804 + .enable_reg = BD72720_REG_BUCK3_ON, 805 805 + .enable_mask = BD72720_MASK_RUN_B_EN, 806 806 + .vsel_reg = BD72720_REG_BUCK3_VSEL_R, 807 807 + .vsel_mask = BD72720_MASK_BUCK_VSEL, 808 808 + 809 809 + .ramp_delay_table = bd72720_ramp_delay, 810 810 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 811 811 + .ramp_reg = BD72720_REG_BUCK3_MODE, 812 812 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 813 813 + .owner = THIS_MODULE, 814 814 + .of_parse_cb = buck_set_hw_dvs_levels, 815 815 + }, 816 816 + .dvs = { 817 817 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 818 818 + ROHM_DVS_LEVEL_SUSPEND | 819 819 + ROHM_DVS_LEVEL_LPSR, 820 820 + .run_reg = BD72720_REG_BUCK3_VSEL_R, 821 821 + .run_mask = BD72720_MASK_BUCK_VSEL, 822 822 + .idle_reg = BD72720_REG_BUCK3_VSEL_I, 823 823 + .idle_mask = BD72720_MASK_BUCK_VSEL, 824 824 + .idle_on_mask = BD72720_MASK_IDLE_EN, 825 825 + .suspend_reg = BD72720_REG_BUCK3_VSEL_S, 826 826 + .suspend_mask = BD72720_MASK_BUCK_VSEL, 827 827 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 828 828 + .lpsr_reg = BD72720_REG_BUCK3_VSEL_DI, 829 829 + .lpsr_mask = BD72720_MASK_BUCK_VSEL, 830 830 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 831 831 + }, 832 832 + }, { 833 833 + .desc = { 834 834 + .name = "buck4", 835 835 + .of_match = of_match_ptr("buck4"), 836 836 + .regulators_node = of_match_ptr("regulators"), 837 837 + .id = BD72720_BUCK4, 838 838 + .type = REGULATOR_VOLTAGE, 839 839 + .ops = &bd72720_regulator_ops, 840 840 + .linear_ranges = bd72720_buck1234_volts, 841 841 + .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts), 842 842 + .n_voltages = BD72720_NUM_BUCK_VOLTS, 843 843 + .enable_reg = BD72720_REG_BUCK4_ON, 844 844 + .enable_mask = BD72720_MASK_RUN_B_EN, 845 845 + .vsel_reg = BD72720_REG_BUCK4_VSEL_R, 846 846 + .vsel_mask = BD72720_MASK_BUCK_VSEL, 847 847 + 848 848 + .ramp_delay_table = bd72720_ramp_delay, 849 849 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 850 850 + .ramp_reg = BD72720_REG_BUCK4_MODE, 851 851 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 852 852 + .owner = THIS_MODULE, 853 853 + .of_parse_cb = buck_set_hw_dvs_levels, 854 854 + }, 855 855 + .dvs = { 856 856 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 857 857 + ROHM_DVS_LEVEL_SUSPEND | 858 858 + ROHM_DVS_LEVEL_LPSR, 859 859 + .run_reg = BD72720_REG_BUCK4_VSEL_R, 860 860 + .run_mask = BD72720_MASK_BUCK_VSEL, 861 861 + .idle_reg = BD72720_REG_BUCK4_VSEL_I, 862 862 + .idle_mask = BD72720_MASK_BUCK_VSEL, 863 863 + .idle_on_mask = BD72720_MASK_IDLE_EN, 864 864 + .suspend_reg = BD72720_REG_BUCK4_VSEL_S, 865 865 + .suspend_mask = BD72720_MASK_BUCK_VSEL, 866 866 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 867 867 + .lpsr_reg = BD72720_REG_BUCK4_VSEL_DI, 868 868 + .lpsr_mask = BD72720_MASK_BUCK_VSEL, 869 869 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 870 870 + }, 871 871 + }, { 872 872 + .desc = { 873 873 + .name = "buck5", 874 874 + .of_match = of_match_ptr("buck5"), 875 875 + .regulators_node = of_match_ptr("regulators"), 876 876 + .id = BD72720_BUCK5, 877 877 + .type = REGULATOR_VOLTAGE, 878 878 + .ops = &bd72720_regulator_ops, 879 879 + .linear_ranges = bd72720_buck589_volts, 880 880 + .n_linear_ranges = ARRAY_SIZE(bd72720_buck589_volts), 881 881 + .n_voltages = BD72720_NUM_BUCK_VOLTS, 882 882 + .enable_reg = BD72720_REG_BUCK5_ON, 883 883 + .enable_mask = BD72720_MASK_RUN_B_EN, 884 884 + .vsel_reg = BD72720_REG_BUCK5_VSEL, 885 885 + .vsel_mask = BD72720_MASK_BUCK_VSEL, 886 886 + 887 887 + .ramp_delay_table = bd72720_ramp_delay, 888 888 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 889 889 + .ramp_reg = BD72720_REG_BUCK5_MODE, 890 890 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 891 891 + .owner = THIS_MODULE, 892 892 + .of_parse_cb = buck_set_hw_dvs_levels, 893 893 + }, 894 894 + .dvs = { 895 895 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 896 896 + ROHM_DVS_LEVEL_SUSPEND | 897 897 + ROHM_DVS_LEVEL_LPSR, 898 898 + .run_reg = BD72720_REG_BUCK5_VSEL, 899 899 + .run_mask = BD72720_MASK_BUCK_VSEL, 900 900 + .idle_on_mask = BD72720_MASK_IDLE_EN, 901 901 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 902 902 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 903 903 + }, 904 904 + }, { 905 905 + .desc = { 906 906 + .name = "buck6", 907 907 + .of_match = of_match_ptr("buck6"), 908 908 + .regulators_node = of_match_ptr("regulators"), 909 909 + .id = BD72720_BUCK6, 910 910 + .type = REGULATOR_VOLTAGE, 911 911 + .ops = &bd72720_regulator_ops, 912 912 + .linear_ranges = bd72720_buck67_volts, 913 913 + .n_linear_ranges = ARRAY_SIZE(bd72720_buck67_volts), 914 914 + .n_voltages = BD72720_NUM_BUCK_VOLTS, 915 915 + .enable_reg = BD72720_REG_BUCK6_ON, 916 916 + .enable_mask = BD72720_MASK_RUN_B_EN, 917 917 + .vsel_reg = BD72720_REG_BUCK6_VSEL, 918 918 + .vsel_mask = BD72720_MASK_BUCK_VSEL, 919 919 + 920 920 + .ramp_delay_table = bd72720_ramp_delay, 921 921 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 922 922 + .ramp_reg = BD72720_REG_BUCK6_MODE, 923 923 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 924 924 + .owner = THIS_MODULE, 925 925 + .of_parse_cb = buck_set_hw_dvs_levels, 926 926 + }, 927 927 + .dvs = { 928 928 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 929 929 + ROHM_DVS_LEVEL_SUSPEND | 930 930 + ROHM_DVS_LEVEL_LPSR, 931 931 + .run_reg = BD72720_REG_BUCK6_VSEL, 932 932 + .run_mask = BD72720_MASK_BUCK_VSEL, 933 933 + .idle_on_mask = BD72720_MASK_IDLE_EN, 934 934 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 935 935 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 936 936 + }, 937 937 + }, { 938 938 + .desc = { 939 939 + .name = "buck7", 940 940 + .of_match = of_match_ptr("buck7"), 941 941 + .regulators_node = of_match_ptr("regulators"), 942 942 + .id = BD72720_BUCK7, 943 943 + .type = REGULATOR_VOLTAGE, 944 944 + .ops = &bd72720_regulator_ops, 945 945 + .linear_ranges = bd72720_buck67_volts, 946 946 + .n_linear_ranges = ARRAY_SIZE(bd72720_buck67_volts), 947 947 + .n_voltages = BD72720_NUM_BUCK_VOLTS, 948 948 + .enable_reg = BD72720_REG_BUCK7_ON, 949 949 + .enable_mask = BD72720_MASK_RUN_B_EN, 950 950 + .vsel_reg = BD72720_REG_BUCK7_VSEL, 951 951 + .vsel_mask = BD72720_MASK_BUCK_VSEL, 952 952 + 953 953 + .ramp_delay_table = bd72720_ramp_delay, 954 954 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 955 955 + .ramp_reg = BD72720_REG_BUCK7_MODE, 956 956 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 957 957 + .owner = THIS_MODULE, 958 958 + .of_parse_cb = buck_set_hw_dvs_levels, 959 959 + }, 960 960 + .dvs = { 961 961 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 962 962 + ROHM_DVS_LEVEL_SUSPEND | 963 963 + ROHM_DVS_LEVEL_LPSR, 964 964 + .run_reg = BD72720_REG_BUCK7_VSEL, 965 965 + .run_mask = BD72720_MASK_BUCK_VSEL, 966 966 + .idle_on_mask = BD72720_MASK_IDLE_EN, 967 967 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 968 968 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 969 969 + }, 970 970 + }, { 971 971 + .desc = { 972 972 + .name = "buck8", 973 973 + .of_match = of_match_ptr("buck8"), 974 974 + .regulators_node = of_match_ptr("regulators"), 975 975 + .id = BD72720_BUCK8, 976 976 + .type = REGULATOR_VOLTAGE, 977 977 + .ops = &bd72720_regulator_ops, 978 978 + .linear_ranges = bd72720_buck589_volts, 979 979 + .n_linear_ranges = ARRAY_SIZE(bd72720_buck589_volts), 980 980 + .n_voltages = BD72720_NUM_BUCK_VOLTS, 981 981 + .enable_reg = BD72720_REG_BUCK8_ON, 982 982 + .enable_mask = BD72720_MASK_RUN_B_EN, 983 983 + .vsel_reg = BD72720_REG_BUCK8_VSEL, 984 984 + .vsel_mask = BD72720_MASK_BUCK_VSEL, 985 985 + 986 986 + .ramp_delay_table = bd72720_ramp_delay, 987 987 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 988 988 + .ramp_reg = BD72720_REG_BUCK8_MODE, 989 989 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 990 990 + .owner = THIS_MODULE, 991 991 + .of_parse_cb = buck_set_hw_dvs_levels, 992 992 + }, 993 993 + .dvs = { 994 994 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 995 995 + ROHM_DVS_LEVEL_SUSPEND | 996 996 + ROHM_DVS_LEVEL_LPSR, 997 997 + .run_reg = BD72720_REG_BUCK8_VSEL, 998 998 + .run_mask = BD72720_MASK_BUCK_VSEL, 999 999 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1000 1000 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1001 1001 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1002 1002 + }, 1003 1003 + }, { 1004 1004 + .desc = { 1005 1005 + .name = "buck9", 1006 1006 + .of_match = of_match_ptr("buck9"), 1007 1007 + .regulators_node = of_match_ptr("regulators"), 1008 1008 + .id = BD72720_BUCK9, 1009 1009 + .type = REGULATOR_VOLTAGE, 1010 1010 + .ops = &bd72720_regulator_ops, 1011 1011 + .linear_ranges = bd72720_buck589_volts, 1012 1012 + .n_linear_ranges = ARRAY_SIZE(bd72720_buck589_volts), 1013 1013 + .n_voltages = BD72720_NUM_BUCK_VOLTS, 1014 1014 + .enable_reg = BD72720_REG_BUCK9_ON, 1015 1015 + .enable_mask = BD72720_MASK_RUN_B_EN, 1016 1016 + .vsel_reg = BD72720_REG_BUCK9_VSEL, 1017 1017 + .vsel_mask = BD72720_MASK_BUCK_VSEL, 1018 1018 + 1019 1019 + .ramp_delay_table = bd72720_ramp_delay, 1020 1020 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1021 1021 + .ramp_reg = BD72720_REG_BUCK9_MODE, 1022 1022 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1023 1023 + .owner = THIS_MODULE, 1024 1024 + .of_parse_cb = buck_set_hw_dvs_levels, 1025 1025 + }, 1026 1026 + .dvs = { 1027 1027 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1028 1028 + ROHM_DVS_LEVEL_SUSPEND | 1029 1029 + ROHM_DVS_LEVEL_LPSR, 1030 1030 + .run_reg = BD72720_REG_BUCK9_VSEL, 1031 1031 + .run_mask = BD72720_MASK_BUCK_VSEL, 1032 1032 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1033 1033 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1034 1034 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1035 1035 + }, 1036 1036 + }, { 1037 1037 + .desc = { 1038 1038 + .name = "buck10", 1039 1039 + .of_match = of_match_ptr("buck10"), 1040 1040 + .regulators_node = of_match_ptr("regulators"), 1041 1041 + .id = BD72720_BUCK10, 1042 1042 + .type = REGULATOR_VOLTAGE, 1043 1043 + .ops = &bd72720_regulator_ops, 1044 1044 + .linear_ranges = bd72720_buck10_volts, 1045 1045 + .n_linear_ranges = ARRAY_SIZE(bd72720_buck10_volts), 1046 1046 + .n_voltages = BD72720_NUM_BUCK_VOLTS, 1047 1047 + .enable_reg = BD72720_REG_BUCK10_ON, 1048 1048 + .enable_mask = BD72720_MASK_RUN_B_EN, 1049 1049 + .vsel_reg = BD72720_REG_BUCK10_VSEL, 1050 1050 + .vsel_mask = BD72720_MASK_BUCK_VSEL, 1051 1051 + 1052 1052 + .ramp_delay_table = bd72720_ramp_delay, 1053 1053 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1054 1054 + .ramp_reg = BD72720_REG_BUCK10_MODE, 1055 1055 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1056 1056 + .owner = THIS_MODULE, 1057 1057 + .of_parse_cb = buck_set_hw_dvs_levels, 1058 1058 + }, 1059 1059 + .dvs = { 1060 1060 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1061 1061 + ROHM_DVS_LEVEL_SUSPEND | 1062 1062 + ROHM_DVS_LEVEL_LPSR, 1063 1063 + .run_reg = BD72720_REG_BUCK10_VSEL, 1064 1064 + .run_mask = BD72720_MASK_BUCK_VSEL, 1065 1065 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1066 1066 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1067 1067 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1068 1068 + }, 1069 1069 + }, { 1070 1070 + .desc = { 1071 1071 + .name = "ldo1", 1072 1072 + .of_match = of_match_ptr("ldo1"), 1073 1073 + .regulators_node = of_match_ptr("regulators"), 1074 1074 + .id = BD72720_LDO1, 1075 1075 + .type = REGULATOR_VOLTAGE, 1076 1076 + .ops = &bd72720_regulator_ops, 1077 1077 + .linear_ranges = bd72720_ldo1234_volts, 1078 1078 + .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts), 1079 1079 + .n_voltages = BD72720_NUM_LDO12346_VOLTS, 1080 1080 + .enable_reg = BD72720_REG_LDO1_ON, 1081 1081 + .enable_mask = BD72720_MASK_RUN_B_EN, 1082 1082 + .vsel_reg = BD72720_REG_LDO1_VSEL_RB, 1083 1083 + .vsel_mask = BD72720_MASK_LDO12346_VSEL, 1084 1084 + 1085 1085 + .ramp_delay_table = bd72720_ramp_delay, 1086 1086 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1087 1087 + .ramp_reg = BD72720_REG_LDO1_MODE1, 1088 1088 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1089 1089 + .owner = THIS_MODULE, 1090 1090 + .of_parse_cb = buck_set_hw_dvs_levels, 1091 1091 + }, 1092 1092 + .dvs = { 1093 1093 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1094 1094 + ROHM_DVS_LEVEL_SUSPEND | 1095 1095 + ROHM_DVS_LEVEL_LPSR, 1096 1096 + .run_reg = BD72720_REG_LDO1_VSEL_RB, 1097 1097 + .run_mask = BD72720_MASK_LDO12346_VSEL, 1098 1098 + .idle_reg = BD72720_REG_LDO1_VSEL_I, 1099 1099 + .idle_mask = BD72720_MASK_LDO12346_VSEL, 1100 1100 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1101 1101 + .suspend_reg = BD72720_REG_LDO1_VSEL_S, 1102 1102 + .suspend_mask = BD72720_MASK_LDO12346_VSEL, 1103 1103 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1104 1104 + .lpsr_reg = BD72720_REG_LDO1_VSEL_DI, 1105 1105 + .lpsr_mask = BD72720_MASK_LDO12346_VSEL, 1106 1106 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1107 1107 + }, 1108 1108 + .reg_inits = bd72720_ldo1_inits, 1109 1109 + .reg_init_amnt = ARRAY_SIZE(bd72720_ldo1_inits), 1110 1110 + }, { 1111 1111 + .desc = { 1112 1112 + .name = "ldo2", 1113 1113 + .of_match = of_match_ptr("ldo2"), 1114 1114 + .regulators_node = of_match_ptr("regulators"), 1115 1115 + .id = BD72720_LDO2, 1116 1116 + .type = REGULATOR_VOLTAGE, 1117 1117 + .ops = &bd72720_regulator_ops, 1118 1118 + .linear_ranges = bd72720_ldo1234_volts, 1119 1119 + .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts), 1120 1120 + .n_voltages = BD72720_NUM_LDO12346_VOLTS, 1121 1121 + .enable_reg = BD72720_REG_LDO2_ON, 1122 1122 + .enable_mask = BD72720_MASK_RUN_B_EN, 1123 1123 + .vsel_reg = BD72720_REG_LDO2_VSEL_R, 1124 1124 + .vsel_mask = BD72720_MASK_LDO12346_VSEL, 1125 1125 + 1126 1126 + .ramp_delay_table = bd72720_ramp_delay, 1127 1127 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1128 1128 + .ramp_reg = BD72720_REG_LDO2_MODE, 1129 1129 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1130 1130 + .owner = THIS_MODULE, 1131 1131 + .of_parse_cb = buck_set_hw_dvs_levels, 1132 1132 + }, 1133 1133 + .dvs = { 1134 1134 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1135 1135 + ROHM_DVS_LEVEL_SUSPEND | 1136 1136 + ROHM_DVS_LEVEL_LPSR, 1137 1137 + .run_reg = BD72720_REG_LDO2_VSEL_R, 1138 1138 + .run_mask = BD72720_MASK_LDO12346_VSEL, 1139 1139 + .idle_reg = BD72720_REG_LDO2_VSEL_I, 1140 1140 + .idle_mask = BD72720_MASK_LDO12346_VSEL, 1141 1141 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1142 1142 + .suspend_reg = BD72720_REG_LDO2_VSEL_S, 1143 1143 + .suspend_mask = BD72720_MASK_LDO12346_VSEL, 1144 1144 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1145 1145 + .lpsr_reg = BD72720_REG_LDO2_VSEL_DI, 1146 1146 + .lpsr_mask = BD72720_MASK_LDO12346_VSEL, 1147 1147 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1148 1148 + }, 1149 1149 + }, { 1150 1150 + .desc = { 1151 1151 + .name = "ldo3", 1152 1152 + .of_match = of_match_ptr("ldo3"), 1153 1153 + .regulators_node = of_match_ptr("regulators"), 1154 1154 + .id = BD72720_LDO3, 1155 1155 + .type = REGULATOR_VOLTAGE, 1156 1156 + .ops = &bd72720_regulator_ops, 1157 1157 + .linear_ranges = bd72720_ldo1234_volts, 1158 1158 + .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts), 1159 1159 + .n_voltages = BD72720_NUM_LDO12346_VOLTS, 1160 1160 + .enable_reg = BD72720_REG_LDO3_ON, 1161 1161 + .enable_mask = BD72720_MASK_RUN_B_EN, 1162 1162 + .vsel_reg = BD72720_REG_LDO3_VSEL_R, 1163 1163 + .vsel_mask = BD72720_MASK_LDO12346_VSEL, 1164 1164 + 1165 1165 + .ramp_delay_table = bd72720_ramp_delay, 1166 1166 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1167 1167 + .ramp_reg = BD72720_REG_LDO3_MODE, 1168 1168 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1169 1169 + .owner = THIS_MODULE, 1170 1170 + .of_parse_cb = buck_set_hw_dvs_levels, 1171 1171 + }, 1172 1172 + .dvs = { 1173 1173 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1174 1174 + ROHM_DVS_LEVEL_SUSPEND | 1175 1175 + ROHM_DVS_LEVEL_LPSR, 1176 1176 + .run_reg = BD72720_REG_LDO3_VSEL_R, 1177 1177 + .run_mask = BD72720_MASK_LDO12346_VSEL, 1178 1178 + .idle_reg = BD72720_REG_LDO3_VSEL_I, 1179 1179 + .idle_mask = BD72720_MASK_LDO12346_VSEL, 1180 1180 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1181 1181 + .suspend_reg = BD72720_REG_LDO3_VSEL_S, 1182 1182 + .suspend_mask = BD72720_MASK_LDO12346_VSEL, 1183 1183 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1184 1184 + .lpsr_reg = BD72720_REG_LDO3_VSEL_DI, 1185 1185 + .lpsr_mask = BD72720_MASK_LDO12346_VSEL, 1186 1186 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1187 1187 + }, 1188 1188 + }, { 1189 1189 + .desc = { 1190 1190 + .name = "ldo4", 1191 1191 + .of_match = of_match_ptr("ldo4"), 1192 1192 + .regulators_node = of_match_ptr("regulators"), 1193 1193 + .id = BD72720_LDO4, 1194 1194 + .type = REGULATOR_VOLTAGE, 1195 1195 + .ops = &bd72720_regulator_ops, 1196 1196 + .linear_ranges = bd72720_ldo1234_volts, 1197 1197 + .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts), 1198 1198 + .n_voltages = BD72720_NUM_LDO12346_VOLTS, 1199 1199 + .enable_reg = BD72720_REG_LDO4_ON, 1200 1200 + .enable_mask = BD72720_MASK_RUN_B_EN, 1201 1201 + .vsel_reg = BD72720_REG_LDO4_VSEL_R, 1202 1202 + .vsel_mask = BD72720_MASK_LDO12346_VSEL, 1203 1203 + 1204 1204 + .ramp_delay_table = bd72720_ramp_delay, 1205 1205 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1206 1206 + .ramp_reg = BD72720_REG_LDO4_MODE, 1207 1207 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1208 1208 + .owner = THIS_MODULE, 1209 1209 + .of_parse_cb = buck_set_hw_dvs_levels, 1210 1210 + }, 1211 1211 + .dvs = { 1212 1212 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1213 1213 + ROHM_DVS_LEVEL_SUSPEND | 1214 1214 + ROHM_DVS_LEVEL_LPSR, 1215 1215 + .run_reg = BD72720_REG_LDO4_VSEL_R, 1216 1216 + .run_mask = BD72720_MASK_LDO12346_VSEL, 1217 1217 + .idle_reg = BD72720_REG_LDO4_VSEL_I, 1218 1218 + .idle_mask = BD72720_MASK_LDO12346_VSEL, 1219 1219 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1220 1220 + .suspend_reg = BD72720_REG_LDO4_VSEL_S, 1221 1221 + .suspend_mask = BD72720_MASK_LDO12346_VSEL, 1222 1222 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1223 1223 + .lpsr_reg = BD72720_REG_LDO4_VSEL_DI, 1224 1224 + .lpsr_mask = BD72720_MASK_LDO12346_VSEL, 1225 1225 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1226 1226 + }, 1227 1227 + }, { 1228 1228 + .desc = { 1229 1229 + .name = "ldo5", 1230 1230 + .of_match = of_match_ptr("ldo5"), 1231 1231 + .regulators_node = of_match_ptr("regulators"), 1232 1232 + .id = BD72720_LDO5, 1233 1233 + .type = REGULATOR_VOLTAGE, 1234 1234 + .ops = &bd72720_regulator_ops, 1235 1235 + .linear_ranges = bd72720_ldo57891011_volts, 1236 1236 + .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts), 1237 1237 + .n_voltages = BD72720_NUM_LDO_VOLTS, 1238 1238 + .enable_reg = BD72720_REG_LDO5_ON, 1239 1239 + .enable_mask = BD72720_MASK_RUN_B_EN, 1240 1240 + .vsel_reg = BD72720_REG_LDO5_VSEL, 1241 1241 + .vsel_mask = BD72720_MASK_LDO_VSEL, 1242 1242 + 1243 1243 + .ramp_delay_table = bd72720_ramp_delay, 1244 1244 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1245 1245 + .ramp_reg = BD72720_REG_LDO5_MODE, 1246 1246 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1247 1247 + .owner = THIS_MODULE, 1248 1248 + .of_parse_cb = buck_set_hw_dvs_levels, 1249 1249 + }, 1250 1250 + .dvs = { 1251 1251 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1252 1252 + ROHM_DVS_LEVEL_SUSPEND | 1253 1253 + ROHM_DVS_LEVEL_LPSR, 1254 1254 + .run_reg = BD72720_REG_LDO5_VSEL, 1255 1255 + .run_mask = BD72720_MASK_LDO_VSEL, 1256 1256 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1257 1257 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1258 1258 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1259 1259 + }, 1260 1260 + }, { 1261 1261 + .desc = { 1262 1262 + .name = "ldo6", 1263 1263 + .of_match = of_match_ptr("ldo6"), 1264 1264 + .regulators_node = of_match_ptr("regulators"), 1265 1265 + .id = BD72720_LDO6, 1266 1266 + .type = REGULATOR_VOLTAGE, 1267 1267 + .ops = &bd72720_regulator_ops, 1268 1268 + .linear_ranges = bd72720_ldo6_volts, 1269 1269 + .n_linear_ranges = ARRAY_SIZE(bd72720_ldo6_volts), 1270 1270 + .n_voltages = BD72720_NUM_LDO12346_VOLTS, 1271 1271 + .enable_reg = BD72720_REG_LDO6_ON, 1272 1272 + .enable_mask = BD72720_MASK_RUN_B_EN, 1273 1273 + .vsel_reg = BD72720_REG_LDO6_VSEL, 1274 1274 + .vsel_mask = BD72720_MASK_LDO12346_VSEL, 1275 1275 + 1276 1276 + .ramp_delay_table = bd72720_ramp_delay, 1277 1277 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1278 1278 + .ramp_reg = BD72720_REG_LDO6_MODE, 1279 1279 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1280 1280 + .owner = THIS_MODULE, 1281 1281 + .of_parse_cb = buck_set_hw_dvs_levels, 1282 1282 + }, 1283 1283 + .dvs = { 1284 1284 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1285 1285 + ROHM_DVS_LEVEL_SUSPEND | 1286 1286 + ROHM_DVS_LEVEL_LPSR, 1287 1287 + .run_reg = BD72720_REG_LDO6_VSEL, 1288 1288 + .run_mask = BD72720_MASK_LDO12346_VSEL, 1289 1289 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1290 1290 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1291 1291 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1292 1292 + }, 1293 1293 + }, { 1294 1294 + .desc = { 1295 1295 + .name = "ldo7", 1296 1296 + .of_match = of_match_ptr("ldo7"), 1297 1297 + .regulators_node = of_match_ptr("regulators"), 1298 1298 + .id = BD72720_LDO7, 1299 1299 + .type = REGULATOR_VOLTAGE, 1300 1300 + .ops = &bd72720_regulator_ops, 1301 1301 + .linear_ranges = bd72720_ldo57891011_volts, 1302 1302 + .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts), 1303 1303 + .n_voltages = BD72720_NUM_LDO_VOLTS, 1304 1304 + .enable_reg = BD72720_REG_LDO7_ON, 1305 1305 + .enable_mask = BD72720_MASK_RUN_B_EN, 1306 1306 + .vsel_reg = BD72720_REG_LDO7_VSEL, 1307 1307 + .vsel_mask = BD72720_MASK_LDO_VSEL, 1308 1308 + 1309 1309 + .ramp_delay_table = bd72720_ramp_delay, 1310 1310 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1311 1311 + .ramp_reg = BD72720_REG_LDO7_MODE, 1312 1312 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1313 1313 + .owner = THIS_MODULE, 1314 1314 + .of_parse_cb = buck_set_hw_dvs_levels, 1315 1315 + }, 1316 1316 + .dvs = { 1317 1317 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1318 1318 + ROHM_DVS_LEVEL_SUSPEND | 1319 1319 + ROHM_DVS_LEVEL_LPSR, 1320 1320 + .run_reg = BD72720_REG_LDO7_VSEL, 1321 1321 + .run_mask = BD72720_MASK_LDO_VSEL, 1322 1322 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1323 1323 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1324 1324 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1325 1325 + }, 1326 1326 + }, { 1327 1327 + .desc = { 1328 1328 + .name = "ldo8", 1329 1329 + .of_match = of_match_ptr("ldo8"), 1330 1330 + .regulators_node = of_match_ptr("regulators"), 1331 1331 + .id = BD72720_LDO8, 1332 1332 + .type = REGULATOR_VOLTAGE, 1333 1333 + .ops = &bd72720_regulator_ops, 1334 1334 + .linear_ranges = bd72720_ldo57891011_volts, 1335 1335 + .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts), 1336 1336 + .n_voltages = BD72720_NUM_LDO_VOLTS, 1337 1337 + .enable_reg = BD72720_REG_LDO8_ON, 1338 1338 + .enable_mask = BD72720_MASK_RUN_B_EN, 1339 1339 + .vsel_reg = BD72720_REG_LDO8_VSEL, 1340 1340 + .vsel_mask = BD72720_MASK_LDO_VSEL, 1341 1341 + 1342 1342 + .ramp_delay_table = bd72720_ramp_delay, 1343 1343 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1344 1344 + .ramp_reg = BD72720_REG_LDO8_MODE, 1345 1345 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1346 1346 + .owner = THIS_MODULE, 1347 1347 + .of_parse_cb = buck_set_hw_dvs_levels, 1348 1348 + }, 1349 1349 + .dvs = { 1350 1350 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1351 1351 + ROHM_DVS_LEVEL_SUSPEND | 1352 1352 + ROHM_DVS_LEVEL_LPSR, 1353 1353 + .run_reg = BD72720_REG_LDO8_VSEL, 1354 1354 + .run_mask = BD72720_MASK_LDO_VSEL, 1355 1355 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1356 1356 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1357 1357 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1358 1358 + }, 1359 1359 + }, { 1360 1360 + .desc = { 1361 1361 + .name = "ldo9", 1362 1362 + .of_match = of_match_ptr("ldo9"), 1363 1363 + .regulators_node = of_match_ptr("regulators"), 1364 1364 + .id = BD72720_LDO9, 1365 1365 + .type = REGULATOR_VOLTAGE, 1366 1366 + .ops = &bd72720_regulator_ops, 1367 1367 + .linear_ranges = bd72720_ldo57891011_volts, 1368 1368 + .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts), 1369 1369 + .n_voltages = BD72720_NUM_LDO_VOLTS, 1370 1370 + .enable_reg = BD72720_REG_LDO9_ON, 1371 1371 + .enable_mask = BD72720_MASK_RUN_B_EN, 1372 1372 + .vsel_reg = BD72720_REG_LDO9_VSEL, 1373 1373 + .vsel_mask = BD72720_MASK_LDO_VSEL, 1374 1374 + 1375 1375 + .ramp_delay_table = bd72720_ramp_delay, 1376 1376 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1377 1377 + .ramp_reg = BD72720_REG_LDO9_MODE, 1378 1378 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1379 1379 + .owner = THIS_MODULE, 1380 1380 + .of_parse_cb = buck_set_hw_dvs_levels, 1381 1381 + }, 1382 1382 + .dvs = { 1383 1383 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1384 1384 + ROHM_DVS_LEVEL_SUSPEND | 1385 1385 + ROHM_DVS_LEVEL_LPSR, 1386 1386 + .run_reg = BD72720_REG_LDO9_VSEL, 1387 1387 + .run_mask = BD72720_MASK_LDO_VSEL, 1388 1388 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1389 1389 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1390 1390 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1391 1391 + }, 1392 1392 + }, { 1393 1393 + .desc = { 1394 1394 + .name = "ldo10", 1395 1395 + .of_match = of_match_ptr("ldo10"), 1396 1396 + .regulators_node = of_match_ptr("regulators"), 1397 1397 + .id = BD72720_LDO10, 1398 1398 + .type = REGULATOR_VOLTAGE, 1399 1399 + .ops = &bd72720_regulator_ops, 1400 1400 + .linear_ranges = bd72720_ldo57891011_volts, 1401 1401 + .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts), 1402 1402 + .n_voltages = BD72720_NUM_LDO_VOLTS, 1403 1403 + .enable_reg = BD72720_REG_LDO10_ON, 1404 1404 + .enable_mask = BD72720_MASK_RUN_B_EN, 1405 1405 + .vsel_reg = BD72720_REG_LDO10_VSEL, 1406 1406 + .vsel_mask = BD72720_MASK_LDO_VSEL, 1407 1407 + 1408 1408 + .ramp_delay_table = bd72720_ramp_delay, 1409 1409 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1410 1410 + .ramp_reg = BD72720_REG_LDO10_MODE, 1411 1411 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1412 1412 + .owner = THIS_MODULE, 1413 1413 + .of_parse_cb = buck_set_hw_dvs_levels, 1414 1414 + }, 1415 1415 + .dvs = { 1416 1416 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1417 1417 + ROHM_DVS_LEVEL_SUSPEND | 1418 1418 + ROHM_DVS_LEVEL_LPSR, 1419 1419 + .run_reg = BD72720_REG_LDO10_VSEL, 1420 1420 + .run_mask = BD72720_MASK_LDO_VSEL, 1421 1421 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1422 1422 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1423 1423 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1424 1424 + }, 1425 1425 + }, { 1426 1426 + .desc = { 1427 1427 + .name = "ldo11", 1428 1428 + .of_match = of_match_ptr("ldo11"), 1429 1429 + .regulators_node = of_match_ptr("regulators"), 1430 1430 + .id = BD72720_LDO11, 1431 1431 + .type = REGULATOR_VOLTAGE, 1432 1432 + .ops = &bd72720_regulator_ops, 1433 1433 + .linear_ranges = bd72720_ldo57891011_volts, 1434 1434 + .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts), 1435 1435 + .n_voltages = BD72720_NUM_LDO_VOLTS, 1436 1436 + .enable_reg = BD72720_REG_LDO11_ON, 1437 1437 + .enable_mask = BD72720_MASK_RUN_B_EN, 1438 1438 + .vsel_reg = BD72720_REG_LDO11_VSEL, 1439 1439 + .vsel_mask = BD72720_MASK_LDO_VSEL, 1440 1440 + 1441 1441 + .ramp_delay_table = bd72720_ramp_delay, 1442 1442 + .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay), 1443 1443 + .ramp_reg = BD72720_REG_LDO11_MODE, 1444 1444 + .ramp_mask = BD72720_MASK_RAMP_UP_DELAY, 1445 1445 + .owner = THIS_MODULE, 1446 1446 + .of_parse_cb = buck_set_hw_dvs_levels, 1447 1447 + }, 1448 1448 + .dvs = { 1449 1449 + .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | 1450 1450 + ROHM_DVS_LEVEL_SUSPEND | 1451 1451 + ROHM_DVS_LEVEL_LPSR, 1452 1452 + .run_reg = BD72720_REG_LDO11_VSEL, 1453 1453 + .run_mask = BD72720_MASK_LDO_VSEL, 1454 1454 + .idle_on_mask = BD72720_MASK_IDLE_EN, 1455 1455 + .suspend_on_mask = BD72720_MASK_SUSPEND_EN, 1456 1456 + .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN, 1457 1457 + }, 1458 1458 + }, 1459 1459 + }; 1460 1460 + 1461 1461 + static int bd72720_buck10_ldon_head_mode(struct device *dev, 1462 1462 + struct device_node *npreg, 1463 1463 + struct regmap *regmap, 1464 1464 + struct regulator_desc *buck10_desc) 1465 1465 + { 1466 1466 + struct device_node *np __free(device_node) = 1467 1467 + of_get_child_by_name(npreg, "buck10"); 1468 1468 + uint32_t ldon_head; 1469 1469 + int ldon_val; 1470 1470 + int ret; 1471 1471 + 1472 1472 + if (!np) { 1473 1473 + dev_err(dev, "failed to find buck10 regulator node\n"); 1474 1474 + return -ENODEV; 1475 1475 + } 1476 1476 + 1477 1477 + ret = of_property_read_u32(np, "rohm,ldon-head-microvolt", &ldon_head); 1478 1478 + if (ret == -EINVAL) 1479 1479 + return 0; 1480 1480 + if (ret) 1481 1481 + return ret; 1482 1482 + 1483 1483 + /* 1484 1484 + * LDON_HEAD mode means the BUCK10 is used to supply LDOs 1-4 and 1485 1485 + * the BUCK 10 voltage is automatically set to follow LDO 1-4 1486 1486 + * settings. Thus the BUCK10 should not allow voltage [g/s]etting. 1487 1487 + */ 1488 1488 + buck10_desc->ops = &bd72720_buck10_ldon_head_op; 1489 1489 + 1490 1490 + ldon_val = ldon_head / 50000 + 1; 1491 1491 + if (ldon_head > 300000) { 1492 1492 + dev_warn(dev, "Unsupported LDON_HEAD, clamping to 300 mV\n"); 1493 1493 + ldon_val = 7; 1494 1494 + } 1495 1495 + 1496 1496 + return regmap_update_bits(regmap, BD72720_REG_LDO1_MODE2, 1497 1497 + BD72720_MASK_LDON_HEAD, ldon_val); 1498 1498 + } 1499 1499 + 1500 1500 + static int bd72720_dt_parse(struct device *dev, 1501 1501 + struct regulator_desc *buck10_desc, 1502 1502 + struct regmap *regmap) 1503 1503 + { 1504 1504 + struct device_node *nproot __free(device_node) = 1505 1505 + of_get_child_by_name(dev->parent->of_node, "regulators"); 1506 1506 + 1507 1507 + if (!nproot) { 1508 1508 + dev_err(dev, "failed to find regulators node\n"); 1509 1509 + return -ENODEV; 1510 1510 + } 1511 1511 + 1512 1512 + return bd72720_buck10_ldon_head_mode(dev, nproot, regmap, buck10_desc); 1513 1513 + } 1514 1514 + 788 1515 static int bd71828_probe(struct platform_device *pdev) 789 1516 { 790 790 - int i, j, ret; 1517 1517 + int i, j, ret, num_regulators; 791 1518 struct regulator_config config = { 792 1519 .dev = pdev->dev.parent, 793 1520 }; 1521 1521 + enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data; 1522 1522 + struct bd71828_regulator_data *rdata; 794 1523 795 1524 config.regmap = dev_get_regmap(pdev->dev.parent, NULL); 796 1525 if (!config.regmap) 797 1526 return -ENODEV; 798 1527 799 799 - for (i = 0; i < ARRAY_SIZE(bd71828_rdata); i++) { 800 800 - struct regulator_dev *rdev; 801 801 - const struct bd71828_regulator_data *rd; 1528 1528 + switch (chip) { 1529 1529 + case ROHM_CHIP_TYPE_BD72720: 1530 1530 + rdata = devm_kmemdup(&pdev->dev, bd72720_rdata, 1531 1531 + sizeof(bd72720_rdata), GFP_KERNEL); 1532 1532 + if (!rdata) 1533 1533 + return -ENOMEM; 802 1534 803 803 - rd = &bd71828_rdata[i]; 1535 1535 + ret = bd72720_dt_parse(&pdev->dev, &rdata[BD72720_BUCK10_DESC_INDEX].desc, 1536 1536 + config.regmap); 1537 1537 + if (ret) 1538 1538 + return ret; 1539 1539 + 1540 1540 + num_regulators = ARRAY_SIZE(bd72720_rdata); 1541 1541 + break; 1542 1542 + 1543 1543 + case ROHM_CHIP_TYPE_BD71828: 1544 1544 + rdata = devm_kmemdup(&pdev->dev, bd71828_rdata, 1545 1545 + sizeof(bd71828_rdata), GFP_KERNEL); 1546 1546 + if (!rdata) 1547 1547 + return -ENOMEM; 1548 1548 + 1549 1549 + num_regulators = ARRAY_SIZE(bd71828_rdata); 1550 1550 + 1551 1551 + break; 1552 1552 + default: 1553 1553 + return dev_err_probe(&pdev->dev, -EINVAL, 1554 1554 + "Unsupported device\n"); 1555 1555 + } 1556 1556 + 1557 1557 + for (i = 0; i < num_regulators; i++) { 1558 1558 + struct regulator_dev *rdev; 1559 1559 + struct bd71828_regulator_data *rd; 1560 1560 + 1561 1561 + rd = &rdata[i]; 1562 1562 + 1563 1563 + config.driver_data = rd; 804 1564 rdev = devm_regulator_register(&pdev->dev, 805 1565 &rd->desc, &config); 806 1566 if (IS_ERR(rdev)) ··· 1690 714 return 0; 1691 715 } 1692 716 717 717 + static const struct platform_device_id bd71828_pmic_id[] = { 718 718 + { "bd71828-pmic", ROHM_CHIP_TYPE_BD71828 }, 719 719 + { "bd72720-pmic", ROHM_CHIP_TYPE_BD72720 }, 720 720 + { }, 721 721 + }; 722 722 + MODULE_DEVICE_TABLE(platform, bd71828_pmic_id); 723 723 + 1693 724 static struct platform_driver bd71828_regulator = { 1694 725 .driver = { 1695 726 .name = "bd71828-pmic", 1696 727 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1697 728 }, 1698 729 .probe = bd71828_probe, 730 730 + .id_table = bd71828_pmic_id, 1699 731 }; 1700 732 1701 733 module_platform_driver(bd71828_regulator); ··· 1711 727 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 1712 728 MODULE_DESCRIPTION("BD71828 voltage regulator driver"); 1713 729 MODULE_LICENSE("GPL"); 1714 1714 - MODULE_ALIAS("platform:bd71828-pmic");

+2 -1

drivers/rtc/Kconfig

reviewed

··· 570 570 depends on MFD_ROHM_BD71828 571 571 help 572 572 If you say Y here you will get support for the RTC 573 573 - block on ROHM BD71815 and BD71828 Power Management IC. 573 573 + block on ROHM BD71815, BD71828 and BD72720 Power 574 574 + Management ICs. 574 575 575 576 This driver can also be built as a module. If so, the module 576 577 will be called rtc-bd70528.

+14 -7

drivers/rtc/rtc-bd70528.c

reviewed

··· 7 7 #include <linux/bcd.h> 8 8 #include <linux/mfd/rohm-bd71815.h> 9 9 #include <linux/mfd/rohm-bd71828.h> 10 10 + #include <linux/mfd/rohm-bd72720.h> 10 11 #include <linux/module.h> 11 12 #include <linux/of.h> 12 13 #include <linux/platform_device.h> ··· 263 262 264 263 /* 265 264 * See also BD718XX_ALM_EN_OFFSET: 266 266 - * This works for BD71828 and BD71815 as they have same offset 267 267 - * between ALM0 start and ALM0_MASK. If new ICs are to be 268 268 - * added this requires proper check as ALM0_MASK is not located 269 269 - * at the end of ALM0 block - but after all ALM blocks so if 270 270 - * amount of ALMs differ the offset to enable/disable is likely 271 271 - * to be incorrect and enable/disable must be given as own 272 272 - * reg address here. 265 265 + * This works for BD71828, BD71815, and BD72720 as they all 266 266 + * have same offset between the ALM0 start and the ALM0_MASK. 267 267 + * If new ICs are to be added this requires proper check as 268 268 + * the ALM0_MASK is not located at the end of ALM0 block - 269 269 + * but after all ALM blocks. If amount of ALMs differ, the 270 270 + * offset to enable/disable is likely to be incorrect and 271 271 + * enable/disable must be given as own reg address here. 273 272 */ 274 273 bd_rtc->bd718xx_alm_block_start = BD71815_REG_RTC_ALM_START; 275 274 hour_reg = BD71815_REG_HOUR; ··· 278 277 bd_rtc->reg_time_start = BD71828_REG_RTC_START; 279 278 bd_rtc->bd718xx_alm_block_start = BD71828_REG_RTC_ALM_START; 280 279 hour_reg = BD71828_REG_RTC_HOUR; 280 280 + break; 281 281 + case ROHM_CHIP_TYPE_BD72720: 282 282 + bd_rtc->reg_time_start = BD72720_REG_RTC_START; 283 283 + bd_rtc->bd718xx_alm_block_start = BD72720_REG_RTC_ALM_START; 284 284 + hour_reg = BD72720_REG_RTC_HOUR; 281 285 break; 282 286 default: 283 287 dev_err(&pdev->dev, "Unknown chip\n"); ··· 343 337 static const struct platform_device_id bd718x7_rtc_id[] = { 344 338 { "bd71828-rtc", ROHM_CHIP_TYPE_BD71828 }, 345 339 { "bd71815-rtc", ROHM_CHIP_TYPE_BD71815 }, 340 340 + { "bd72720-rtc", ROHM_CHIP_TYPE_BD72720 }, 346 341 { }, 347 342 }; 348 343 MODULE_DEVICE_TABLE(platform, bd718x7_rtc_id);

+61

include/dt-bindings/gpio/nvidia,tegra264-gpio.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 2 + /* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */ 3 3 + 4 4 + /* 5 5 + * This header provides constants for binding nvidia,tegra264-gpio*. 6 6 + * 7 7 + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 8 8 + * provide names for this. 9 9 + * 10 10 + * The second cell contains standard flag values specified in gpio.h. 11 11 + */ 12 12 + 13 13 + #ifndef _DT_BINDINGS_GPIO_TEGRA264_GPIO_H 14 14 + #define _DT_BINDINGS_GPIO_TEGRA264_GPIO_H 15 15 + 16 16 + #include <dt-bindings/gpio/gpio.h> 17 17 + 18 18 + /* GPIOs implemented by main GPIO controller */ 19 19 + #define TEGRA264_MAIN_GPIO_PORT_T 0 20 20 + #define TEGRA264_MAIN_GPIO_PORT_U 1 21 21 + #define TEGRA264_MAIN_GPIO_PORT_V 2 22 22 + #define TEGRA264_MAIN_GPIO_PORT_W 3 23 23 + #define TEGRA264_MAIN_GPIO_PORT_AL 4 24 24 + #define TEGRA264_MAIN_GPIO_PORT_Y 5 25 25 + #define TEGRA264_MAIN_GPIO_PORT_Z 6 26 26 + #define TEGRA264_MAIN_GPIO_PORT_X 7 27 27 + #define TEGRA264_MAIN_GPIO_PORT_H 8 28 28 + #define TEGRA264_MAIN_GPIO_PORT_J 9 29 29 + #define TEGRA264_MAIN_GPIO_PORT_K 10 30 30 + #define TEGRA264_MAIN_GPIO_PORT_L 11 31 31 + #define TEGRA264_MAIN_GPIO_PORT_M 12 32 32 + #define TEGRA264_MAIN_GPIO_PORT_P 13 33 33 + #define TEGRA264_MAIN_GPIO_PORT_Q 14 34 34 + #define TEGRA264_MAIN_GPIO_PORT_R 15 35 35 + #define TEGRA264_MAIN_GPIO_PORT_S 16 36 36 + #define TEGRA264_MAIN_GPIO_PORT_F 17 37 37 + #define TEGRA264_MAIN_GPIO_PORT_G 18 38 38 + 39 39 + #define TEGRA264_MAIN_GPIO(port, offset) \ 40 40 + ((TEGRA264_MAIN_GPIO_PORT_##port * 8) + (offset)) 41 41 + 42 42 + /* GPIOs implemented by AON GPIO controller */ 43 43 + #define TEGRA264_AON_GPIO_PORT_AA 0 44 44 + #define TEGRA264_AON_GPIO_PORT_BB 1 45 45 + #define TEGRA264_AON_GPIO_PORT_CC 2 46 46 + #define TEGRA264_AON_GPIO_PORT_DD 3 47 47 + #define TEGRA264_AON_GPIO_PORT_EE 4 48 48 + 49 49 + #define TEGRA264_AON_GPIO(port, offset) \ 50 50 + ((TEGRA264_AON_GPIO_PORT_##port * 8) + (offset)) 51 51 + 52 52 + #define TEGRA264_UPHY_GPIO_PORT_A 0 53 53 + #define TEGRA264_UPHY_GPIO_PORT_B 1 54 54 + #define TEGRA264_UPHY_GPIO_PORT_C 2 55 55 + #define TEGRA264_UPHY_GPIO_PORT_D 3 56 56 + #define TEGRA264_UPHY_GPIO_PORT_E 4 57 57 + 58 58 + #define TEGRA264_UPHY_GPIO(port, offset) \ 59 59 + ((TEGRA264_UPHY_GPIO_PORT_##port * 8) + (offset)) 60 60 + 61 61 + #endif

+36

include/linux/gpio/consumer.h

reviewed

··· 607 607 flags, label); 608 608 } 609 609 610 610 + /** 611 611 + * devm_fwnode_gpiod_get_optional - obtain an optional GPIO from firmware node 612 612 + * @dev: GPIO consumer 613 613 + * @fwnode: handle of the firmware node 614 614 + * @con_id: function within the GPIO consumer 615 615 + * @flags: GPIO initialization flags 616 616 + * @label: label to attach to the requested GPIO 617 617 + * 618 618 + * This function can be used for drivers that get their configuration 619 619 + * from opaque firmware. 620 620 + * 621 621 + * GPIO descriptors returned from this function are automatically disposed on 622 622 + * driver detach. 623 623 + * 624 624 + * Returns: 625 625 + * The GPIO descriptor corresponding to the optional function @con_id of device 626 626 + * dev, NULL if no GPIO has been assigned to the requested function, or 627 627 + * another IS_ERR() code if an error occurred while trying to acquire the GPIO. 628 628 + */ 629 629 + static inline 630 630 + struct gpio_desc *devm_fwnode_gpiod_get_optional(struct device *dev, 631 631 + struct fwnode_handle *fwnode, 632 632 + const char *con_id, 633 633 + enum gpiod_flags flags, 634 634 + const char *label) 635 635 + { 636 636 + struct gpio_desc *desc; 637 637 + 638 638 + desc = devm_fwnode_gpiod_get_index(dev, fwnode, con_id, 0, 639 639 + flags, label); 640 640 + if (IS_ERR(desc) && PTR_ERR(desc) == -ENOENT) 641 641 + return NULL; 642 642 + 643 643 + return desc; 644 644 + } 645 645 + 610 646 struct acpi_gpio_params { 611 647 unsigned int crs_entry_index; 612 648 unsigned short line_index;

+634

include/linux/mfd/rohm-bd72720.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 2 + /* 3 3 + * Copyright 2025 ROHM Semiconductors. 4 4 + * 5 5 + * Author: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> 6 6 + */ 7 7 + 8 8 + #ifndef _MFD_BD72720_H 9 9 + #define _MFD_BD72720_H 10 10 + 11 11 + #include <linux/regmap.h> 12 12 + 13 13 + enum { 14 14 + BD72720_BUCK1, 15 15 + BD72720_BUCK2, 16 16 + BD72720_BUCK3, 17 17 + BD72720_BUCK4, 18 18 + BD72720_BUCK5, 19 19 + BD72720_BUCK6, 20 20 + BD72720_BUCK7, 21 21 + BD72720_BUCK8, 22 22 + BD72720_BUCK9, 23 23 + BD72720_BUCK10, 24 24 + BD72720_BUCK11, 25 25 + BD72720_LDO1, 26 26 + BD72720_LDO2, 27 27 + BD72720_LDO3, 28 28 + BD72720_LDO4, 29 29 + BD72720_LDO5, 30 30 + BD72720_LDO6, 31 31 + BD72720_LDO7, 32 32 + BD72720_LDO8, 33 33 + BD72720_LDO9, 34 34 + BD72720_LDO10, 35 35 + BD72720_LDO11, 36 36 + BD72720_REGULATOR_AMOUNT, 37 37 + }; 38 38 + 39 39 + /* BD72720 interrupts */ 40 40 + #define BD72720_INT_LONGPUSH_MASK BIT(0) 41 41 + #define BD72720_INT_MIDPUSH_MASK BIT(1) 42 42 + #define BD72720_INT_SHORTPUSH_MASK BIT(2) 43 43 + #define BD72720_INT_PUSH_MASK BIT(3) 44 44 + #define BD72720_INT_HALL_DET_MASK BIT(4) 45 45 + #define BD72720_INT_HALL_TGL_MASK BIT(5) 46 46 + #define BD72720_INT_WDOG_MASK BIT(6) 47 47 + #define BD72720_INT_SWRESET_MASK BIT(7) 48 48 + #define BD72720_INT_SEQ_DONE_MASK BIT(0) 49 49 + #define BD72720_INT_PGFAULT_MASK BIT(4) 50 50 + #define BD72720_INT_BUCK1_DVS_MASK BIT(0) 51 51 + #define BD72720_INT_BUCK2_DVS_MASK BIT(1) 52 52 + #define BD72720_INT_BUCK3_DVS_MASK BIT(2) 53 53 + #define BD72720_INT_BUCK4_DVS_MASK BIT(3) 54 54 + #define BD72720_INT_BUCK5_DVS_MASK BIT(4) 55 55 + #define BD72720_INT_BUCK6_DVS_MASK BIT(5) 56 56 + #define BD72720_INT_BUCK7_DVS_MASK BIT(6) 57 57 + #define BD72720_INT_BUCK8_DVS_MASK BIT(7) 58 58 + #define BD72720_INT_BUCK9_DVS_MASK BIT(0) 59 59 + #define BD72720_INT_BUCK10_DVS_MASK BIT(1) 60 60 + #define BD72720_INT_LDO1_DVS_MASK BIT(4) 61 61 + #define BD72720_INT_LDO2_DVS_MASK BIT(5) 62 62 + #define BD72720_INT_LDO3_DVS_MASK BIT(6) 63 63 + #define BD72720_INT_LDO4_DVS_MASK BIT(7) 64 64 + #define BD72720_INT_VBUS_RMV_MASK BIT(0) 65 65 + #define BD72720_INT_VBUS_DET_MASK BIT(1) 66 66 + #define BD72720_INT_VBUS_MON_RES_MASK BIT(2) 67 67 + #define BD72720_INT_VBUS_MON_DET_MASK BIT(3) 68 68 + #define BD72720_INT_VSYS_MON_RES_MASK BIT(0) 69 69 + #define BD72720_INT_VSYS_MON_DET_MASK BIT(1) 70 70 + #define BD72720_INT_VSYS_UV_RES_MASK BIT(2) 71 71 + #define BD72720_INT_VSYS_UV_DET_MASK BIT(3) 72 72 + #define BD72720_INT_VSYS_LO_RES_MASK BIT(4) 73 73 + #define BD72720_INT_VSYS_LO_DET_MASK BIT(5) 74 74 + #define BD72720_INT_VSYS_OV_RES_MASK BIT(6) 75 75 + #define BD72720_INT_VSYS_OV_DET_MASK BIT(7) 76 76 + #define BD72720_INT_BAT_ILIM_MASK BIT(0) 77 77 + #define BD72720_INT_CHG_DONE_MASK BIT(1) 78 78 + #define BD72720_INT_EXTEMP_TOUT_MASK BIT(2) 79 79 + #define BD72720_INT_CHG_WDT_EXP_MASK BIT(3) 80 80 + #define BD72720_INT_BAT_MNT_OUT_MASK BIT(4) 81 81 + #define BD72720_INT_BAT_MNT_IN_MASK BIT(5) 82 82 + #define BD72720_INT_CHG_TRNS_MASK BIT(7) 83 83 + #define BD72720_INT_VBAT_MON_RES_MASK BIT(0) 84 84 + #define BD72720_INT_VBAT_MON_DET_MASK BIT(1) 85 85 + #define BD72720_INT_VBAT_SHT_RES_MASK BIT(2) 86 86 + #define BD72720_INT_VBAT_SHT_DET_MASK BIT(3) 87 87 + #define BD72720_INT_VBAT_LO_RES_MASK BIT(4) 88 88 + #define BD72720_INT_VBAT_LO_DET_MASK BIT(5) 89 89 + #define BD72720_INT_VBAT_OV_RES_MASK BIT(6) 90 90 + #define BD72720_INT_VBAT_OV_DET_MASK BIT(7) 91 91 + #define BD72720_INT_BAT_RMV_MASK BIT(0) 92 92 + #define BD72720_INT_BAT_DET_MASK BIT(1) 93 93 + #define BD72720_INT_DBAT_DET_MASK BIT(2) 94 94 + #define BD72720_INT_BAT_TEMP_TRNS_MASK BIT(3) 95 95 + #define BD72720_INT_LOBTMP_RES_MASK BIT(4) 96 96 + #define BD72720_INT_LOBTMP_DET_MASK BIT(5) 97 97 + #define BD72720_INT_OVBTMP_RES_MASK BIT(6) 98 98 + #define BD72720_INT_OVBTMP_DET_MASK BIT(7) 99 99 + #define BD72720_INT_OCUR1_RES_MASK BIT(0) 100 100 + #define BD72720_INT_OCUR1_DET_MASK BIT(1) 101 101 + #define BD72720_INT_OCUR2_RES_MASK BIT(2) 102 102 + #define BD72720_INT_OCUR2_DET_MASK BIT(3) 103 103 + #define BD72720_INT_OCUR3_RES_MASK BIT(4) 104 104 + #define BD72720_INT_OCUR3_DET_MASK BIT(5) 105 105 + #define BD72720_INT_CC_MON1_DET_MASK BIT(0) 106 106 + #define BD72720_INT_CC_MON2_DET_MASK BIT(1) 107 107 + #define BD72720_INT_CC_MON3_DET_MASK BIT(2) 108 108 + #define BD72720_INT_GPIO1_IN_MASK BIT(4) 109 109 + #define BD72720_INT_GPIO2_IN_MASK BIT(5) 110 110 + #define BD72720_INT_VF125_RES_MASK BIT(0) 111 111 + #define BD72720_INT_VF125_DET_MASK BIT(1) 112 112 + #define BD72720_INT_VF_RES_MASK BIT(2) 113 113 + #define BD72720_INT_VF_DET_MASK BIT(3) 114 114 + #define BD72720_INT_RTC0_MASK BIT(4) 115 115 + #define BD72720_INT_RTC1_MASK BIT(5) 116 116 + #define BD72720_INT_RTC2_MASK BIT(6) 117 117 + 118 118 + enum { 119 119 + /* 120 120 + * The IRQs excluding GPIO1 and GPIO2 are ordered in a same way as the 121 121 + * respective IRQ bits in status and mask registers are ordered. 122 122 + * 123 123 + * The BD72720_INT_GPIO1_IN and BD72720_INT_GPIO2_IN are IRQs which can 124 124 + * be used by other devices. Let's have GPIO1 and GPIO2 as first IRQs 125 125 + * here so we can use the regmap-IRQ with standard device tree xlate 126 126 + * while devices connected to the BD72720 IRQ input pins can refer to 127 127 + * the first two interrupt numbers in their device tree. If we placed 128 128 + * BD72720_INT_GPIO1_IN and BD72720_INT_GPIO2_IN after the CC_MON_DET 129 129 + * interrupts (like they are in the registers), the devices using 130 130 + * BD72720 as an IRQ parent should refer the interrupts starting with 131 131 + * an offset which might not be trivial to understand. 132 132 + */ 133 133 + BD72720_INT_GPIO1_IN, 134 134 + BD72720_INT_GPIO2_IN, 135 135 + BD72720_INT_LONGPUSH, 136 136 + BD72720_INT_MIDPUSH, 137 137 + BD72720_INT_SHORTPUSH, 138 138 + BD72720_INT_PUSH, 139 139 + BD72720_INT_HALL_DET, 140 140 + BD72720_INT_HALL_TGL, 141 141 + BD72720_INT_WDOG, 142 142 + BD72720_INT_SWRESET, 143 143 + BD72720_INT_SEQ_DONE, 144 144 + BD72720_INT_PGFAULT, 145 145 + BD72720_INT_BUCK1_DVS, 146 146 + BD72720_INT_BUCK2_DVS, 147 147 + BD72720_INT_BUCK3_DVS, 148 148 + BD72720_INT_BUCK4_DVS, 149 149 + BD72720_INT_BUCK5_DVS, 150 150 + BD72720_INT_BUCK6_DVS, 151 151 + BD72720_INT_BUCK7_DVS, 152 152 + BD72720_INT_BUCK8_DVS, 153 153 + BD72720_INT_BUCK9_DVS, 154 154 + BD72720_INT_BUCK10_DVS, 155 155 + BD72720_INT_LDO1_DVS, 156 156 + BD72720_INT_LDO2_DVS, 157 157 + BD72720_INT_LDO3_DVS, 158 158 + BD72720_INT_LDO4_DVS, 159 159 + BD72720_INT_VBUS_RMV, 160 160 + BD72720_INT_VBUS_DET, 161 161 + BD72720_INT_VBUS_MON_RES, 162 162 + BD72720_INT_VBUS_MON_DET, 163 163 + BD72720_INT_VSYS_MON_RES, 164 164 + BD72720_INT_VSYS_MON_DET, 165 165 + BD72720_INT_VSYS_UV_RES, 166 166 + BD72720_INT_VSYS_UV_DET, 167 167 + BD72720_INT_VSYS_LO_RES, 168 168 + BD72720_INT_VSYS_LO_DET, 169 169 + BD72720_INT_VSYS_OV_RES, 170 170 + BD72720_INT_VSYS_OV_DET, 171 171 + BD72720_INT_BAT_ILIM, 172 172 + BD72720_INT_CHG_DONE, 173 173 + BD72720_INT_EXTEMP_TOUT, 174 174 + BD72720_INT_CHG_WDT_EXP, 175 175 + BD72720_INT_BAT_MNT_OUT, 176 176 + BD72720_INT_BAT_MNT_IN, 177 177 + BD72720_INT_CHG_TRNS, 178 178 + BD72720_INT_VBAT_MON_RES, 179 179 + BD72720_INT_VBAT_MON_DET, 180 180 + BD72720_INT_VBAT_SHT_RES, 181 181 + BD72720_INT_VBAT_SHT_DET, 182 182 + BD72720_INT_VBAT_LO_RES, 183 183 + BD72720_INT_VBAT_LO_DET, 184 184 + BD72720_INT_VBAT_OV_RES, 185 185 + BD72720_INT_VBAT_OV_DET, 186 186 + BD72720_INT_BAT_RMV, 187 187 + BD72720_INT_BAT_DET, 188 188 + BD72720_INT_DBAT_DET, 189 189 + BD72720_INT_BAT_TEMP_TRNS, 190 190 + BD72720_INT_LOBTMP_RES, 191 191 + BD72720_INT_LOBTMP_DET, 192 192 + BD72720_INT_OVBTMP_RES, 193 193 + BD72720_INT_OVBTMP_DET, 194 194 + BD72720_INT_OCUR1_RES, 195 195 + BD72720_INT_OCUR1_DET, 196 196 + BD72720_INT_OCUR2_RES, 197 197 + BD72720_INT_OCUR2_DET, 198 198 + BD72720_INT_OCUR3_RES, 199 199 + BD72720_INT_OCUR3_DET, 200 200 + BD72720_INT_CC_MON1_DET, 201 201 + BD72720_INT_CC_MON2_DET, 202 202 + BD72720_INT_CC_MON3_DET, 203 203 + BD72720_INT_VF125_RES, 204 204 + BD72720_INT_VF125_DET, 205 205 + BD72720_INT_VF_RES, 206 206 + BD72720_INT_VF_DET, 207 207 + BD72720_INT_RTC0, 208 208 + BD72720_INT_RTC1, 209 209 + BD72720_INT_RTC2, 210 210 + }; 211 211 + 212 212 + /* 213 213 + * BD72720 Registers: 214 214 + * The BD72720 has two sets of registers behind two different I2C slave 215 215 + * addresses. "Common" registers being behind 0x4b, the charger registers 216 216 + * being behind 0x4c. 217 217 + */ 218 218 + /* Registers behind I2C slave 0x4b */ 219 219 + enum { 220 220 + BD72720_REG_PRODUCT_ID, 221 221 + BD72720_REG_MANUFACTURER_ID, 222 222 + BD72720_REG_PMIC_REV_NUM, 223 223 + BD72720_REG_NVM_REV_NUM, 224 224 + BD72720_REG_BOOTSRC = 0x10, 225 225 + BD72720_REG_RESETSRC_1, 226 226 + BD72720_REG_RESETSRC_2, 227 227 + BD72720_REG_RESETSRC_3, 228 228 + BD72720_REG_RESETSRC_4, 229 229 + BD72720_REG_RESETSRC_5, 230 230 + BD72720_REG_RESETSRC_6, 231 231 + BD72720_REG_RESETSRC_7, 232 232 + BD72720_REG_POWER_STATE, 233 233 + BD72720_REG_PS_CFG, 234 234 + BD72720_REG_PS_CTRL_1, 235 235 + BD72720_REG_PS_CTRL_2, 236 236 + BD72720_REG_RCVCFG, 237 237 + BD72720_REG_RCVNUM, 238 238 + BD72720_REG_CRDCFG, 239 239 + BD72720_REG_REX_CTRL, 240 240 + 241 241 + BD72720_REG_BUCK1_ON, 242 242 + BD72720_REG_BUCK1_MODE, 243 243 + /* Deep idle vsel */ 244 244 + BD72720_REG_BUCK1_VSEL_DI, 245 245 + /* Idle vsel */ 246 246 + BD72720_REG_BUCK1_VSEL_I, 247 247 + /* Suspend vsel */ 248 248 + BD72720_REG_BUCK1_VSEL_S, 249 249 + /* Run boot vsel */ 250 250 + BD72720_REG_BUCK1_VSEL_RB, 251 251 + /* Run0 ... run3 vsel */ 252 252 + BD72720_REG_BUCK1_VSEL_RB0, 253 253 + BD72720_REG_BUCK1_VSEL_RB1, 254 254 + BD72720_REG_BUCK1_VSEL_RB2, 255 255 + BD72720_REG_BUCK1_VSEL_RB3, 256 256 + 257 257 + BD72720_REG_BUCK2_ON, 258 258 + BD72720_REG_BUCK2_MODE, 259 259 + BD72720_REG_BUCK2_VSEL_DI, 260 260 + BD72720_REG_BUCK2_VSEL_I, 261 261 + BD72720_REG_BUCK2_VSEL_S, 262 262 + /* Run vsel */ 263 263 + BD72720_REG_BUCK2_VSEL_R, 264 264 + 265 265 + BD72720_REG_BUCK3_ON, 266 266 + BD72720_REG_BUCK3_MODE, 267 267 + BD72720_REG_BUCK3_VSEL_DI, 268 268 + BD72720_REG_BUCK3_VSEL_I, 269 269 + BD72720_REG_BUCK3_VSEL_S, 270 270 + BD72720_REG_BUCK3_VSEL_R, 271 271 + 272 272 + BD72720_REG_BUCK4_ON, 273 273 + BD72720_REG_BUCK4_MODE, 274 274 + BD72720_REG_BUCK4_VSEL_DI, 275 275 + BD72720_REG_BUCK4_VSEL_I, 276 276 + BD72720_REG_BUCK4_VSEL_S, 277 277 + BD72720_REG_BUCK4_VSEL_R, 278 278 + 279 279 + BD72720_REG_BUCK5_ON, 280 280 + BD72720_REG_BUCK5_MODE, 281 281 + BD72720_REG_BUCK5_VSEL, 282 282 + 283 283 + BD72720_REG_BUCK6_ON, 284 284 + BD72720_REG_BUCK6_MODE, 285 285 + BD72720_REG_BUCK6_VSEL, 286 286 + 287 287 + BD72720_REG_BUCK7_ON, 288 288 + BD72720_REG_BUCK7_MODE, 289 289 + BD72720_REG_BUCK7_VSEL, 290 290 + 291 291 + BD72720_REG_BUCK8_ON, 292 292 + BD72720_REG_BUCK8_MODE, 293 293 + BD72720_REG_BUCK8_VSEL, 294 294 + 295 295 + BD72720_REG_BUCK9_ON, 296 296 + BD72720_REG_BUCK9_MODE, 297 297 + BD72720_REG_BUCK9_VSEL, 298 298 + 299 299 + BD72720_REG_BUCK10_ON, 300 300 + BD72720_REG_BUCK10_MODE, 301 301 + BD72720_REG_BUCK10_VSEL, 302 302 + 303 303 + BD72720_REG_LDO1_ON, 304 304 + BD72720_REG_LDO1_MODE1, 305 305 + BD72720_REG_LDO1_MODE2, 306 306 + BD72720_REG_LDO1_VSEL_DI, 307 307 + BD72720_REG_LDO1_VSEL_I, 308 308 + BD72720_REG_LDO1_VSEL_S, 309 309 + BD72720_REG_LDO1_VSEL_RB, 310 310 + BD72720_REG_LDO1_VSEL_R0, 311 311 + BD72720_REG_LDO1_VSEL_R1, 312 312 + BD72720_REG_LDO1_VSEL_R2, 313 313 + BD72720_REG_LDO1_VSEL_R3, 314 314 + 315 315 + BD72720_REG_LDO2_ON, 316 316 + BD72720_REG_LDO2_MODE, 317 317 + BD72720_REG_LDO2_VSEL_DI, 318 318 + BD72720_REG_LDO2_VSEL_I, 319 319 + BD72720_REG_LDO2_VSEL_S, 320 320 + BD72720_REG_LDO2_VSEL_R, 321 321 + 322 322 + BD72720_REG_LDO3_ON, 323 323 + BD72720_REG_LDO3_MODE, 324 324 + BD72720_REG_LDO3_VSEL_DI, 325 325 + BD72720_REG_LDO3_VSEL_I, 326 326 + BD72720_REG_LDO3_VSEL_S, 327 327 + BD72720_REG_LDO3_VSEL_R, 328 328 + 329 329 + BD72720_REG_LDO4_ON, 330 330 + BD72720_REG_LDO4_MODE, 331 331 + BD72720_REG_LDO4_VSEL_DI, 332 332 + BD72720_REG_LDO4_VSEL_I, 333 333 + BD72720_REG_LDO4_VSEL_S, 334 334 + BD72720_REG_LDO4_VSEL_R, 335 335 + 336 336 + BD72720_REG_LDO5_ON, 337 337 + BD72720_REG_LDO5_MODE, 338 338 + BD72720_REG_LDO5_VSEL, 339 339 + 340 340 + BD72720_REG_LDO6_ON, 341 341 + BD72720_REG_LDO6_MODE, 342 342 + BD72720_REG_LDO6_VSEL, 343 343 + 344 344 + BD72720_REG_LDO7_ON, 345 345 + BD72720_REG_LDO7_MODE, 346 346 + BD72720_REG_LDO7_VSEL, 347 347 + 348 348 + BD72720_REG_LDO8_ON, 349 349 + BD72720_REG_LDO8_MODE, 350 350 + BD72720_REG_LDO8_VSEL, 351 351 + 352 352 + BD72720_REG_LDO9_ON, 353 353 + BD72720_REG_LDO9_MODE, 354 354 + BD72720_REG_LDO9_VSEL, 355 355 + 356 356 + BD72720_REG_LDO10_ON, 357 357 + BD72720_REG_LDO10_MODE, 358 358 + BD72720_REG_LDO10_VSEL, 359 359 + 360 360 + BD72720_REG_LDO11_ON, 361 361 + BD72720_REG_LDO11_MODE, 362 362 + BD72720_REG_LDO11_VSEL, 363 363 + 364 364 + BD72720_REG_GPIO1_ON = 0x8b, 365 365 + BD72720_REG_GPIO2_ON, 366 366 + BD72720_REG_GPIO3_ON, 367 367 + BD72720_REG_GPIO4_ON, 368 368 + BD72720_REG_GPIO5_ON, 369 369 + 370 370 + BD72720_REG_GPIO1_CTRL, 371 371 + BD72720_REG_GPIO2_CTRL, 372 372 + #define BD72720_GPIO_IRQ_TYPE_MASK GENMASK(6, 4) 373 373 + #define BD72720_GPIO_IRQ_TYPE_FALLING 0x0 374 374 + #define BD72720_GPIO_IRQ_TYPE_RISING 0x1 375 375 + #define BD72720_GPIO_IRQ_TYPE_BOTH 0x2 376 376 + #define BD72720_GPIO_IRQ_TYPE_HIGH 0x3 377 377 + #define BD72720_GPIO_IRQ_TYPE_LOW 0x4 378 378 + BD72720_REG_GPIO3_CTRL, 379 379 + BD72720_REG_GPIO4_CTRL, 380 380 + BD72720_REG_GPIO5_CTRL, 381 381 + #define BD72720_GPIO_DRIVE_MASK BIT(1) 382 382 + #define BD72720_GPIO_HIGH BIT(0) 383 383 + 384 384 + BD72720_REG_EPDEN_CTRL, 385 385 + BD72720_REG_GATECNT_CTRL, 386 386 + BD72720_REG_LED_CTRL, 387 387 + 388 388 + BD72720_REG_PWRON_CFG1, 389 389 + BD72720_REG_PWRON_CFG2, 390 390 + 391 391 + BD72720_REG_OUT32K, 392 392 + BD72720_REG_CONF, 393 393 + BD72720_REG_HALL_STAT, 394 394 + 395 395 + BD72720_REG_RTC_SEC = 0xa0, 396 396 + #define BD72720_REG_RTC_START BD72720_REG_RTC_SEC 397 397 + BD72720_REG_RTC_MIN, 398 398 + BD72720_REG_RTC_HOUR, 399 399 + BD72720_REG_RTC_WEEK, 400 400 + BD72720_REG_RTC_DAY, 401 401 + BD72720_REG_RTC_MON, 402 402 + BD72720_REG_RTC_YEAR, 403 403 + 404 404 + BD72720_REG_RTC_ALM0_SEC, 405 405 + #define BD72720_REG_RTC_ALM_START BD72720_REG_RTC_ALM0_SEC 406 406 + BD72720_REG_RTC_ALM0_MIN, 407 407 + BD72720_REG_RTC_ALM0_HOUR, 408 408 + BD72720_REG_RTC_ALM0_WEEK, 409 409 + BD72720_REG_RTC_ALM0_MON, 410 410 + BD72720_REG_RTC_ALM0_YEAR, 411 411 + 412 412 + BD72720_REG_RTC_ALM1_SEC, 413 413 + BD72720_REG_RTC_ALM1_MIN, 414 414 + BD72720_REG_RTC_ALM1_HOUR, 415 415 + BD72720_REG_RTC_ALM1_WEEK, 416 416 + BD72720_REG_RTC_ALM1_MON, 417 417 + BD72720_REG_RTC_ALM1_YEAR, 418 418 + 419 419 + BD72720_REG_RTC_ALM0_EN, 420 420 + BD72720_REG_RTC_ALM1_EN, 421 421 + BD72720_REG_RTC_ALM2, 422 422 + 423 423 + BD72720_REG_INT_LVL1_EN = 0xc0, 424 424 + #define BD72720_MASK_LVL1_EN_ALL GENMASK(7, 0) 425 425 + BD72720_REG_INT_PS1_EN, 426 426 + BD72720_REG_INT_PS2_EN, 427 427 + BD72720_REG_INT_DVS1_EN, 428 428 + BD72720_REG_INT_DVS2_EN, 429 429 + BD72720_REG_INT_VBUS_EN, 430 430 + BD72720_REG_INT_VSYS_EN, 431 431 + BD72720_REG_INT_CHG_EN, 432 432 + BD72720_REG_INT_BAT1_EN, 433 433 + BD72720_REG_INT_BAT2_EN, 434 434 + BD72720_REG_INT_IBAT_EN, 435 435 + BD72720_REG_INT_ETC1_EN, 436 436 + BD72720_REG_INT_ETC2_EN, 437 437 + 438 438 + /* 439 439 + * The _STAT registers inform IRQ line state, and are used to ack IRQ. 440 440 + * The _SRC registers below indicate current state of the function 441 441 + * connected to the line. 442 442 + */ 443 443 + BD72720_REG_INT_LVL1_STAT, 444 444 + BD72720_REG_INT_PS1_STAT, 445 445 + BD72720_REG_INT_PS2_STAT, 446 446 + BD72720_REG_INT_DVS1_STAT, 447 447 + BD72720_REG_INT_DVS2_STAT, 448 448 + BD72720_REG_INT_VBUS_STAT, 449 449 + BD72720_REG_INT_VSYS_STAT, 450 450 + BD72720_REG_INT_CHG_STAT, 451 451 + BD72720_REG_INT_BAT1_STAT, 452 452 + BD72720_REG_INT_BAT2_STAT, 453 453 + BD72720_REG_INT_IBAT_STAT, 454 454 + BD72720_REG_INT_ETC1_STAT, 455 455 + BD72720_REG_INT_ETC2_STAT, 456 456 + 457 457 + BD72720_REG_INT_LVL1_SRC, 458 458 + BD72720_REG_INT_PS1_SRC, 459 459 + BD72720_REG_INT_PS2_SRC, 460 460 + BD72720_REG_INT_DVS1_SRC, 461 461 + BD72720_REG_INT_DVS2_SRC, 462 462 + BD72720_REG_INT_VBUS_SRC, 463 463 + #define BD72720_MASK_DCIN_DET BIT(1) 464 464 + BD72720_REG_INT_VSYS_SRC, 465 465 + BD72720_REG_INT_CHG_SRC, 466 466 + BD72720_REG_INT_BAT1_SRC, 467 467 + BD72720_REG_INT_BAT2_SRC, 468 468 + BD72720_REG_INT_IBAT_SRC, 469 469 + BD72720_REG_INT_ETC1_SRC, 470 470 + BD72720_REG_INT_ETC2_SRC, 471 471 + }; 472 472 + 473 473 + /* Register masks */ 474 474 + #define BD72720_MASK_DEEP_IDLE_EN BIT(0) 475 475 + #define BD72720_MASK_IDLE_EN BIT(1) 476 476 + #define BD72720_MASK_SUSPEND_EN BIT(2) 477 477 + #define BD72720_MASK_RUN_B_EN BIT(3) 478 478 + #define BD72720_MASK_RUN_0_EN BIT(4) 479 479 + #define BD72720_MASK_RUN_1_EN BIT(5) 480 480 + #define BD72720_MASK_RUN_2_EN BIT(6) 481 481 + #define BD72720_MASK_RUN_3_EN BIT(7) 482 482 + 483 483 + #define BD72720_MASK_RAMP_UP_DELAY GENMASK(7, 6) 484 484 + #define BD72720_MASK_BUCK_VSEL GENMASK(7, 0) 485 485 + #define BD72720_MASK_LDO12346_VSEL GENMASK(6, 0) 486 486 + #define BD72720_MASK_LDO_VSEL GENMASK(7, 0) 487 487 + 488 488 + #define BD72720_I2C4C_ADDR_OFFSET 0x100 489 489 + 490 490 + /* Registers behind I2C slave 0x4c */ 491 491 + enum { 492 492 + BD72720_REG_CHG_STATE = BD72720_I2C4C_ADDR_OFFSET, 493 493 + BD72720_REG_CHG_LAST_STATE, 494 494 + BD72720_REG_CHG_VBUS_STAT, 495 495 + BD72720_REG_CHG_VSYS_STAT, 496 496 + BD72720_REG_CHG_BAT_TEMP_STAT, 497 497 + BD72720_REG_CHG_WDT_STAT, 498 498 + BD72720_REG_CHG_ILIM_STAT, 499 499 + BD72720_REG_CHG_CHG_STAT, 500 500 + BD72720_REG_CHG_EN, 501 501 + BD72720_REG_CHG_INIT, 502 502 + BD72720_REG_CHG_CTRL, 503 503 + BD72720_REG_CHG_SET_1, 504 504 + BD72720_REG_CHG_SET_2, 505 505 + BD72720_REG_CHG_SET_3, 506 506 + BD72720_REG_CHG_VPRE, 507 507 + BD72720_REG_CHG_VBAT_1, 508 508 + BD72720_REG_CHG_VBAT_2, 509 509 + BD72720_REG_CHG_VBAT_3, 510 510 + BD72720_REG_CHG_VBAT_4, 511 511 + BD72720_REG_CHG_BAT_SET_1, 512 512 + BD72720_REG_CHG_BAT_SET_2, 513 513 + BD72720_REG_CHG_BAT_SET_3, 514 514 + BD72720_REG_CHG_IPRE, 515 515 + BD72720_REG_CHG_IFST_TERM, 516 516 + BD72720_REG_CHG_VSYS_REG, 517 517 + BD72720_REG_CHG_VBUS_SET, 518 518 + BD72720_REG_CHG_WDT_PRE, 519 519 + BD72720_REG_CHG_WDT_FST, 520 520 + BD72720_REG_CHG_LED_CTRL, 521 521 + BD72720_REG_CHG_CFG_1, 522 522 + BD72720_REG_CHG_IFST_1, 523 523 + BD72720_REG_CHG_IFST_2, 524 524 + BD72720_REG_CHG_IFST_3, 525 525 + BD72720_REG_CHG_IFST_4, 526 526 + BD72720_REG_CHG_S_CFG_1, 527 527 + BD72720_REG_CHG_S_CFG_2, 528 528 + BD72720_REG_RS_VBUS, 529 529 + BD72720_REG_RS_IBUS, 530 530 + BD72720_REG_RS_VSYS, 531 531 + BD72720_REG_VSYS_STATE_STAT, /* 0x27 + offset*/ 532 532 + 533 533 + BD72720_REG_VM_VBAT_U = BD72720_I2C4C_ADDR_OFFSET + 0x30, 534 534 + BD72720_REG_VM_VBAT_L, 535 535 + BD72720_REG_VM_OCV_PRE_U, 536 536 + BD72720_REG_VM_OCV_PRE_L, 537 537 + BD72720_REG_VM_OCV_PST_U, 538 538 + BD72720_REG_VM_OCV_PST_L, 539 539 + BD72720_REG_VM_OCV_PWRON_U, 540 540 + BD72720_REG_VM_OCV_PWRON_L, 541 541 + BD72720_REG_VM_DVBAT_IMP_U, 542 542 + BD72720_REG_VM_DVBAT_IMP_L, 543 543 + BD72720_REG_VM_SA_VBAT_U, 544 544 + BD72720_REG_VM_SA_VBAT_L, 545 545 + BD72720_REG_VM_SA_VBAT_MIN_U, 546 546 + BD72720_REG_VM_SA_VBAT_MIN_L, 547 547 + BD72720_REG_VM_SA_VBAT_MAX_U, 548 548 + BD72720_REG_VM_SA_VBAT_MAX_L, 549 549 + BD72720_REG_REX_SA_VBAT_U, 550 550 + BD72720_REG_REX_SA_VBAT_L, 551 551 + BD72720_REG_VM_VSYS_U, 552 552 + BD72720_REG_VM_VSYS_L, 553 553 + BD72720_REG_VM_SA_VSYS_U, 554 554 + BD72720_REG_VM_SA_VSYS_L, 555 555 + BD72720_REG_VM_SA_VSYS_MIN_U, 556 556 + BD72720_REG_VM_SA_VSYS_MIN_L, 557 557 + BD72720_REG_VM_SA_VSYS_MAX_U, 558 558 + BD72720_REG_VM_SA_VSYS_MAX_L, 559 559 + BD72720_REG_VM_SA2_VSYS_U, 560 560 + BD72720_REG_VM_SA2_VSYS_L, 561 561 + BD72720_REG_VM_VBUS_U, 562 562 + #define BD72720_MASK_VDCIN_U GENMASK(3, 0) 563 563 + BD72720_REG_VM_VBUS_L, 564 564 + BD72720_REG_VM_BATID_U, 565 565 + BD72720_REG_VM_BATID_L, 566 566 + BD72720_REG_VM_BATID_NOLOAD_U, 567 567 + BD72720_REG_VM_BATID_NOLOAD_L, 568 568 + BD72720_REG_VM_BATID_OFS_U, 569 569 + BD72720_REG_VM_BATID_OFS_L, 570 570 + BD72720_REG_VM_VTH_U, 571 571 + BD72720_REG_VM_VTH_L, 572 572 + BD72720_REG_VM_VTH_CORR_U, 573 573 + BD72720_REG_VM_VTH_CORR_L, 574 574 + BD72720_REG_VM_BTMP_U, 575 575 + BD72720_REG_VM_BTMP_L, 576 576 + BD72720_REG_VM_BTMP_IMP_U, 577 577 + BD72720_REG_VM_BTMP_IMP_L, 578 578 + BD72720_REG_VM_VF_U, 579 579 + BD72720_REG_VM_VF_L, 580 580 + BD72720_REG_VM_BATID_TH_U, 581 581 + BD72720_REG_VM_BATID_TH_L, 582 582 + BD72720_REG_VM_BTMP_OV_THR, 583 583 + BD72720_REG_VM_BTMP_OV_DUR, 584 584 + BD72720_REG_VM_BTMP_LO_THR, 585 585 + BD72720_REG_VM_BTMP_LO_DUR, 586 586 + BD72720_REG_ALM_VBAT_TH_U, 587 587 + BD72720_REG_ALM_VBAT_TH_L, 588 588 + BD72720_REG_ALM_VSYS_TH, 589 589 + BD72720_REG_ALM_VBUS_TH, 590 590 + BD72720_REG_ALM_VF_TH, 591 591 + BD72720_REG_VSYS_MAX, 592 592 + BD72720_REG_VSYS_MIN, 593 593 + BD72720_REG_VM_VSYS_SA_MINMAX_CTRL, 594 594 + BD72720_REG_VM_SA_CFG, /* 0x6c + offset*/ 595 595 + 596 596 + BD72720_REG_CC_CURCD_U = BD72720_I2C4C_ADDR_OFFSET + 0x70, 597 597 + BD72720_REG_CC_CURCD_L, 598 598 + BD72720_REG_CC_CURCD_IMP_U, 599 599 + BD72720_REG_CC_CURCD_IMP_L, 600 600 + BD72720_REG_CC_SA_CURCD_U, 601 601 + BD72720_REG_CC_SA_CURCD_L, 602 602 + BD72720_REG_CC_OCUR_MON, 603 603 + BD72720_REG_CC_CCNTD_3, 604 604 + BD72720_REG_CC_CCNTD_2, 605 605 + BD72720_REG_CC_CCNTD_1, 606 606 + BD72720_REG_CC_CCNTD_0, 607 607 + BD72720_REG_REX_CCNTD_3, 608 608 + BD72720_REG_REX_CCNTD_2, 609 609 + BD72720_REG_REX_CCNTD_1, 610 610 + BD72720_REG_REX_CCNTD_0, 611 611 + BD72720_REG_FULL_CCNTD_3, 612 612 + BD72720_REG_FULL_CCNTD_2, 613 613 + BD72720_REG_FULL_CCNTD_1, 614 614 + BD72720_REG_FULL_CCNTD_0, 615 615 + BD72720_REG_CCNTD_CHG_3, 616 616 + BD72720_REG_CCNTD_CHG_2, 617 617 + BD72720_REG_CC_STAT, 618 618 + BD72720_REG_CC_CTRL, 619 619 + BD72720_REG_CC_OCUR_THR_1, 620 620 + BD72720_REG_CC_OCUR_THR_2, 621 621 + BD72720_REG_CC_OCUR_THR_3, 622 622 + BD72720_REG_REX_CURCD_TH, 623 623 + BD72720_REG_CC_BATCAP1_TH_U, 624 624 + BD72720_REG_CC_BATCAP1_TH_L, 625 625 + BD72720_REG_CC_BATCAP2_TH_U, 626 626 + BD72720_REG_CC_BATCAP2_TH_L, 627 627 + BD72720_REG_CC_BATCAP3_TH_U, 628 628 + BD72720_REG_CC_BATCAP3_TH_L, 629 629 + BD72720_REG_CC_CCNTD_CTRL, 630 630 + BD72720_REG_CC_SA_CFG, /* 0x92 + offset*/ 631 631 + BD72720_REG_IMPCHK_CTRL = BD72720_I2C4C_ADDR_OFFSET + 0xa0, 632 632 + }; 633 633 + 634 634 + #endif /* __LINUX_MFD_BD72720_H */

+1

include/linux/mfd/rohm-generic.h

reviewed

··· 16 16 ROHM_CHIP_TYPE_BD71828, 17 17 ROHM_CHIP_TYPE_BD71837, 18 18 ROHM_CHIP_TYPE_BD71847, 19 19 + ROHM_CHIP_TYPE_BD72720, 19 20 ROHM_CHIP_TYPE_BD96801, 20 21 ROHM_CHIP_TYPE_BD96802, 21 22 ROHM_CHIP_TYPE_BD96805,