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Merge branch 's32g-use-a-syscon-for-gpr'

Dan Carpenter says:

====================
s32g: Use a syscon for GPR

The s32g devices have a GPR register region which holds a number of
miscellaneous registers. Currently only the stmmac/dwmac-s32.c uses
anything from there and we just add a line to the device tree to
access that GMAC_0_CTRL_STS register:

reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */

I have included the whole list of registers below.

We still have to maintain backwards compatibility to this format,
of course, but it would be better to access these registers through a
syscon. Putting all the registers together is more organized and shows
how the hardware actually is implemented.

Secondly, in some versions of this chipset those registers can only be
accessed via SCMI. It's relatively straight forward to handle this
by writing a syscon driver and registering it with of_syscon_register_regmap()
but it's complicated to deal with if the registers aren't grouped
together.

Here is the whole list of registers in the GPR region

Starting from 0x4007C000

0 Software-Triggered Faults (SW_NCF)
4 GMAC Control (GMAC_0_CTRL_STS)
28 CMU Status 1 (CMU_STATUS_REG1)
2C CMUs Status 2 (CMU_STATUS_REG2)
30 FCCU EOUT Override Clear (FCCU_EOUT_OVERRIDE_CLEAR_REG)
38 SRC POR Control (SRC_POR_CTRL_REG)
54 GPR21 (GPR21)
5C GPR23 (GPR23)
60 GPR24 Register (GPR24)
CC Debug Control (DEBUG_CONTROL)
F0 Timestamp Control (TIMESTAMP_CONTROL_REGISTER)
F4 FlexRay OS Tick Input Select (FLEXRAY_OS_TICK_INPUT_SELECT_REG)
FC GPR63 Register (GPR63)

Starting from 0x4007CA00

0 Coherency Enable for PFE Ports (PFE_COH_EN)
4 PFE EMAC Interface Mode (PFE_EMACX_INTF_SEL)
20 PFE EMACX Power Control (PFE_PWR_CTRL)
28 Error Injection on Cortex-M7 AHB and AXI Pipe (CM7_TCM_AHB_SLICE)
2C Error Injection AHBP Gasket Cortex-M7 (ERROR_INJECTION_AHBP_GASKET_CM7)
40 LLCE Subsystem Status (LLCE_STAT)
44 LLCE Power Control (LLCE_CTRL)
48 DDR Urgent Control (DDR_URGENT_CTRL)
4C FTM Global Load Control (FLXTIM_CTRL)
50 FTM LDOK Status (FLXTIM_STAT)
54 Top CMU Status (CMU_STAT)
58 Accelerator NoC No Pending Trans Status (NOC_NOPEND_TRANS)
90 SerDes RD/WD Toggle Control (PCIE_TOGGLE)
94 SerDes Toggle Done Status (PCIE_TOGGLEDONE_STAT)
E0 Generic Control 0 (GENCTRL0)
E4 Generic Control 1 (GENCTRL1)
F0 Generic Status 0 (GENSTAT0)
FC Cortex-M7 AXI Parity Error and AHBP Gasket Error Alarm (CM7_AXI_AHBP_GASKET_ERROR_ALARM)

Starting from 4007C800

4 GPR01 Register (GPR01)
30 GPR12 Register (GPR12)
58 GPR22 Register (GPR22)
70 GPR28 Register (GPR28)
74 GPR29 Register (GPR29)

Starting from 4007CB00

4 WKUP Pad Pullup/Pulldown Select (WKUP_PUS)
====================

Link: https://patch.msgid.link/cover.1769764941.git.dan.carpenter@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski d713ed0f f70f835f

+35 -6
+13
Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
··· 32 32 - description: Main GMAC registers 33 33 - description: GMAC PHY mode control register 34 34 35 + nxp,phy-sel: 36 + $ref: /schemas/types.yaml#/definitions/phandle-array 37 + items: 38 + - items: 39 + - description: phandle to the GPR syscon node 40 + - description: offset of PHY selection register 41 + description: 42 + This phandle points to the GMAC_0_CTRL_STS register which controls the 43 + GMAC_0 configuration options. The register lets you select the PHY 44 + interface and the PHY mode. It also controls if the FTM_0 or FTM_1 45 + FlexTimer Modules connect to GMAC_0. 46 + 35 47 interrupts: 36 48 maxItems: 1 37 49 ··· 86 74 compatible = "nxp,s32g2-dwmac"; 87 75 reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ 88 76 <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ 77 + nxp,phy-sel = <&gpr 0x4>; 89 78 interrupt-parent = <&gic>; 90 79 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 91 80 interrupt-names = "macirq";
+22 -6
drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
··· 11 11 #include <linux/device.h> 12 12 #include <linux/ethtool.h> 13 13 #include <linux/io.h> 14 + #include <linux/mfd/syscon.h> 14 15 #include <linux/module.h> 15 16 #include <linux/of_mdio.h> 16 17 #include <linux/of_address.h> 17 18 #include <linux/phy.h> 18 19 #include <linux/phylink.h> 19 20 #include <linux/platform_device.h> 21 + #include <linux/regmap.h> 20 22 #include <linux/stmmac.h> 21 23 22 24 #include "stmmac_platform.h" ··· 34 32 struct s32_priv_data { 35 33 void __iomem *ioaddr; 36 34 void __iomem *ctrl_sts; 35 + struct regmap *sts_regmap; 36 + unsigned int sts_offset; 37 37 struct device *dev; 38 38 phy_interface_t *intf_mode; 39 39 struct clk *tx_clk; ··· 44 40 45 41 static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac) 46 42 { 47 - writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); 43 + int ret = 0; 44 + 45 + if (gmac->ctrl_sts) 46 + writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); 47 + else 48 + ret = regmap_write(gmac->sts_regmap, gmac->sts_offset, 49 + S32_PHY_INTF_SEL_RGMII); 48 50 49 51 dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); 50 52 51 - return 0; 53 + return ret; 52 54 } 53 55 54 56 static int s32_gmac_init(struct device *dev, void *priv) ··· 135 125 "dt configuration failed\n"); 136 126 137 127 /* PHY interface mode control reg */ 138 - gmac->ctrl_sts = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 139 - if (IS_ERR(gmac->ctrl_sts)) 140 - return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts), 141 - "S32CC config region is missing\n"); 128 + gmac->sts_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, 129 + "nxp,phy-sel", 1, &gmac->sts_offset); 130 + if (gmac->sts_regmap == ERR_PTR(-EPROBE_DEFER)) 131 + return PTR_ERR(gmac->sts_regmap); 132 + if (IS_ERR(gmac->sts_regmap)) { 133 + gmac->ctrl_sts = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 134 + if (IS_ERR(gmac->ctrl_sts)) 135 + return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts), 136 + "S32CC config region is missing\n"); 137 + } 142 138 143 139 /* tx clock */ 144 140 gmac->tx_clk = devm_clk_get(&pdev->dev, "tx");