Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"One fix for a broken driver on Renesas RZ/A1 SoCs with bootloaders
that don't turn all the clks on and another fix for stm32f4 SoCs where
we have multiple drivers attaching to the same DT node"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method
clk: renesas: mstp: Support 8-bit registers for r7s72100
+24
-7
+2
-2
drivers/clk/clk-stm32f4.c
+2
-2
drivers/clk/clk-stm32f4.c
···
768
768
kfree(clks);
769
769
iounmap(base);
770
770
}
771
-
CLK_OF_DECLARE(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
772
-
CLK_OF_DECLARE(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
771
+
CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
772
+
CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
+22
-5
drivers/clk/renesas/clk-mstp.c
+22
-5
drivers/clk/renesas/clk-mstp.c
···
37
37
* @smstpcr: module stop control register
38
38
* @mstpsr: module stop status register (optional)
39
39
* @lock: protects writes to SMSTPCR
40
+
* @width_8bit: registers are 8-bit, not 32-bit
40
41
*/
41
42
struct mstp_clock_group {
42
43
struct clk_onecell_data data;
43
44
void __iomem *smstpcr;
44
45
void __iomem *mstpsr;
45
46
spinlock_t lock;
47
+
bool width_8bit;
46
48
};
47
49
48
50
/**
···
61
59
62
60
#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
63
61
62
+
static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
63
+
u32 __iomem *reg)
64
+
{
65
+
return group->width_8bit ? readb(reg) : clk_readl(reg);
66
+
}
67
+
68
+
static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
69
+
u32 __iomem *reg)
70
+
{
71
+
group->width_8bit ? writeb(val, reg) : clk_writel(val, reg);
72
+
}
73
+
64
74
static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
65
75
{
66
76
struct mstp_clock *clock = to_mstp_clock(hw);
···
84
70
85
71
spin_lock_irqsave(&group->lock, flags);
86
72
87
-
value = clk_readl(group->smstpcr);
73
+
value = cpg_mstp_read(group, group->smstpcr);
88
74
if (enable)
89
75
value &= ~bitmask;
90
76
else
91
77
value |= bitmask;
92
-
clk_writel(value, group->smstpcr);
78
+
cpg_mstp_write(group, value, group->smstpcr);
93
79
94
80
spin_unlock_irqrestore(&group->lock, flags);
95
81
···
97
83
return 0;
98
84
99
85
for (i = 1000; i > 0; --i) {
100
-
if (!(clk_readl(group->mstpsr) & bitmask))
86
+
if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
101
87
break;
102
88
cpu_relax();
103
89
}
···
128
114
u32 value;
129
115
130
116
if (group->mstpsr)
131
-
value = clk_readl(group->mstpsr);
117
+
value = cpg_mstp_read(group, group->mstpsr);
132
118
else
133
-
value = clk_readl(group->smstpcr);
119
+
value = cpg_mstp_read(group, group->smstpcr);
134
120
135
121
return !(value & BIT(clock->bit_index));
136
122
}
···
201
187
kfree(clks);
202
188
return;
203
189
}
190
+
191
+
if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
192
+
group->width_8bit = true;
204
193
205
194
for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
206
195
clks[i] = ERR_PTR(-ENOENT);