Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer:
- Support for Mobileye EyeQ6Lplus
- Cleanups and fixes
* tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits)
MIPS/mtd: Handle READY GPIO in generic NAND platform data
MIPS/input: Move RB532 button to GPIO descriptors
MIPS: validate DT bootargs before appending them
MIPS: Alchemy: Remove unused forward declaration
MAINTAINERS: Mobileye: Add EyeQ6Lplus files
MIPS: config: add eyeq6lplus_defconfig
MIPS: Add Mobileye EyeQ6Lplus evaluation board dts
MIPS: Add Mobileye EyeQ6Lplus SoC dtsi
clk: eyeq: Add Mobileye EyeQ6Lplus OLB
clk: eyeq: Adjust PLL accuracy computation
clk: eyeq: Skip post-divisor when computing PLL frequency
pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB
pinctrl: eyeq5: Use match data
reset: eyeq: Add Mobileye EyeQ6Lplus OLB
MIPS: Add Mobileye EyeQ6Lplus support
dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB
dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC
MIPS: dts: loongson64g-package: Switch to Loongson UART driver
mips: pci-mt7620: rework initialization procedure
mips: pci-mt7620: add more register init values
...
+1589
-247
+5
Documentation/devicetree/bindings/mips/mobileye.yaml
+5
Documentation/devicetree/bindings/mips/mobileye.yaml
+6
-1
Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
+6
-1
Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
···
51
51
clock-names:
52
52
const: ref
53
53
54
+
'#phy-cells':
55
+
const: 1
56
+
54
57
patternProperties:
55
58
'-pins?$':
56
59
type: object
···
313
310
properties:
314
311
'#reset-cells': false
315
312
316
-
# Only EyeQ5 has pinctrl in OLB.
313
+
# Only EyeQ5 has pinctrl and PHY in OLB.
317
314
- if:
318
315
not:
319
316
properties:
···
323
320
then:
324
321
patternProperties:
325
322
'-pins?$': false
323
+
properties:
324
+
'#phy-cells': false
326
325
327
326
examples:
328
327
- |
+208
Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq6lplus-olb.yaml
+208
Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq6lplus-olb.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq6lplus-olb.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Mobileye EyeQ6Lplus SoC system controller
8
+
9
+
maintainers:
10
+
- Benoît Monin <benoit.monin@bootlin.com>
11
+
- Grégory Clement <gregory.clement@bootlin.com>
12
+
- Théo Lebrun <theo.lebrun@bootlin.com>
13
+
- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
14
+
15
+
description:
16
+
OLB ("Other Logic Block") is a hardware block grouping smaller blocks.
17
+
Clocks, resets, pinctrl are being handled from here. EyeQ6Lplus hosts
18
+
a single instance providing 22 clocks, two reset domains and one bank
19
+
of 32 pins.
20
+
21
+
properties:
22
+
compatible:
23
+
items:
24
+
- const: mobileye,eyeq6lplus-olb
25
+
- const: syscon
26
+
27
+
reg:
28
+
maxItems: 1
29
+
30
+
'#reset-cells':
31
+
description:
32
+
First cell is reset domain index.
33
+
Second cell is reset index inside that domain.
34
+
const: 2
35
+
36
+
'#clock-cells':
37
+
const: 1
38
+
39
+
clocks:
40
+
maxItems: 1
41
+
description:
42
+
Input parent clock to all PLLs. Expected to be the main crystal.
43
+
44
+
clock-names:
45
+
const: ref
46
+
47
+
patternProperties:
48
+
'-pins?$':
49
+
type: object
50
+
description: Pin muxing configuration.
51
+
$ref: /schemas/pinctrl/pinmux-node.yaml#
52
+
additionalProperties: false
53
+
properties:
54
+
pins: true
55
+
function:
56
+
enum: [gpio, timer0, timer1, uart_ssi, spi0, uart0, timer2, timer3,
57
+
timer_ext0, spi1, timer_ext1, ext_ref_clk, mipi_ref_clk]
58
+
bias-disable: true
59
+
bias-pull-down: true
60
+
bias-pull-up: true
61
+
drive-strength: true
62
+
required:
63
+
- pins
64
+
- function
65
+
allOf:
66
+
- if:
67
+
properties:
68
+
function:
69
+
const: gpio
70
+
then:
71
+
properties:
72
+
pins:
73
+
items: # PA0 - PA31
74
+
pattern: '^(PA[1,2]?[0-9]|PA3[0,1])$'
75
+
- if:
76
+
properties:
77
+
function:
78
+
const: timer0
79
+
then:
80
+
properties:
81
+
pins:
82
+
items:
83
+
enum: [PA0, PA1]
84
+
- if:
85
+
properties:
86
+
function:
87
+
const: timer1
88
+
then:
89
+
properties:
90
+
pins:
91
+
items:
92
+
enum: [PA2, PA3]
93
+
- if:
94
+
properties:
95
+
function:
96
+
const: uart_ssi
97
+
then:
98
+
properties:
99
+
pins:
100
+
items:
101
+
enum: [PA4, PA5]
102
+
- if:
103
+
properties:
104
+
function:
105
+
const: spi0
106
+
then:
107
+
properties:
108
+
pins:
109
+
items:
110
+
enum: [PA6, PA7, PA8, PA9, PA10]
111
+
- if:
112
+
properties:
113
+
function:
114
+
const: uart0
115
+
then:
116
+
properties:
117
+
pins:
118
+
items:
119
+
enum: [PA11, PA12]
120
+
- if:
121
+
properties:
122
+
function:
123
+
const: timer2
124
+
then:
125
+
properties:
126
+
pins:
127
+
items:
128
+
enum: [PA13, PA14]
129
+
- if:
130
+
properties:
131
+
function:
132
+
const: timer3
133
+
then:
134
+
properties:
135
+
pins:
136
+
items:
137
+
enum: [PA15, PA16]
138
+
- if:
139
+
properties:
140
+
function:
141
+
const: timer_ext0
142
+
then:
143
+
properties:
144
+
pins:
145
+
items:
146
+
enum: [PA17, PA18, PA19, PA20]
147
+
- if:
148
+
properties:
149
+
function:
150
+
const: spi1
151
+
then:
152
+
properties:
153
+
pins:
154
+
items:
155
+
enum: [PA21, PA22, PA23, PA24, PA25]
156
+
- if:
157
+
properties:
158
+
function:
159
+
const: timer_ext1
160
+
then:
161
+
properties:
162
+
pins:
163
+
items:
164
+
enum: [PA26, PA27, PA28, PA29]
165
+
- if:
166
+
properties:
167
+
function:
168
+
const: ext_ref_clk
169
+
then:
170
+
properties:
171
+
pins:
172
+
items:
173
+
enum: [PA30]
174
+
- if:
175
+
properties:
176
+
function:
177
+
const: mipi_ref_clk
178
+
then:
179
+
properties:
180
+
pins:
181
+
items:
182
+
enum: [PA31]
183
+
184
+
required:
185
+
- compatible
186
+
- reg
187
+
- '#clock-cells'
188
+
- clocks
189
+
- clock-names
190
+
- '#reset-cells'
191
+
192
+
additionalProperties: false
193
+
194
+
examples:
195
+
- |
196
+
soc {
197
+
#address-cells = <2>;
198
+
#size-cells = <2>;
199
+
200
+
system-controller@e8400000 {
201
+
compatible = "mobileye,eyeq6lplus-olb", "syscon";
202
+
reg = <0 0xe8400000 0x0 0x80000>;
203
+
#reset-cells = <2>;
204
+
#clock-cells = <1>;
205
+
clocks = <&xtal>;
206
+
clock-names = "ref";
207
+
};
208
+
};
+3
-1
MAINTAINERS
+3
-1
MAINTAINERS
···
17913
17913
17914
17914
MOBILEYE MIPS SOCS
17915
17915
M: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
17916
+
M: Benoît Monin <benoit.monin@bootlin.com>
17916
17917
M: Gregory CLEMENT <gregory.clement@bootlin.com>
17917
17918
M: Théo Lebrun <theo.lebrun@bootlin.com>
17918
17919
L: linux-mips@vger.kernel.org
···
17921
17920
F: Documentation/devicetree/bindings/mips/mobileye.yaml
17922
17921
F: Documentation/devicetree/bindings/soc/mobileye/
17923
17922
F: arch/mips/boot/dts/mobileye/
17924
-
F: arch/mips/configs/eyeq5_defconfig
17923
+
F: arch/mips/configs/eyeq*_defconfig
17925
17924
F: arch/mips/mobileye/board-epm5.its.S
17926
17925
F: drivers/clk/clk-eyeq.c
17927
17926
F: drivers/pinctrl/pinctrl-eyeq5.c
17928
17927
F: drivers/reset/reset-eyeq.c
17929
17928
F: include/dt-bindings/clock/mobileye,eyeq5-clk.h
17929
+
F: include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h
17930
17930
17931
17931
MODULE SUPPORT
17932
17932
M: Luis Chamberlain <mcgrof@kernel.org>
+114
arch/mips/boot/dts/econet/en751221.dtsi
+114
arch/mips/boot/dts/econet/en751221.dtsi
···
1
1
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
/dts-v1/;
3
3
4
+
#include <dt-bindings/clock/econet,en751221-scu.h>
5
+
4
6
/ {
5
7
compatible = "econet,en751221";
6
8
#address-cells = <1>;
···
32
30
#interrupt-cells = <1>;
33
31
};
34
32
33
+
chip_scu: syscon@1fa20000 {
34
+
compatible = "econet,en751221-chip-scu", "syscon";
35
+
reg = <0x1fa20000 0x388>;
36
+
};
37
+
38
+
pcie_phy1: pcie-phy@1fac0000 {
39
+
compatible = "econet,en751221-pcie-gen2";
40
+
reg = <0x1fac0000 0x1000>;
41
+
#phy-cells = <0>;
42
+
};
43
+
44
+
pcie_phy0: pcie-phy@1faf2000 {
45
+
compatible = "econet,en751221-pcie-gen1";
46
+
reg = <0x1faf2000 0x1000>;
47
+
#phy-cells = <0>;
48
+
};
49
+
50
+
scuclk: clock-controller@1fb00000 {
51
+
compatible = "econet,en751221-scu";
52
+
reg = <0x1fb00000 0x970>;
53
+
#clock-cells = <1>;
54
+
#reset-cells = <1>;
55
+
};
56
+
35
57
intc: interrupt-controller@1fb40000 {
36
58
compatible = "econet,en751221-intc";
37
59
reg = <0x1fb40000 0x100>;
···
65
39
interrupt-controller;
66
40
#interrupt-cells = <1>;
67
41
econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
42
+
};
43
+
44
+
pciecfg: pciecfg@1fb80000 {
45
+
compatible = "mediatek,generic-pciecfg", "syscon";
46
+
reg = <0x1fb80000 0x1000>;
47
+
};
48
+
49
+
pcie0: pcie@1fb81000 {
50
+
compatible = "econet,en7528-pcie";
51
+
device_type = "pci";
52
+
reg = <0x1fb81000 0x1000>;
53
+
reg-names = "port0";
54
+
linux,pci-domain = <0>;
55
+
#address-cells = <3>;
56
+
#size-cells = <2>;
57
+
interrupt-parent = <&intc>;
58
+
interrupts = <23>;
59
+
interrupt-names = "pcie_irq";
60
+
clocks = <&scuclk EN751221_CLK_PCIE>;
61
+
clock-names = "sys_ck0";
62
+
phys = <&pcie_phy0>;
63
+
phy-names = "pcie-phy0";
64
+
bus-range = <0x00 0xff>;
65
+
ranges = <0x01000000 0 0x00000000 0x1f600000 0 0x00008000>,
66
+
<0x82000000 0 0x20000000 0x20000000 0 0x08000000>;
67
+
status = "disabled";
68
+
69
+
#interrupt-cells = <1>;
70
+
interrupt-map-mask = <0 0 0 7>;
71
+
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
72
+
<0 0 0 2 &pcie_intc0 1>,
73
+
<0 0 0 3 &pcie_intc0 2>,
74
+
<0 0 0 4 &pcie_intc0 3>;
75
+
76
+
pcie_intc0: interrupt-controller {
77
+
interrupt-controller;
78
+
#address-cells = <0>;
79
+
#interrupt-cells = <1>;
80
+
};
81
+
82
+
slot0: pcie@0,0 {
83
+
reg = <0x0000 0 0 0 0>;
84
+
device_type = "pci";
85
+
#address-cells = <3>;
86
+
#size-cells = <2>;
87
+
ranges;
88
+
};
89
+
};
90
+
91
+
pcie1: pcie@1fb83000 {
92
+
compatible = "econet,en7528-pcie";
93
+
device_type = "pci";
94
+
reg = <0x1fb83000 0x1000>;
95
+
reg-names = "port1";
96
+
linux,pci-domain = <1>;
97
+
#address-cells = <3>;
98
+
#size-cells = <2>;
99
+
interrupt-parent = <&intc>;
100
+
interrupts = <24>;
101
+
interrupt-names = "pcie_irq";
102
+
clocks = <&scuclk EN751221_CLK_PCIE>;
103
+
clock-names = "sys_ck1";
104
+
phys = <&pcie_phy1>;
105
+
phy-names = "pcie-phy1";
106
+
bus-range = <0x00 0xff>;
107
+
ranges = <0x81000000 0 0x00000000 0x1f608000 0 0x00008000>,
108
+
<0x82000000 0 0x28000000 0x28000000 0 0x08000000>;
109
+
status = "disabled";
110
+
111
+
#interrupt-cells = <1>;
112
+
interrupt-map-mask = <0 0 0 7>;
113
+
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
114
+
<0 0 0 2 &pcie_intc1 1>,
115
+
<0 0 0 3 &pcie_intc1 2>,
116
+
<0 0 0 4 &pcie_intc1 3>;
117
+
118
+
pcie_intc1: interrupt-controller {
119
+
interrupt-controller;
120
+
#address-cells = <0>;
121
+
#interrupt-cells = <1>;
122
+
};
123
+
124
+
slot1: pcie@1,0 {
125
+
reg = <0x0800 0 0 0 0>;
126
+
#address-cells = <3>;
127
+
#size-cells = <2>;
128
+
ranges;
129
+
};
68
130
};
69
131
70
132
uart: serial@1fbf0000 {
+21
arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
+21
arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
···
17
17
linux,usable-memory-range = <0x00020000 0x1bfe0000>;
18
18
};
19
19
};
20
+
21
+
&pcie0 {
22
+
status = "okay";
23
+
};
24
+
&slot0 {
25
+
wifi@0,0 {
26
+
/* MT7612E */
27
+
compatible = "mediatek,mt76";
28
+
reg = <0x0000 0 0 0 0>;
29
+
};
30
+
};
31
+
&pcie1 {
32
+
status = "okay";
33
+
};
34
+
&slot1 {
35
+
wifi@0,0 {
36
+
/* MT7592 */
37
+
compatible = "mediatek,mt76";
38
+
reg = <0x0000 0 0 0 0>;
39
+
};
40
+
};
+2
-2
arch/mips/boot/dts/loongson/loongson64g-package.dtsi
+2
-2
arch/mips/boot/dts/loongson/loongson64g-package.dtsi
···
40
40
};
41
41
42
42
cpu_uart0: serial@1fe00100 {
43
-
compatible = "ns16550a";
43
+
compatible = "loongson,ls3a4000-uart", "loongson,ls2k1500-uart", "ns16550a";
44
44
reg = <0 0x1fe00100 0x10>;
45
45
clock-frequency = <100000000>;
46
46
interrupt-parent = <&liointc>;
···
50
50
51
51
cpu_uart1: serial@1fe00110 {
52
52
status = "disabled";
53
-
compatible = "ns16550a";
53
+
compatible = "loongson,ls3a4000-uart", "loongson,ls2k1500-uart", "ns16550a";
54
54
reg = <0 0x1fe00110 0x10>;
55
55
clock-frequency = <100000000>;
56
56
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
+1
arch/mips/boot/dts/mobileye/Makefile
+1
arch/mips/boot/dts/mobileye/Makefile
+26
arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
+26
arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
···
29
29
label = "U60";
30
30
};
31
31
};
32
+
33
+
&macb0 {
34
+
phy-mode = "sgmii";
35
+
phy-handle = <&macb0_phy>;
36
+
37
+
mdio {
38
+
#address-cells = <1>;
39
+
#size-cells = <0>;
40
+
macb0_phy: ethernet-phy@e {
41
+
reg = <0xe>;
42
+
};
43
+
};
44
+
};
45
+
46
+
&macb1 {
47
+
phy-mode = "rgmii-id";
48
+
phy-handle = <&macb1_phy>;
49
+
50
+
mdio {
51
+
#address-cells = <1>;
52
+
#size-cells = <0>;
53
+
macb1_phy: ethernet-phy@e {
54
+
reg = <0xe>;
55
+
};
56
+
};
57
+
};
+45
arch/mips/boot/dts/mobileye/eyeq5.dtsi
+45
arch/mips/boot/dts/mobileye/eyeq5.dtsi
···
77
77
serial0 = &uart0;
78
78
serial1 = &uart1;
79
79
serial2 = &uart2;
80
+
ethernet0 = &macb0;
81
+
ethernet1 = &macb1;
80
82
};
81
83
82
84
cpu_intc: interrupt-controller {
···
233
231
#clock-cells = <1>;
234
232
clocks = <&xtal>;
235
233
clock-names = "ref";
234
+
#phy-cells = <1>;
236
235
};
237
236
238
237
gic: interrupt-controller@140000 {
···
308
305
#interrupt-cells = <2>;
309
306
resets = <&olb 0 26>;
310
307
};
308
+
309
+
iocu-bus {
310
+
compatible = "simple-bus";
311
+
#address-cells = <2>;
312
+
#size-cells = <2>;
313
+
ranges;
314
+
dma-coherent;
315
+
dma-ranges = <0x10 0x00000000 0x0 0x0 0x10 0>;
316
+
317
+
macb0: ethernet@2a00000 {
318
+
compatible = "mobileye,eyeq5-gem";
319
+
reg = <0x0 0x02a00000 0x0 0x4000>;
320
+
interrupt-parent = <&gic>;
321
+
/* One interrupt per queue */
322
+
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>,
323
+
<GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>,
324
+
<GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>,
325
+
<GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
326
+
clock-names = "pclk", "hclk", "tsu_clk";
327
+
clocks = <&pclk>, <&pclk>, <&tsu_clk>;
328
+
nvmem-cells = <ð0_mac>;
329
+
nvmem-cell-names = "mac-address";
330
+
phys = <&olb 0>;
331
+
};
332
+
333
+
macb1: ethernet@2b00000 {
334
+
compatible = "mobileye,eyeq5-gem";
335
+
reg = <0x0 0x02b00000 0x0 0x4000>;
336
+
interrupt-parent = <&gic>;
337
+
/* One interrupt per queue */
338
+
interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
339
+
<GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
340
+
<GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
341
+
<GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
342
+
clock-names = "pclk", "hclk", "tsu_clk";
343
+
clocks = <&pclk>, <&pclk>, <&tsu_clk>;
344
+
nvmem-cells = <ð1_mac>;
345
+
nvmem-cell-names = "mac-address";
346
+
phys = <&olb 1>;
347
+
};
348
+
};
349
+
311
350
};
312
351
};
313
352
+103
arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts
+103
arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Copyright 2025 Mobileye Vision Technologies Ltd.
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "eyeq6lplus.dtsi"
9
+
10
+
/ {
11
+
compatible = "mobileye,eyeq6lplus-epm6", "mobileye,eyeq6lplus";
12
+
model = "Mobileye EyeQ6Lplus Evaluation board";
13
+
14
+
aliases {
15
+
serial0 = &uart0;
16
+
};
17
+
18
+
chosen {
19
+
stdout-path = "serial0:921600n8";
20
+
};
21
+
22
+
memory@0 {
23
+
device_type = "memory";
24
+
reg = <0x1 0x00000000 0x0 0x80000000>;
25
+
};
26
+
27
+
reserved-memory {
28
+
#address-cells = <2>;
29
+
#size-cells = <2>;
30
+
ranges;
31
+
32
+
/* These reserved memory regions are also defined in bootmanager
33
+
* for configuring inbound translation for BARS, don't change
34
+
* these without syncing with bootmanager
35
+
*/
36
+
mhm_reserved_0: the-mhm-reserved-0 {
37
+
reg = <0x1 0x00000000 0x0 0x0000800>;
38
+
};
39
+
bm_logs_reserved: bm-logs-reserved {
40
+
reg = <0x1 0x0000800 0x0 0x000f800>;
41
+
};
42
+
shmem0_reserved: shmem@804000000 {
43
+
reg = <0x1 0x04000000 0x0 0x1000000>;
44
+
};
45
+
shmem1_reserved: shmem@805000000 {
46
+
reg = <0x1 0x05000000 0x0 0x1000000>;
47
+
};
48
+
mini_coredump0_reserved: mini-coredump0@806200000 {
49
+
reg = <0x1 0x06200000 0x0 0x100000>;
50
+
};
51
+
mailbox_reserved: mailbox-reserved {
52
+
reg = <0x1 0x06300000 0x0 0x000300>;
53
+
};
54
+
sys_logs_reserved: sys-logs-reserved {
55
+
reg = <0x1 0x10000000 0x0 0x800000>;
56
+
};
57
+
csl_policy_logs_reserved: csl-policy-logs-reserved {
58
+
reg = <0x1 0x10800000 0x0 0x10000>;
59
+
};
60
+
};
61
+
};
62
+
63
+
&ospi {
64
+
status = "okay";
65
+
flash@0 {
66
+
compatible = "spi-nand";
67
+
reg = <0>;
68
+
spi-max-frequency = <40000000>;
69
+
cdns,read-delay = <0>;
70
+
cdns,tshsl-ns = <400>;
71
+
cdns,tsd2d-ns = <120>;
72
+
cdns,tchsh-ns = <40>;
73
+
cdns,tslch-ns = <20>;
74
+
spi-tx-bus-width = <1>;
75
+
spi-rx-bus-width = <8>;
76
+
};
77
+
};
78
+
79
+
&spi0 {
80
+
pinctrl-0 = <&spi0_pins>;
81
+
pinctrl-names = "default";
82
+
status = "okay";
83
+
};
84
+
85
+
&spi1 {
86
+
pinctrl-0 = <&spi1_pins>;
87
+
pinctrl-names = "default";
88
+
status = "okay";
89
+
};
90
+
91
+
&uart0 {
92
+
pinctrl-0 = <&uart0_pins>;
93
+
pinctrl-names = "default";
94
+
status = "okay";
95
+
};
96
+
97
+
&i2c0 {
98
+
status = "okay";
99
+
};
100
+
101
+
&i2c1 {
102
+
status = "okay";
103
+
};
+84
arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi
+84
arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
3
+
&olb {
4
+
timer0_pins: timer0-pins {
5
+
function = "timer0";
6
+
pins = "PA0", "PA1";
7
+
};
8
+
timer1_pins: timer1-pins {
9
+
function = "timer1";
10
+
pins = "PA2", "PA3";
11
+
};
12
+
uart_ssi_pins: uart-ssi-pins {
13
+
function = "uart_ssi";
14
+
pins = "PA4", "PA5";
15
+
};
16
+
spi0_pins: spi0-pins {
17
+
function = "spi0";
18
+
pins = "PA6", "PA7", "PA8", "PA9";
19
+
};
20
+
uart0_pins: uart0-pins {
21
+
function = "uart0";
22
+
pins = "PA11", "PA12";
23
+
};
24
+
timer2_pins: timer2-pins {
25
+
function = "timer2";
26
+
pins = "PA13", "PA14";
27
+
};
28
+
timer3_pins: timer3-pins {
29
+
function = "timer3";
30
+
pins = "PA15", "PA16";
31
+
};
32
+
timer_ext0_pins: timer-ext0-pins {
33
+
function = "timer_ext0";
34
+
pins = "PA17", "PA18", "PA19", "PA20";
35
+
};
36
+
timer_ext0_input_a_pins: timer-ext0-input-a-pins {
37
+
function = "timer_ext0";
38
+
pins = "PA17";
39
+
};
40
+
pps0_pins: pps0-pins {
41
+
function = "timer_ext0";
42
+
pins = "PA17";
43
+
};
44
+
timer_ext0_input_b_pins: timer-ext0-input-b-pins {
45
+
function = "timer_ext0";
46
+
pins = "PA18";
47
+
};
48
+
timer_ext0_output_pins: timer-ext0-output-pins {
49
+
function = "timer_ext0";
50
+
pins = "PA19", "PA20";
51
+
};
52
+
spi1_pins: spi1-pins {
53
+
function = "spi1";
54
+
pins = "PA21", "PA22", "PA23", "PA24";
55
+
};
56
+
spi1_reduced_pins: spi1-reduced-pins {
57
+
function = "spi1";
58
+
pins = "PA21", "PA22", "PA23";
59
+
};
60
+
timer_ext1_pins: timer-ext1-pins {
61
+
function = "timer_ext1";
62
+
pins = "PA26", "PA27", "PA28", "PA29";
63
+
};
64
+
timer_ext1_input_a_pins: timer-ext1-input-a-pins {
65
+
function = "timer_ext1";
66
+
pins = "PA26";
67
+
};
68
+
timer_ext1_input_b_pins: timer-ext1-input-b-pins {
69
+
function = "timer_ext1";
70
+
pins = "PA27";
71
+
};
72
+
timer_ext1_output_pins: timer-ext1-output-pins {
73
+
function = "timer_ext1";
74
+
pins = "PA28", "PA29";
75
+
};
76
+
ext_ref_clk_pins: ext-ref-clk-pins {
77
+
function = "ext_ref_clk";
78
+
pins = "PA30";
79
+
};
80
+
mipi_ref_clk_pins: mipi-ref-clk-pins {
81
+
function = "mipi_ref_clk";
82
+
pins = "PA31";
83
+
};
84
+
};
+170
arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi
+170
arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
/*
3
+
* Copyright 2025 Mobileye Vision Technologies Ltd.
4
+
*/
5
+
6
+
#include <dt-bindings/interrupt-controller/mips-gic.h>
7
+
8
+
#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h>
9
+
10
+
/ {
11
+
#address-cells = <2>;
12
+
#size-cells = <2>;
13
+
cpus {
14
+
#address-cells = <1>;
15
+
#size-cells = <0>;
16
+
cpu@0 {
17
+
device_type = "cpu";
18
+
compatible = "img,i6500";
19
+
reg = <0>;
20
+
clocks = <&olb EQ6LPC_CPU_OCC>;
21
+
};
22
+
};
23
+
24
+
cpu_intc: interrupt-controller {
25
+
compatible = "mti,cpu-interrupt-controller";
26
+
interrupt-controller;
27
+
#address-cells = <0>;
28
+
#interrupt-cells = <1>;
29
+
};
30
+
31
+
coherency-manager {
32
+
compatible = "mobileye,eyeq6-cm";
33
+
};
34
+
35
+
xtal: clock-30000000 {
36
+
compatible = "fixed-clock";
37
+
#clock-cells = <0>;
38
+
clock-frequency = <30000000>;
39
+
};
40
+
41
+
soc: soc {
42
+
compatible = "simple-bus";
43
+
#address-cells = <2>;
44
+
#size-cells = <2>;
45
+
ranges;
46
+
47
+
olb: system-controller@e8400000 {
48
+
compatible = "mobileye,eyeq6lplus-olb", "syscon";
49
+
reg = <0 0xe8400000 0x0 0x80000>;
50
+
#reset-cells = <2>;
51
+
#clock-cells = <1>;
52
+
clocks = <&xtal>;
53
+
clock-names = "ref";
54
+
};
55
+
56
+
ospi: spi@e8800000 {
57
+
compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor";
58
+
#address-cells = <1>;
59
+
#size-cells = <0>;
60
+
reg = <0 0xe8800000 0x0 0x100000>,
61
+
<0 0xb0000000 0x0 0x30000000>;
62
+
interrupt-parent = <&gic>;
63
+
interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>;
64
+
cdns,fifo-depth = <128>;
65
+
cdns,fifo-width = <4>;
66
+
cdns,trigger-address = <0x00000000>;
67
+
clocks = <&olb EQ6LPC_PER_OSPI>;
68
+
status = "disabled";
69
+
};
70
+
71
+
spi0: spi@eac0d000 {
72
+
compatible = "snps,dw-apb-ssi";
73
+
reg = <0 0xeac0d000 0x0 0x1000>;
74
+
clocks = <&olb EQ6LPC_PER_SPI>;
75
+
interrupt-parent = <&gic>;
76
+
interrupts = <GIC_SHARED 11 IRQ_TYPE_LEVEL_HIGH>;
77
+
resets = <&olb 0 0>;
78
+
reset-names = "spi";
79
+
#address-cells = <1>;
80
+
#size-cells = <0>;
81
+
status = "disabled";
82
+
};
83
+
84
+
spi1: spi@eac0e000 {
85
+
compatible = "snps,dw-apb-ssi";
86
+
reg = <0 0xeac0e000 0x0 0x1000>;
87
+
spi-slave;
88
+
clocks = <&olb EQ6LPC_PER_SPI>;
89
+
interrupt-parent = <&gic>;
90
+
interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
91
+
resets = <&olb 0 1>;
92
+
reset-names = "spi";
93
+
#address-cells = <0>;
94
+
#size-cells = <0>;
95
+
status = "disabled";
96
+
};
97
+
98
+
uart0: serial@eac10000 {
99
+
compatible = "snps,dw-apb-uart";
100
+
reg-shift = <2>;
101
+
reg-io-width = <4>;
102
+
clocks = <&olb EQ6LPC_PER_UART>;
103
+
clock-frequency = <15625000>;
104
+
reg = <0 0xeac10000 0x0 0x1000>;
105
+
interrupt-parent = <&gic>;
106
+
interrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>;
107
+
resets = <&olb 0 2>;
108
+
status = "disabled";
109
+
};
110
+
111
+
i2c0: i2c@eac11000 {
112
+
compatible = "mobileye,eyeq6lplus-i2c", "snps,designware-i2c";
113
+
reg = <0 0xeac11000 0x0 0x1000>;
114
+
interrupt-parent = <&gic>;
115
+
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
116
+
clock-frequency = <400000>;
117
+
clocks = <&olb EQ6LPC_PER_I2C_SER>;
118
+
resets = <&olb 0 3>;
119
+
i2c-sda-hold-time-ns = <50>;
120
+
status = "disabled";
121
+
};
122
+
123
+
i2c1: i2c@eac12000 {
124
+
compatible = "mobileye,eyeq6lplus-i2c", "snps,designware-i2c";
125
+
reg = <0 0xeac12000 0x0 0x1000>;
126
+
interrupt-parent = <&gic>;
127
+
interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
128
+
clock-frequency = <400000>;
129
+
clocks = <&olb EQ6LPC_PER_I2C_SER>;
130
+
resets = <&olb 0 4>;
131
+
i2c-sda-hold-time-ns = <50>;
132
+
status = "disabled";
133
+
};
134
+
135
+
gpio: gpio@eac14000 {
136
+
compatible = "snps,dw-apb-gpio";
137
+
reg = <0x0 0xeac14000 0x0 0x1000>;
138
+
#address-cells = <1>;
139
+
#size-cells = <0>;
140
+
resets = <&olb 0 13>;
141
+
porta: gpio-port@0 {
142
+
compatible = "snps,dw-apb-gpio-port";
143
+
gpio-controller;
144
+
#gpio-cells = <2>;
145
+
snps,nr-gpios = <32>;
146
+
gpio-ranges = <&olb 0 0 32>;
147
+
reg = <0>;
148
+
interrupt-controller;
149
+
#interrupt-cells = <2>;
150
+
interrupt-parent = <&gic>;
151
+
interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
152
+
};
153
+
};
154
+
155
+
gic: interrupt-controller@f0920000 {
156
+
compatible = "mti,gic";
157
+
reg = <0x0 0xf0920000 0x0 0x20000>;
158
+
interrupt-controller;
159
+
#interrupt-cells = <3>;
160
+
interrupt-parent = <&cpu_intc>;
161
+
timer {
162
+
compatible = "mti,gic-timer";
163
+
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
164
+
clocks = <&olb EQ6LPC_CPU_OCC>;
165
+
};
166
+
};
167
+
};
168
+
};
169
+
170
+
#include "eyeq6lplus-pins.dtsi"
+117
arch/mips/configs/eyeq6lplus_defconfig
+117
arch/mips/configs/eyeq6lplus_defconfig
···
1
+
CONFIG_SYSVIPC=y
2
+
CONFIG_NO_HZ_IDLE=y
3
+
CONFIG_HIGH_RES_TIMERS=y
4
+
CONFIG_BPF_SYSCALL=y
5
+
CONFIG_TASKSTATS=y
6
+
CONFIG_IKCONFIG=y
7
+
CONFIG_IKCONFIG_PROC=y
8
+
CONFIG_MEMCG=y
9
+
CONFIG_BLK_CGROUP=y
10
+
CONFIG_CFS_BANDWIDTH=y
11
+
CONFIG_RT_GROUP_SCHED=y
12
+
CONFIG_CGROUP_PIDS=y
13
+
CONFIG_CGROUP_FREEZER=y
14
+
CONFIG_CPUSETS=y
15
+
CONFIG_CGROUP_DEVICE=y
16
+
CONFIG_CGROUP_CPUACCT=y
17
+
CONFIG_NAMESPACES=y
18
+
CONFIG_USER_NS=y
19
+
CONFIG_SCHED_AUTOGROUP=y
20
+
CONFIG_BLK_DEV_INITRD=y
21
+
CONFIG_EXPERT=y
22
+
CONFIG_EYEQ=y
23
+
CONFIG_MACH_EYEQ6LPLUS=y
24
+
CONFIG_MIPS_CPS=y
25
+
CONFIG_CPU_HAS_MSA=y
26
+
CONFIG_NR_CPUS=16
27
+
CONFIG_MIPS_RAW_APPENDED_DTB=y
28
+
CONFIG_JUMP_LABEL=y
29
+
CONFIG_PAGE_SIZE_16KB=y
30
+
CONFIG_COMPAT_32BIT_TIME=y
31
+
CONFIG_MODULES=y
32
+
CONFIG_MODULE_UNLOAD=y
33
+
CONFIG_TRIM_UNUSED_KSYMS=y
34
+
# CONFIG_COMPAT_BRK is not set
35
+
CONFIG_USERFAULTFD=y
36
+
CONFIG_NET=y
37
+
CONFIG_PACKET=y
38
+
CONFIG_UNIX=y
39
+
CONFIG_INET=y
40
+
CONFIG_IP_PNP=y
41
+
CONFIG_IP_PNP_DHCP=y
42
+
CONFIG_NETFILTER=y
43
+
CONFIG_CAN=y
44
+
CONFIG_PCI=y
45
+
CONFIG_PCI_MSI=y
46
+
CONFIG_PCI_DEBUG=y
47
+
CONFIG_PCI_ENDPOINT=y
48
+
CONFIG_DEVTMPFS=y
49
+
CONFIG_DEVTMPFS_MOUNT=y
50
+
CONFIG_CONNECTOR=y
51
+
CONFIG_MTD=y
52
+
CONFIG_MTD_SPI_NAND=y
53
+
CONFIG_MTD_UBI=y
54
+
CONFIG_MTD_UBI_BLOCK=y
55
+
CONFIG_SCSI=y
56
+
CONFIG_NETDEVICES=y
57
+
CONFIG_MACVLAN=y
58
+
CONFIG_IPVLAN=y
59
+
CONFIG_MACB=y
60
+
CONFIG_MARVELL_PHY=y
61
+
CONFIG_MICREL_PHY=y
62
+
CONFIG_CAN_M_CAN=y
63
+
CONFIG_SERIAL_8250=y
64
+
CONFIG_SERIAL_8250_CONSOLE=y
65
+
CONFIG_SERIAL_8250_DW=y
66
+
CONFIG_HW_RANDOM=y
67
+
CONFIG_I2C=y
68
+
CONFIG_I2C_CHARDEV=y
69
+
CONFIG_I2C_DESIGNWARE_CORE=y
70
+
CONFIG_SPI=y
71
+
CONFIG_SPI_CADENCE_QUADSPI=y
72
+
CONFIG_SPI_DESIGNWARE=y
73
+
CONFIG_SPI_DW_MMIO=y
74
+
CONFIG_SPI_SPIDEV=y
75
+
CONFIG_SPI_SLAVE=y
76
+
# CONFIG_PTP_1588_CLOCK is not set
77
+
CONFIG_PINCTRL=y
78
+
CONFIG_GPIOLIB=y
79
+
CONFIG_GPIO_DWAPB=y
80
+
CONFIG_MFD_SYSCON=y
81
+
CONFIG_HID_A4TECH=y
82
+
CONFIG_HID_BELKIN=y
83
+
CONFIG_HID_CHERRY=y
84
+
CONFIG_HID_CYPRESS=y
85
+
CONFIG_HID_EZKEY=y
86
+
CONFIG_HID_ITE=y
87
+
CONFIG_HID_KENSINGTON=y
88
+
CONFIG_HID_REDRAGON=y
89
+
CONFIG_HID_MICROSOFT=y
90
+
CONFIG_HID_MONTEREY=y
91
+
CONFIG_MMC=y
92
+
CONFIG_MMC_SDHCI=y
93
+
CONFIG_MMC_SDHCI_PLTFM=y
94
+
CONFIG_MMC_SDHCI_CADENCE=y
95
+
# CONFIG_IOMMU_SUPPORT is not set
96
+
CONFIG_RESET_CONTROLLER=y
97
+
# CONFIG_NVMEM is not set
98
+
CONFIG_EXT4_FS=y
99
+
CONFIG_EXT4_FS_POSIX_ACL=y
100
+
CONFIG_EXT4_FS_SECURITY=y
101
+
CONFIG_FS_ENCRYPTION=y
102
+
CONFIG_FUSE_FS=y
103
+
CONFIG_CUSE=y
104
+
CONFIG_MSDOS_FS=y
105
+
CONFIG_VFAT_FS=y
106
+
CONFIG_TMPFS=y
107
+
CONFIG_TMPFS_POSIX_ACL=y
108
+
CONFIG_UBIFS_FS=y
109
+
CONFIG_NFS_FS=y
110
+
CONFIG_NFS_V3_ACL=y
111
+
CONFIG_NFS_V4=y
112
+
CONFIG_NFS_V4_2=y
113
+
CONFIG_ROOT_NFS=y
114
+
CONFIG_FRAME_WARN=1024
115
+
CONFIG_DEBUG_FS=y
116
+
# CONFIG_RCU_TRACE is not set
117
+
# CONFIG_FTRACE is not set
-1
arch/mips/configs/ip32_defconfig
-1
arch/mips/configs/ip32_defconfig
-1
arch/mips/configs/lemote2f_defconfig
-1
arch/mips/configs/lemote2f_defconfig
-1
arch/mips/configs/malta_qemu_32r6_defconfig
-1
arch/mips/configs/malta_qemu_32r6_defconfig
-1
arch/mips/configs/maltaaprp_defconfig
-1
arch/mips/configs/maltaaprp_defconfig
-1
arch/mips/configs/maltasmvp_defconfig
-1
arch/mips/configs/maltasmvp_defconfig
-1
arch/mips/configs/maltasmvp_eva_defconfig
-1
arch/mips/configs/maltasmvp_eva_defconfig
-1
arch/mips/configs/maltaup_defconfig
-1
arch/mips/configs/maltaup_defconfig
+11
-5
arch/mips/dec/ecc-berr.c
+11
-5
arch/mips/dec/ecc-berr.c
···
5
5
* 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
6
6
* 5900/260 (KN05) systems.
7
7
*
8
-
* Copyright (c) 2003, 2005 Maciej W. Rozycki
8
+
* Copyright (c) 2003, 2005, 2026 Maciej W. Rozycki
9
9
*/
10
10
11
11
#include <linux/init.h>
12
12
#include <linux/interrupt.h>
13
13
#include <linux/kernel.h>
14
+
#include <linux/ratelimit.h>
14
15
#include <linux/sched.h>
15
16
#include <linux/types.h>
16
17
···
52
51
static const char overstr[] = "overrun";
53
52
static const char eccstr[] = "ECC error";
54
53
54
+
static DEFINE_RATELIMIT_STATE(rs,
55
+
DEFAULT_RATELIMIT_INTERVAL,
56
+
DEFAULT_RATELIMIT_BURST);
57
+
55
58
const char *kind, *agent, *cycle, *event;
56
59
const char *status = "", *xbit = "", *fmt = "";
57
60
unsigned long address;
···
75
70
76
71
if (!(erraddr & KN0X_EAR_VALID)) {
77
72
/* No idea what happened. */
78
-
printk(KERN_ALERT "Unidentified bus error %s\n", kind);
73
+
pr_alert_ratelimited("Unidentified bus error %s\n", kind);
79
74
return action;
80
75
}
81
76
···
185
180
}
186
181
}
187
182
188
-
if (action != MIPS_BE_FIXUP)
183
+
if (action != MIPS_BE_FIXUP && __ratelimit(&rs)) {
189
184
printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
190
185
kind, agent, cycle, event, address);
191
186
192
-
if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
193
-
printk(fmt, " ECC syndrome ", syn, status, xbit, i);
187
+
if (erraddr & KN0X_EAR_ECCERR)
188
+
printk(fmt, " ECC syndrome ", syn, status, xbit, i);
189
+
}
194
190
195
191
return action;
196
192
}
+3
-3
arch/mips/dec/kn01-berr.c
+3
-3
arch/mips/dec/kn01-berr.c
···
4
4
* and 2100 (KN01) systems equipped with parity error detection
5
5
* logic.
6
6
*
7
-
* Copyright (c) 2005 Maciej W. Rozycki
7
+
* Copyright (c) 2005, 2026 Maciej W. Rozycki
8
8
*/
9
9
10
10
#include <linux/init.h>
···
134
134
action = MIPS_BE_FIXUP;
135
135
136
136
if (action != MIPS_BE_FIXUP)
137
-
printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
138
-
kind, agent, cycle, event, address);
137
+
pr_alert_ratelimited("Bus error %s: %s %s %s at %#010lx\n",
138
+
kind, agent, cycle, event, address);
139
139
140
140
return action;
141
141
}
+16
-10
arch/mips/dec/kn02xa-berr.c
+16
-10
arch/mips/dec/kn02xa-berr.c
···
6
6
* DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50
7
7
* (KN04-CA) systems.
8
8
*
9
-
* Copyright (c) 2005 Maciej W. Rozycki
9
+
* Copyright (c) 2005, 2026 Maciej W. Rozycki
10
10
*/
11
11
12
12
#include <linux/init.h>
13
13
#include <linux/interrupt.h>
14
14
#include <linux/kernel.h>
15
+
#include <linux/ratelimit.h>
15
16
#include <linux/types.h>
16
17
17
18
#include <asm/addrspace.h>
···
51
50
static const char paritystr[] = "parity error";
52
51
static const char lanestat[][4] = { " OK", "BAD" };
53
52
53
+
static DEFINE_RATELIMIT_STATE(rs,
54
+
DEFAULT_RATELIMIT_INTERVAL,
55
+
DEFAULT_RATELIMIT_BURST);
56
+
54
57
const char *kind, *agent, *cycle, *event;
55
58
unsigned long address;
56
59
···
84
79
if (is_fixup)
85
80
action = MIPS_BE_FIXUP;
86
81
87
-
if (action != MIPS_BE_FIXUP)
82
+
if (action != MIPS_BE_FIXUP && __ratelimit(&rs)) {
88
83
printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
89
84
kind, agent, cycle, event, address);
90
85
91
-
if (action != MIPS_BE_FIXUP && address < 0x10000000)
92
-
printk(KERN_ALERT " Byte lane status %#3x -- "
93
-
"#3: %s, #2: %s, #1: %s, #0: %s\n",
94
-
(mer & KN02XA_MER_BYTERR) >> 8,
95
-
lanestat[(mer & KN02XA_MER_BYTERR_3) != 0],
96
-
lanestat[(mer & KN02XA_MER_BYTERR_2) != 0],
97
-
lanestat[(mer & KN02XA_MER_BYTERR_1) != 0],
98
-
lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]);
86
+
if (address < 0x10000000)
87
+
printk(KERN_ALERT " Byte lane status %#3x -- "
88
+
"#3: %s, #2: %s, #1: %s, #0: %s\n",
89
+
(mer & KN02XA_MER_BYTERR) >> 8,
90
+
lanestat[(mer & KN02XA_MER_BYTERR_3) != 0],
91
+
lanestat[(mer & KN02XA_MER_BYTERR_2) != 0],
92
+
lanestat[(mer & KN02XA_MER_BYTERR_1) != 0],
93
+
lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]);
94
+
}
99
95
100
96
return action;
101
97
}
+2
arch/mips/econet/Kconfig
+2
arch/mips/econet/Kconfig
-2
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
-2
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
-1
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
-1
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
+1
-1
arch/mips/kernel/r4k-bugs64.c
+1
-1
arch/mips/kernel/r4k-bugs64.c
···
91
91
".set pop"
92
92
: "=&r" (lv1), "=r" (lw)
93
93
: "r" (m1), "r" (m2), "r" (s), "I" (0)
94
-
: "hi", "lo", "$0");
94
+
: "hi", "lo");
95
95
/* We have to use single integers for m1 and m2 and a double
96
96
* one for p to be sure the mulsidi3 gcc's RTL multiplication
97
97
* instruction has the workaround applied. Older versions of
+4
arch/mips/kernel/setup.c
+4
arch/mips/kernel/setup.c
···
31
31
#include <linux/of_fdt.h>
32
32
#include <linux/dmi.h>
33
33
#include <linux/crash_dump.h>
34
+
#include <linux/string.h>
34
35
35
36
#include <asm/addrspace.h>
36
37
#include <asm/bootinfo.h>
···
542
541
543
542
p = of_get_flat_dt_prop(node, "bootargs", &l);
544
543
if (p != NULL && l > 0) {
544
+
if (strnlen(p, l) >= l)
545
+
return 1;
546
+
545
547
bootcmdline_append(p, min(l, COMMAND_LINE_SIZE));
546
548
*dt_bootargs = true;
547
549
}
+3
arch/mips/mobileye/Kconfig
+3
arch/mips/mobileye/Kconfig
+1
arch/mips/mobileye/Platform
+1
arch/mips/mobileye/Platform
+69
-39
arch/mips/pci/pci-mt7620.c
+69
-39
arch/mips/pci/pci-mt7620.c
···
26
26
27
27
#define RALINK_INT_PCIE0 4
28
28
29
+
#define RALINK_SYSCFG0 0x10
30
+
#define RALINK_SYSCFG0_XTAL40 BIT(6)
29
31
#define RALINK_CLKCFG1 0x30
30
-
#define RALINK_GPIOMODE 0x60
31
32
32
33
#define PPLL_CFG1 0x9c
33
34
#define PPLL_LD BIT(23)
···
63
62
64
63
#define PCIEPHY0_CFG 0x90
65
64
66
-
#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
65
+
#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7000
67
66
#define RALINK_PCIE0_CLK_EN BIT(26)
68
67
69
68
#define BUSY 0x80000000
···
88
87
return ioread32(bridge_base + reg);
89
88
}
90
89
90
+
static inline void bridge_m32(u32 clr, u32 set, unsigned reg)
91
+
{
92
+
u32 val = bridge_r32(reg);
93
+
94
+
val &= ~clr;
95
+
val |= set;
96
+
bridge_w32(val, reg);
97
+
}
98
+
91
99
static inline void pcie_w32(u32 val, unsigned reg)
92
100
{
93
101
iowrite32(val, pcie_base + reg);
···
114
104
val &= ~clr;
115
105
val |= set;
116
106
pcie_w32(val, reg);
107
+
}
108
+
109
+
static inline void
110
+
pcie_phyctrl_set(unsigned offset, u32 b_start, u32 bits, u32 val)
111
+
{
112
+
pcie_m32(GENMASK(b_start + bits - 1, b_start),
113
+
val << b_start,
114
+
RALINK_PCIEPHY_P0_CTL_OFFSET + offset);
117
115
}
118
116
119
117
static int wait_pciephy_busy(void)
···
245
227
/* Elastic buffer control */
246
228
pcie_phy(0x68, 0xB4);
247
229
248
-
/* put core into reset */
249
-
pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
250
-
reset_control_assert(rstpcie0);
251
-
252
-
/* disable power and all clocks */
253
-
rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
254
-
rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
255
-
256
-
/* bring core out of reset */
257
-
reset_control_deassert(rstpcie0);
258
-
rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
259
-
mdelay(100);
260
-
261
230
if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
262
231
dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n");
263
232
reset_control_assert(rstpcie0);
···
259
254
return 0;
260
255
}
261
256
262
-
static int mt7628_pci_hw_init(struct platform_device *pdev)
257
+
static void mt7628_pci_hw_init(struct platform_device *pdev)
263
258
{
264
-
u32 val = 0;
265
-
266
-
/* bring the core out of reset */
267
-
rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
268
-
reset_control_deassert(rstpcie0);
269
-
270
-
/* enable the pci clk */
271
-
rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
272
-
mdelay(100);
273
-
274
259
/* voodoo from the SDK driver */
275
-
pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
260
+
pcie_phyctrl_set(0x400, 8, 1, 0x1);
261
+
pcie_phyctrl_set(0x400, 9, 2, 0x0);
262
+
pcie_phyctrl_set(0x000, 4, 1, 0x1);
263
+
pcie_phyctrl_set(0x000, 5, 1, 0x0);
264
+
pcie_phyctrl_set(0x4ac, 16, 3, 0x3);
276
265
277
-
pci_config_read(NULL, 0, 0x70c, 4, &val);
278
-
val &= ~(0xff) << 8;
279
-
val |= 0x50 << 8;
280
-
pci_config_write(NULL, 0, 0x70c, 4, val);
266
+
if (rt_sysc_r32(RALINK_SYSCFG0) & RALINK_SYSCFG0_XTAL40) {
267
+
pcie_phyctrl_set(0x4bc, 24, 8, 0x7d);
268
+
pcie_phyctrl_set(0x490, 12, 4, 0x08);
269
+
pcie_phyctrl_set(0x490, 6, 2, 0x01);
270
+
pcie_phyctrl_set(0x4c0, 0, 32, 0x1f400000);
271
+
pcie_phyctrl_set(0x4a4, 0, 16, 0x013d);
272
+
pcie_phyctrl_set(0x4a8, 16, 16, 0x74);
273
+
pcie_phyctrl_set(0x4a8, 0, 16, 0x74);
274
+
} else {
275
+
pcie_phyctrl_set(0x4bc, 24, 8, 0x64);
276
+
pcie_phyctrl_set(0x490, 12, 4, 0x0a);
277
+
pcie_phyctrl_set(0x490, 6, 2, 0x00);
278
+
pcie_phyctrl_set(0x4c0, 0, 32, 0x19000000);
279
+
pcie_phyctrl_set(0x4a4, 0, 16, 0x018d);
280
+
pcie_phyctrl_set(0x4a8, 16, 16, 0x4a);
281
+
pcie_phyctrl_set(0x4a8, 0, 16, 0x4a);
282
+
}
281
283
282
-
return 0;
284
+
pcie_phyctrl_set(0x498, 0, 8, 0x5);
285
+
pcie_phyctrl_set(0x000, 5, 1, 0x1);
286
+
pcie_phyctrl_set(0x000, 4, 1, 0x0);
283
287
}
284
288
285
289
static int mt7620_pci_probe(struct platform_device *pdev)
···
312
298
ioport_resource.start = 0;
313
299
ioport_resource.end = ~0;
314
300
301
+
/* reset PCIe controller */
302
+
reset_control_assert(rstpcie0);
303
+
msleep(100);
304
+
reset_control_deassert(rstpcie0);
305
+
rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
306
+
msleep(100);
307
+
308
+
/* assert PERST_N pin */
309
+
bridge_m32(PCIRST, PCIRST, RALINK_PCI_PCICFG_ADDR);
310
+
315
311
/* bring up the pci core */
316
312
switch (ralink_soc) {
317
313
case MT762X_SOC_MT7620A:
···
331
307
332
308
case MT762X_SOC_MT7628AN:
333
309
case MT762X_SOC_MT7688:
334
-
if (mt7628_pci_hw_init(pdev))
335
-
return -1;
310
+
mt7628_pci_hw_init(pdev);
336
311
break;
337
312
338
313
default:
339
314
dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
340
315
return -1;
341
316
}
342
-
mdelay(50);
317
+
msleep(500);
343
318
344
-
/* enable write access */
345
-
pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
346
-
mdelay(100);
319
+
/* deassert PERST_N pin and wait PCIe peripheral init */
320
+
bridge_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
321
+
msleep(1000);
347
322
348
323
/* check if there is a card present */
349
324
if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
···
350
327
rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
351
328
if (ralink_soc == MT762X_SOC_MT7620A)
352
329
rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
330
+
else
331
+
pcie_phyctrl_set(0x000, 0, 32, 0x10);
353
332
dev_info(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
354
333
return -1;
355
334
}
···
365
340
pcie_w32(0x06040001, RALINK_PCI0_CLASS);
366
341
367
342
/* enable interrupts */
368
-
pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
343
+
bridge_m32(PCIINT2, PCIINT2, RALINK_PCI_PCIENA);
369
344
370
345
/* voodoo from the SDK driver */
371
346
pci_config_read(NULL, 0, 4, 4, &val);
372
347
pci_config_write(NULL, 0, 4, 4, val | 0x7);
348
+
349
+
pci_config_read(NULL, 0, 0x70c, 4, &val);
350
+
val &= ~(0xff) << 8;
351
+
val |= 0x50 << 8;
352
+
pci_config_write(NULL, 0, 0x70c, 4, val);
373
353
374
354
pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
375
355
register_pci_controller(&mt7620_controller);
+61
-22
arch/mips/rb532/devices.c
+61
-22
arch/mips/rb532/devices.c
···
14
14
#include <linux/platform_device.h>
15
15
#include <linux/mtd/platnand.h>
16
16
#include <linux/mtd/mtd.h>
17
-
#include <linux/gpio.h>
18
17
#include <linux/gpio/machine.h>
18
+
#include <linux/gpio/property.h>
19
19
#include <linux/gpio_keys.h>
20
20
#include <linux/input.h>
21
+
#include <linux/property.h>
21
22
#include <linux/serial_8250.h>
22
23
23
24
#include <asm/bootinfo.h>
···
38
37
extern unsigned int idt_cpu_freq;
39
38
40
39
static struct mpmc_device dev3;
40
+
41
+
static const struct software_node rb532_gpio0_node = {
42
+
.name = "gpio0",
43
+
};
41
44
42
45
void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
43
46
{
···
134
129
.num_resources = ARRAY_SIZE(cf_slot0_res),
135
130
};
136
131
137
-
/* Resources and device for NAND */
138
-
static int rb532_dev_ready(struct nand_chip *chip)
139
-
{
140
-
return gpio_get_value(GPIO_RDY);
141
-
}
142
-
143
132
static void rb532_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)
144
133
{
145
134
unsigned char orbits, nandbits;
···
159
160
};
160
161
161
162
static struct platform_nand_data rb532_nand_data = {
162
-
.ctrl.dev_ready = rb532_dev_ready,
163
163
.ctrl.cmd_ctrl = rb532_cmd_ctrl,
164
164
};
165
165
166
-
static struct platform_device nand_slot0 = {
167
-
.name = "gen_nand",
168
-
.id = -1,
169
-
.resource = nand_slot0_res,
170
-
.num_resources = ARRAY_SIZE(nand_slot0_res),
171
-
.dev.platform_data = &rb532_nand_data,
166
+
static const struct property_entry nand0_properties[] = {
167
+
PROPERTY_ENTRY_GPIO("ready-gpios", &rb532_gpio0_node,
168
+
GPIO_RDY, GPIO_ACTIVE_HIGH),
169
+
{ }
170
+
};
171
+
172
+
static const struct platform_device_info nand0_info __initconst = {
173
+
.name = "gen_nand",
174
+
.id = PLATFORM_DEVID_NONE,
175
+
.res = nand_slot0_res,
176
+
.num_res = ARRAY_SIZE(nand_slot0_res),
177
+
.data = &rb532_nand_data,
178
+
.size_data = sizeof(struct platform_nand_data),
179
+
.properties = nand0_properties,
172
180
};
173
181
174
182
static struct mtd_partition rb532_partition_info[] = {
···
193
187
static struct platform_device rb532_led = {
194
188
.name = "rb532-led",
195
189
.id = -1,
196
-
};
197
-
198
-
static struct platform_device rb532_button = {
199
-
.name = "rb532-button",
200
-
.id = -1,
201
190
};
202
191
203
192
static struct resource rb532_wdt_res[] = {
···
234
233
235
234
static struct platform_device *rb532_devs[] = {
236
235
&korina_dev0,
237
-
&nand_slot0,
238
236
&cf_slot0,
239
237
&rb532_led,
240
-
&rb532_button,
241
238
&rb532_uart,
242
239
&rb532_wdt
243
240
};
241
+
242
+
static const struct property_entry rb532_button_properties[] = {
243
+
PROPERTY_ENTRY_GPIO("button-gpios", &rb532_gpio0_node,
244
+
GPIO_BTN_S1, GPIO_ACTIVE_LOW),
245
+
{ }
246
+
};
247
+
248
+
static const struct platform_device_info rb532_button_info __initconst = {
249
+
.name = "rb532-button",
250
+
.id = PLATFORM_DEVID_NONE,
251
+
.properties = rb532_button_properties,
252
+
};
253
+
244
254
245
255
/* NAND definitions */
246
256
#define NAND_CHIP_DELAY 25
···
279
267
280
268
static int __init plat_setup_devices(void)
281
269
{
270
+
struct platform_device *pd;
271
+
int ret;
272
+
282
273
/* Look for the CF card reader */
283
274
if (!readl(IDT434_REG_BASE + DEV1MASK))
284
275
rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
···
310
295
rb532_uart_res[0].uartclk = idt_cpu_freq;
311
296
312
297
gpiod_add_lookup_table(&cf_slot0_gpio_table);
313
-
return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
298
+
ret = platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
299
+
if (ret)
300
+
return ret;
301
+
302
+
/*
303
+
* Stack devices using full info and properties here, after we
304
+
* register the node for the GPIO chip.
305
+
*/
306
+
software_node_register(&rb532_gpio0_node);
307
+
308
+
pd = platform_device_register_full(&nand0_info);
309
+
ret = PTR_ERR_OR_ZERO(pd);
310
+
if (ret) {
311
+
pr_err("failed to create NAND slot0 device: %d\n", ret);
312
+
return ret;
313
+
}
314
+
315
+
pd = platform_device_register_full(&rb532_button_info);
316
+
ret = PTR_ERR_OR_ZERO(pd);
317
+
if (ret) {
318
+
pr_err("failed to create RB532 button device: %d\n", ret);
319
+
return ret;
320
+
}
321
+
322
+
return 0;
314
323
}
315
324
316
325
#ifdef CONFIG_NET
+2
-2
drivers/clk/Kconfig
+2
-2
drivers/clk/Kconfig
···
236
236
237
237
config COMMON_CLK_EYEQ
238
238
bool "Clock driver for the Mobileye EyeQ platform"
239
-
depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
239
+
depends on EYEQ || COMPILE_TEST
240
240
select AUXILIARY_BUS
241
-
default MACH_EYEQ5 || MACH_EYEQ6H
241
+
default EYEQ
242
242
help
243
243
This driver provides clocks found on Mobileye EyeQ5, EyeQ6L and Eye6H
244
244
SoCs. Controllers live in shared register regions called OLB. Driver
+79
-11
drivers/clk/clk-eyeq.c
+79
-11
drivers/clk/clk-eyeq.c
···
45
45
#include <linux/types.h>
46
46
47
47
#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
48
+
#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h>
48
49
49
50
/* In frac mode, it enables fractional noise canceling DAC. Else, no function. */
50
51
#define PCSR0_DAC_EN BIT(0)
···
164
163
static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
165
164
unsigned long *div, unsigned long *acc)
166
165
{
167
-
u32 spread;
166
+
unsigned long spread;
168
167
169
168
if (r0 & PCSR0_BYPASS) {
170
169
*mult = 1;
···
178
177
179
178
*mult = FIELD_GET(PCSR0_INTIN, r0);
180
179
*div = FIELD_GET(PCSR0_REF_DIV, r0);
181
-
if (r0 & PCSR0_FOUTPOSTDIV_EN)
182
-
*div *= FIELD_GET(PCSR0_POST_DIV1, r0) * FIELD_GET(PCSR0_POST_DIV2, r0);
183
180
184
181
/* Fractional mode, in 2^20 (0x100000) parts. */
185
182
if (r0 & PCSR0_DSM_EN) {
···
196
197
/*
197
198
* Spread spectrum.
198
199
*
199
-
* Spread is 1/1000 parts of frequency, accuracy is half of
200
-
* that. To get accuracy, convert to ppb (parts per billion).
200
+
* Spread is in 1/1024 parts of frequency. Clock accuracy
201
+
* is half the spread value expressed in parts per billion.
201
202
*
202
-
* acc = spread * 1e6 / 2
203
-
* with acc in parts per billion and,
204
-
* spread in parts per thousand.
203
+
* accuracy = (spread * 1e9) / (1024 * 2)
204
+
*
205
+
* Care is taken to avoid overflowing or losing precision.
205
206
*/
206
207
spread = FIELD_GET(PCSR1_SPREAD, r1);
207
-
*acc = spread * 500000;
208
+
*acc = DIV_ROUND_CLOSEST(spread * 1000000000, 1024 * 2);
208
209
209
210
if (r1 & PCSR1_DOWN_SPREAD) {
210
211
/*
211
212
* Downspreading: the central frequency is half a
212
213
* spread lower.
213
214
*/
214
-
*mult *= 2000 - spread;
215
-
*div *= 2000;
215
+
*mult *= 2048 - spread;
216
+
*div *= 2048;
216
217
217
218
/*
218
219
* Previous operation might overflow 32 bits. If it
···
572
573
.reset_auxdev_name = "reset",
573
574
};
574
575
576
+
static const struct eqc_pll eqc_eyeq6lplus_early_plls[] = {
577
+
{ .index = EQ6LPC_PLL_CPU, .name = "pll-cpu", .reg64 = 0x058 },
578
+
};
579
+
580
+
static const struct eqc_pll eqc_eyeq6lplus_plls[] = {
581
+
{ .index = EQ6LPC_PLL_DDR, .name = "pll-ddr", .reg64 = 0x02C },
582
+
{ .index = EQ6LPC_PLL_ACC, .name = "pll-acc", .reg64 = 0x034 },
583
+
{ .index = EQ6LPC_PLL_PER, .name = "pll-per", .reg64 = 0x03C },
584
+
{ .index = EQ6LPC_PLL_VDI, .name = "pll-vdi", .reg64 = 0x044 },
585
+
};
586
+
587
+
static const struct eqc_fixed_factor eqc_eyeq6lplus_early_fixed_factors[] = {
588
+
{ EQ6LPC_CPU_OCC, "occ-cpu", 1, 1, EQ6LPC_PLL_CPU },
589
+
};
590
+
591
+
static const struct eqc_fixed_factor eqc_eyeq6lplus_fixed_factors[] = {
592
+
{ EQ6LPC_DDR_OCC, "occ-ddr", 1, 1, EQ6LPC_PLL_DDR },
593
+
594
+
{ EQ6LPC_ACC_VDI, "vdi-div", 1, 10, EQ6LPC_PLL_ACC },
595
+
{ EQ6LPC_ACC_OCC, "occ-acc", 1, 1, EQ6LPC_PLL_ACC },
596
+
{ EQ6LPC_ACC_FCMU, "fcmu-a-clk", 1, 10, EQ6LPC_ACC_OCC },
597
+
598
+
{ EQ6LPC_PER_OCC, "occ-per", 1, 1, EQ6LPC_PLL_PER },
599
+
{ EQ6LPC_PER_I2C_SER, "i2c-ser-clk", 1, 10, EQ6LPC_PER_OCC },
600
+
{ EQ6LPC_PER_PCLK, "pclk", 1, 4, EQ6LPC_PER_OCC },
601
+
{ EQ6LPC_PER_TSU, "tsu-clk", 1, 8, EQ6LPC_PER_OCC },
602
+
{ EQ6LPC_PER_OSPI, "ospi-ref-clk", 1, 10, EQ6LPC_PER_OCC },
603
+
{ EQ6LPC_PER_GPIO, "gpio-clk", 1, 4, EQ6LPC_PER_OCC },
604
+
{ EQ6LPC_PER_TIMER, "timer-clk", 1, 4, EQ6LPC_PER_OCC },
605
+
{ EQ6LPC_PER_I2C, "i2c-clk", 1, 4, EQ6LPC_PER_OCC },
606
+
{ EQ6LPC_PER_UART, "uart-clk", 1, 4, EQ6LPC_PER_OCC },
607
+
{ EQ6LPC_PER_SPI, "spi-clk", 1, 4, EQ6LPC_PER_OCC },
608
+
{ EQ6LPC_PER_PERIPH, "periph-clk", 1, 1, EQ6LPC_PER_OCC },
609
+
610
+
{ EQ6LPC_VDI_OCC, "occ-vdi", 1, 1, EQ6LPC_PLL_VDI },
611
+
};
612
+
613
+
static const struct eqc_early_match_data eqc_eyeq6lplus_early_match_data __initconst = {
614
+
.early_pll_count = ARRAY_SIZE(eqc_eyeq6lplus_early_plls),
615
+
.early_plls = eqc_eyeq6lplus_early_plls,
616
+
617
+
.early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6lplus_early_fixed_factors),
618
+
.early_fixed_factors = eqc_eyeq6lplus_early_fixed_factors,
619
+
620
+
.late_clk_count = ARRAY_SIZE(eqc_eyeq6lplus_plls) +
621
+
ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors),
622
+
};
623
+
624
+
static const struct eqc_match_data eqc_eyeq6lplus_match_data = {
625
+
.pll_count = ARRAY_SIZE(eqc_eyeq6lplus_plls),
626
+
.plls = eqc_eyeq6lplus_plls,
627
+
628
+
.fixed_factor_count = ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors),
629
+
.fixed_factors = eqc_eyeq6lplus_fixed_factors,
630
+
631
+
.reset_auxdev_name = "reset",
632
+
.pinctrl_auxdev_name = "pinctrl",
633
+
634
+
.early_clk_count = ARRAY_SIZE(eqc_eyeq6lplus_early_plls) +
635
+
ARRAY_SIZE(eqc_eyeq6lplus_early_fixed_factors),
636
+
};
637
+
575
638
static const struct eqc_match_data eqc_eyeq6h_west_match_data = {
576
639
.reset_auxdev_name = "reset_west",
577
640
};
···
735
674
static const struct of_device_id eqc_match_table[] = {
736
675
{ .compatible = "mobileye,eyeq5-olb", .data = &eqc_eyeq5_match_data },
737
676
{ .compatible = "mobileye,eyeq6l-olb", .data = &eqc_eyeq6l_match_data },
677
+
{ .compatible = "mobileye,eyeq6lplus-olb", .data = &eqc_eyeq6lplus_match_data },
738
678
{ .compatible = "mobileye,eyeq6h-west-olb", .data = &eqc_eyeq6h_west_match_data },
739
679
{ .compatible = "mobileye,eyeq6h-east-olb", .data = &eqc_eyeq6h_east_match_data },
740
680
{ .compatible = "mobileye,eyeq6h-south-olb", .data = &eqc_eyeq6h_south_match_data },
···
919
857
}
920
858
CLK_OF_DECLARE_DRIVER(eqc_eyeq6h_west, "mobileye,eyeq6h-west-olb",
921
859
eqc_eyeq6h_west_early_init);
860
+
861
+
static void __init eqc_eyeq6lplus_early_init(struct device_node *np)
862
+
{
863
+
eqc_early_init(np, &eqc_eyeq6lplus_early_match_data);
864
+
}
865
+
CLK_OF_DECLARE_DRIVER(eqc_eyeq6lplus, "mobileye,eyeq6lplus-olb", eqc_eyeq6lplus_early_init);
+23
-1
drivers/mtd/nand/raw/plat_nand.c
+23
-1
drivers/mtd/nand/raw/plat_nand.c
···
6
6
*/
7
7
8
8
#include <linux/err.h>
9
+
#include <linux/gpio/consumer.h>
9
10
#include <linux/io.h>
10
11
#include <linux/module.h>
11
12
#include <linux/platform_device.h>
···
18
17
struct nand_controller controller;
19
18
struct nand_chip chip;
20
19
void __iomem *io_base;
20
+
struct gpio_desc *ready_gpio;
21
21
};
22
22
23
23
static int plat_nand_attach_chip(struct nand_chip *chip)
···
34
32
.attach_chip = plat_nand_attach_chip,
35
33
};
36
34
35
+
/* Resources and device for NAND */
36
+
static int plat_nand_gpio_dev_ready(struct nand_chip *chip)
37
+
{
38
+
struct plat_nand_data *data = nand_get_controller_data(chip);
39
+
40
+
return gpiod_get_value(data->ready_gpio);
41
+
}
42
+
37
43
/*
38
44
* Probe for the NAND device.
39
45
*/
···
51
41
struct plat_nand_data *data;
52
42
struct mtd_info *mtd;
53
43
const char **part_types;
44
+
struct nand_chip *chip;
54
45
int err = 0;
55
46
56
47
if (!pdata) {
···
70
59
if (!data)
71
60
return -ENOMEM;
72
61
62
+
data->ready_gpio = devm_gpiod_get_optional(&pdev->dev, "ready",
63
+
GPIOD_IN);
64
+
if (IS_ERR(data->ready_gpio))
65
+
return dev_err_probe(&pdev->dev, PTR_ERR(data->ready_gpio),
66
+
"could not get READY GPIO\n");
67
+
73
68
data->controller.ops = &plat_nand_ops;
74
69
nand_controller_init(&data->controller);
75
70
data->chip.controller = &data->controller;
71
+
chip = &data->chip;
72
+
nand_set_controller_data(chip, data);
76
73
77
74
data->io_base = devm_platform_ioremap_resource(pdev, 0);
78
75
if (IS_ERR(data->io_base))
···
93
74
data->chip.legacy.IO_ADDR_R = data->io_base;
94
75
data->chip.legacy.IO_ADDR_W = data->io_base;
95
76
data->chip.legacy.cmd_ctrl = pdata->ctrl.cmd_ctrl;
96
-
data->chip.legacy.dev_ready = pdata->ctrl.dev_ready;
77
+
if (data->ready_gpio)
78
+
data->chip.legacy.dev_ready = plat_nand_gpio_dev_ready;
79
+
else
80
+
data->chip.legacy.dev_ready = pdata->ctrl.dev_ready;
97
81
data->chip.legacy.select_chip = pdata->ctrl.select_chip;
98
82
data->chip.legacy.write_buf = pdata->ctrl.write_buf;
99
83
data->chip.legacy.read_buf = pdata->ctrl.read_buf;
+2
-2
drivers/pinctrl/Kconfig
+2
-2
drivers/pinctrl/Kconfig
···
254
254
config PINCTRL_EYEQ5
255
255
bool "Mobileye EyeQ5 pinctrl driver"
256
256
depends on OF
257
-
depends on MACH_EYEQ5 || COMPILE_TEST
257
+
depends on MACH_EYEQ5 || MACH_EYEQ6LPLUS || COMPILE_TEST
258
258
select PINMUX
259
259
select GENERIC_PINCONF
260
260
select AUXILIARY_BUS
261
-
default MACH_EYEQ5
261
+
default MACH_EYEQ5 || MACH_EYEQ6LPLUS
262
262
help
263
263
Pin controller driver for the Mobileye EyeQ5 platform. It does both
264
264
pin config & pin muxing. It does not handle GPIO.
+308
-129
drivers/pinctrl/pinctrl-eyeq5.c
+308
-129
drivers/pinctrl/pinctrl-eyeq5.c
···
26
26
#include <linux/errno.h>
27
27
#include <linux/io.h>
28
28
#include <linux/mod_devicetable.h>
29
+
#include <linux/of.h>
29
30
#include <linux/seq_file.h>
30
31
#include <linux/slab.h>
31
32
#include <linux/types.h>
···
39
38
#include "core.h"
40
39
#include "pinctrl-utils.h"
41
40
42
-
struct eq5p_pinctrl {
43
-
struct pinctrl_desc desc;
44
-
void __iomem *base;
45
-
};
46
-
47
-
enum eq5p_bank {
48
-
EQ5P_BANK_A,
49
-
EQ5P_BANK_B,
50
-
51
-
EQ5P_BANK_COUNT,
52
-
};
53
-
54
41
enum eq5p_regs {
55
42
EQ5P_PD,
56
43
EQ5P_PU,
···
49
60
EQ5P_REG_COUNT,
50
61
};
51
62
52
-
static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] = {
53
-
[EQ5P_BANK_A] = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},
54
-
[EQ5P_BANK_B] = {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4},
63
+
struct eq5p_bank {
64
+
const unsigned int npins;
65
+
const unsigned int regs[EQ5P_REG_COUNT];
66
+
};
67
+
68
+
struct eq5p_match_data {
69
+
const unsigned int npins;
70
+
const unsigned int nfunctions;
71
+
const unsigned int nbanks;
72
+
const struct pinctrl_pin_desc *pins;
73
+
const struct pinfunction *functions;
74
+
const struct eq5p_bank *banks;
75
+
};
76
+
77
+
struct eq5p_pinctrl {
78
+
struct pinctrl_desc desc;
79
+
void __iomem *base;
80
+
const struct eq5p_match_data *data;
55
81
};
56
82
57
83
/*
···
75
71
#define EQ5P_DS_MASK GENMASK(1, 0)
76
72
77
73
/*
74
+
* The GPIO function is always the first function
75
+
*/
76
+
#define EQ5P_GPIO_FUNC_SELECTOR 0
77
+
78
+
/* Helper to declare pinfunction */
79
+
#define EQ5P_PINFUNCTION(func, groups) PINCTRL_PINFUNCTION(func, groups, ARRAY_SIZE(groups))
80
+
81
+
/*
78
82
* Comments to the right of each pin are the "signal name" in the datasheet.
79
83
*/
80
-
static const struct pinctrl_pin_desc eq5p_pins[] = {
84
+
static const struct pinctrl_pin_desc eq5p_eyeq5_pins[] = {
81
85
/* Bank A */
82
86
PINCTRL_PIN(0, "PA0"), /* A0_TIMER0_CK */
83
87
PINCTRL_PIN(1, "PA1"), /* A1_TIMER0_EOC */
···
117
105
PINCTRL_PIN(27, "PA27"), /* A27_SPI_1_CS1 */
118
106
PINCTRL_PIN(28, "PA28"), /* A28_REF_CLK0 */
119
107
120
-
#define EQ5P_PIN_OFFSET_BANK_B 29
108
+
#define EQ5P_EYEQ5_PIN_OFFSET_BANK_B 29
121
109
122
110
/* Bank B */
123
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 0, "PB0"), /* B0_TIMER3_CK */
124
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 1, "PB1"), /* B1_TIMER3_EOC */
125
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 2, "PB2"), /* B2_TIMER4_CK */
126
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 3, "PB3"), /* B3_TIMER4_EOC */
127
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 4, "PB4"), /* B4_TIMER6_EXT_INCAP1 */
128
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 5, "PB5"), /* B5_TIMER6_EXT_INCAP2 */
129
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 6, "PB6"), /* B6_TIMER6_EXT_OUTCMP1 */
130
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 7, "PB7"), /* B7_TIMER6_EXT_OUTCMP2 */
131
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 8, "PB8"), /* B8_UART_2_TX */
132
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 9, "PB9"), /* B9_UART_2_RX */
133
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */
134
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */
135
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */
136
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */
137
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */
138
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */
139
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */
140
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */
141
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */
142
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */
143
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 */
144
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 */
145
-
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */
111
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 0, "PB0"), /* B0_TIMER3_CK */
112
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 1, "PB1"), /* B1_TIMER3_EOC */
113
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 2, "PB2"), /* B2_TIMER4_CK */
114
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 3, "PB3"), /* B3_TIMER4_EOC */
115
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 4, "PB4"), /* B4_TIMER6_EXT_INCAP1 */
116
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 5, "PB5"), /* B5_TIMER6_EXT_INCAP2 */
117
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 6, "PB6"), /* B6_TIMER6_EXT_OUTCMP1 */
118
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 7, "PB7"), /* B7_TIMER6_EXT_OUTCMP2 */
119
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 8, "PB8"), /* B8_UART_2_TX */
120
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 9, "PB9"), /* B9_UART_2_RX */
121
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */
122
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */
123
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */
124
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */
125
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */
126
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */
127
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */
128
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */
129
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */
130
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */
131
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 */
132
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 */
133
+
PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */
146
134
};
147
135
148
-
static const char * const gpio_groups[] = {
136
+
static const char * const eq5p_eyeq5_gpio_groups[] = {
149
137
/* Bank A */
150
138
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
151
139
"PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15",
···
159
147
};
160
148
161
149
/* Groups of functions on bank A */
162
-
static const char * const timer0_groups[] = { "PA0", "PA1" };
163
-
static const char * const timer1_groups[] = { "PA2", "PA3" };
164
-
static const char * const timer2_groups[] = { "PA4", "PA5" };
165
-
static const char * const timer5_groups[] = { "PA6", "PA7", "PA8", "PA9" };
166
-
static const char * const uart0_groups[] = { "PA10", "PA11" };
167
-
static const char * const uart1_groups[] = { "PA12", "PA13" };
168
-
static const char * const can0_groups[] = { "PA14", "PA15" };
169
-
static const char * const can1_groups[] = { "PA16", "PA17" };
170
-
static const char * const spi0_groups[] = { "PA18", "PA19", "PA20", "PA21", "PA22" };
171
-
static const char * const spi1_groups[] = { "PA23", "PA24", "PA25", "PA26", "PA27" };
172
-
static const char * const refclk0_groups[] = { "PA28" };
150
+
static const char * const eq5p_eyeq5_timer0_groups[] = { "PA0", "PA1" };
151
+
static const char * const eq5p_eyeq5_timer1_groups[] = { "PA2", "PA3" };
152
+
static const char * const eq5p_eyeq5_timer2_groups[] = { "PA4", "PA5" };
153
+
static const char * const eq5p_eyeq5_timer5_groups[] = { "PA6", "PA7", "PA8", "PA9" };
154
+
static const char * const eq5p_eyeq5_uart0_groups[] = { "PA10", "PA11" };
155
+
static const char * const eq5p_eyeq5_uart1_groups[] = { "PA12", "PA13" };
156
+
static const char * const eq5p_eyeq5_can0_groups[] = { "PA14", "PA15" };
157
+
static const char * const eq5p_eyeq5_can1_groups[] = { "PA16", "PA17" };
158
+
static const char * const eq5p_eyeq5_spi0_groups[] = { "PA18", "PA19", "PA20", "PA21", "PA22" };
159
+
static const char * const eq5p_eyeq5_spi1_groups[] = { "PA23", "PA24", "PA25", "PA26", "PA27" };
160
+
static const char * const eq5p_eyeq5_refclk0_groups[] = { "PA28" };
173
161
174
162
/* Groups of functions on bank B */
175
-
static const char * const timer3_groups[] = { "PB0", "PB1" };
176
-
static const char * const timer4_groups[] = { "PB2", "PB3" };
177
-
static const char * const timer6_groups[] = { "PB4", "PB5", "PB6", "PB7" };
178
-
static const char * const uart2_groups[] = { "PB8", "PB9" };
179
-
static const char * const can2_groups[] = { "PB10", "PB11" };
180
-
static const char * const spi2_groups[] = { "PB12", "PB13", "PB14", "PB15", "PB16" };
181
-
static const char * const spi3_groups[] = { "PB17", "PB18", "PB19", "PB20", "PB21" };
182
-
static const char * const mclk0_groups[] = { "PB22" };
163
+
static const char * const eq5p_eyeq5_timer3_groups[] = { "PB0", "PB1" };
164
+
static const char * const eq5p_eyeq5_timer4_groups[] = { "PB2", "PB3" };
165
+
static const char * const eq5p_eyeq5_timer6_groups[] = { "PB4", "PB5", "PB6", "PB7" };
166
+
static const char * const eq5p_eyeq5_uart2_groups[] = { "PB8", "PB9" };
167
+
static const char * const eq5p_eyeq5_can2_groups[] = { "PB10", "PB11" };
168
+
static const char * const eq5p_eyeq5_spi2_groups[] = { "PB12", "PB13", "PB14", "PB15", "PB16" };
169
+
static const char * const eq5p_eyeq5_spi3_groups[] = { "PB17", "PB18", "PB19", "PB20", "PB21" };
170
+
static const char * const eq5p_eyeq5_mclk0_groups[] = { "PB22" };
183
171
184
-
static const struct pinfunction eq5p_functions[] = {
185
-
/* GPIO having a fixed index is depended upon, see GPIO_FUNC_SELECTOR. */
186
-
PINCTRL_PINFUNCTION("gpio", gpio_groups, ARRAY_SIZE(gpio_groups)),
187
-
#define GPIO_FUNC_SELECTOR 0
172
+
static const struct pinfunction eq5p_eyeq5_functions[] = {
173
+
/* GPIO having a fixed index is depended upon, see EQ5P_GPIO_FUNC_SELECTOR. */
174
+
EQ5P_PINFUNCTION("gpio", eq5p_eyeq5_gpio_groups),
188
175
189
176
/* Bank A functions */
190
-
PINCTRL_PINFUNCTION("timer0", timer0_groups, ARRAY_SIZE(timer0_groups)),
191
-
PINCTRL_PINFUNCTION("timer1", timer1_groups, ARRAY_SIZE(timer1_groups)),
192
-
PINCTRL_PINFUNCTION("timer2", timer2_groups, ARRAY_SIZE(timer2_groups)),
193
-
PINCTRL_PINFUNCTION("timer5", timer5_groups, ARRAY_SIZE(timer5_groups)),
194
-
PINCTRL_PINFUNCTION("uart0", uart0_groups, ARRAY_SIZE(uart0_groups)),
195
-
PINCTRL_PINFUNCTION("uart1", uart1_groups, ARRAY_SIZE(uart1_groups)),
196
-
PINCTRL_PINFUNCTION("can0", can0_groups, ARRAY_SIZE(can0_groups)),
197
-
PINCTRL_PINFUNCTION("can1", can1_groups, ARRAY_SIZE(can1_groups)),
198
-
PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)),
199
-
PINCTRL_PINFUNCTION("spi1", spi1_groups, ARRAY_SIZE(spi1_groups)),
200
-
PINCTRL_PINFUNCTION("refclk0", refclk0_groups, ARRAY_SIZE(refclk0_groups)),
177
+
EQ5P_PINFUNCTION("timer0", eq5p_eyeq5_timer0_groups),
178
+
EQ5P_PINFUNCTION("timer1", eq5p_eyeq5_timer1_groups),
179
+
EQ5P_PINFUNCTION("timer2", eq5p_eyeq5_timer2_groups),
180
+
EQ5P_PINFUNCTION("timer5", eq5p_eyeq5_timer5_groups),
181
+
EQ5P_PINFUNCTION("uart0", eq5p_eyeq5_uart0_groups),
182
+
EQ5P_PINFUNCTION("uart1", eq5p_eyeq5_uart1_groups),
183
+
EQ5P_PINFUNCTION("can0", eq5p_eyeq5_can0_groups),
184
+
EQ5P_PINFUNCTION("can1", eq5p_eyeq5_can1_groups),
185
+
EQ5P_PINFUNCTION("spi0", eq5p_eyeq5_spi0_groups),
186
+
EQ5P_PINFUNCTION("spi1", eq5p_eyeq5_spi1_groups),
187
+
EQ5P_PINFUNCTION("refclk0", eq5p_eyeq5_refclk0_groups),
201
188
202
189
/* Bank B functions */
203
-
PINCTRL_PINFUNCTION("timer3", timer3_groups, ARRAY_SIZE(timer3_groups)),
204
-
PINCTRL_PINFUNCTION("timer4", timer4_groups, ARRAY_SIZE(timer4_groups)),
205
-
PINCTRL_PINFUNCTION("timer6", timer6_groups, ARRAY_SIZE(timer6_groups)),
206
-
PINCTRL_PINFUNCTION("uart2", uart2_groups, ARRAY_SIZE(uart2_groups)),
207
-
PINCTRL_PINFUNCTION("can2", can2_groups, ARRAY_SIZE(can2_groups)),
208
-
PINCTRL_PINFUNCTION("spi2", spi2_groups, ARRAY_SIZE(spi2_groups)),
209
-
PINCTRL_PINFUNCTION("spi3", spi3_groups, ARRAY_SIZE(spi3_groups)),
210
-
PINCTRL_PINFUNCTION("mclk0", mclk0_groups, ARRAY_SIZE(mclk0_groups)),
190
+
EQ5P_PINFUNCTION("timer3", eq5p_eyeq5_timer3_groups),
191
+
EQ5P_PINFUNCTION("timer4", eq5p_eyeq5_timer4_groups),
192
+
EQ5P_PINFUNCTION("timer6", eq5p_eyeq5_timer6_groups),
193
+
EQ5P_PINFUNCTION("uart2", eq5p_eyeq5_uart2_groups),
194
+
EQ5P_PINFUNCTION("can2", eq5p_eyeq5_can2_groups),
195
+
EQ5P_PINFUNCTION("spi2", eq5p_eyeq5_spi2_groups),
196
+
EQ5P_PINFUNCTION("spi3", eq5p_eyeq5_spi3_groups),
197
+
EQ5P_PINFUNCTION("mclk0", eq5p_eyeq5_mclk0_groups),
198
+
};
199
+
200
+
static const struct eq5p_bank eq5p_eyeq5_banks[] = {
201
+
{
202
+
.npins = EQ5P_EYEQ5_PIN_OFFSET_BANK_B,
203
+
.regs = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},
204
+
},
205
+
{
206
+
.npins = ARRAY_SIZE(eq5p_eyeq5_pins) - EQ5P_EYEQ5_PIN_OFFSET_BANK_B,
207
+
.regs = {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4},
208
+
},
209
+
};
210
+
211
+
static const struct eq5p_match_data eq5p_eyeq5_data = {
212
+
.npins = ARRAY_SIZE(eq5p_eyeq5_pins),
213
+
.nfunctions = ARRAY_SIZE(eq5p_eyeq5_functions),
214
+
.nbanks = ARRAY_SIZE(eq5p_eyeq5_banks),
215
+
.pins = eq5p_eyeq5_pins,
216
+
.functions = eq5p_eyeq5_functions,
217
+
.banks = eq5p_eyeq5_banks,
218
+
};
219
+
220
+
static const struct pinctrl_pin_desc eq5p_eyeq6lplus_pins[] = {
221
+
PINCTRL_PIN(0, "PA0"), /* GPIO_A0_TIMER0_CK0 */
222
+
PINCTRL_PIN(1, "PA1"), /* GPIO_A1_TIMER0_EOC */
223
+
PINCTRL_PIN(2, "PA2"), /* GPIO_A2_TIMER1_CK */
224
+
PINCTRL_PIN(3, "PA3"), /* GPIO_A3_TIMER1_EOC1 */
225
+
PINCTRL_PIN(4, "PA4"), /* GPIO_A4_SSI_UART_RX */
226
+
PINCTRL_PIN(5, "PA5"), /* GPIO_A5_SSI_UART_TX */
227
+
PINCTRL_PIN(6, "PA6"), /* GPIO_A6_SPI_0_CS */
228
+
PINCTRL_PIN(7, "PA7"), /* GPIO_A7_SPI_0_DI */
229
+
PINCTRL_PIN(8, "PA8"), /* GPIO_A8_SPI_0_CK */
230
+
PINCTRL_PIN(9, "PA9"), /* GPIO_A9_SPI_0_DO */
231
+
PINCTRL_PIN(10, "PA10"), /* GPIO_A10_SPI_0_CS1 */
232
+
PINCTRL_PIN(11, "PA11"), /* GPIO_A11_UART_0_RX */
233
+
PINCTRL_PIN(12, "PA12"), /* GPIO_A12_UART_0_TX */
234
+
PINCTRL_PIN(13, "PA13"), /* GPIO_A13_TIMER2_CK */
235
+
PINCTRL_PIN(14, "PA14"), /* GPIO_A14_TIMER2_EOC */
236
+
PINCTRL_PIN(15, "PA15"), /* GPIO_A15_TIMER3_CK */
237
+
PINCTRL_PIN(16, "PA16"), /* GPIO_A16_TIMER_EOC */
238
+
PINCTRL_PIN(17, "PA17"), /* GPIO_A17_TIMER_EXT0_INCA P1 */
239
+
PINCTRL_PIN(18, "PA18"), /* GPIO_A18_TIMER_EXT0_INCA P2 */
240
+
PINCTRL_PIN(19, "PA19"), /* GPIO_A19_TIMER_EXT0_OUT CMP1 */
241
+
PINCTRL_PIN(20, "PA20"), /* GPIO_A20_TIMER_EXT0_OUT CMP2 */
242
+
PINCTRL_PIN(21, "PA21"), /* GPIO_A21_SPI_1_CS0 */
243
+
PINCTRL_PIN(22, "PA22"), /* GPIO_A22_SPI_1_DI */
244
+
PINCTRL_PIN(23, "PA23"), /* GPIO_A23_SPI_1_CK */
245
+
PINCTRL_PIN(24, "PA24"), /* GPIO_A24_SPI_1_DO */
246
+
PINCTRL_PIN(25, "PA25"), /* GPIO_A25_SPI_1_CS1 */
247
+
PINCTRL_PIN(26, "PA26"), /* GPIO_A26_TIMER_EXT1_INCA P1 */
248
+
PINCTRL_PIN(27, "PA27"), /* GPIO_A27_TIMER_EXT1_INCA P2 */
249
+
PINCTRL_PIN(28, "PA28"), /* GPIO_A28_TIMER_EXT1_OUTC MP1 */
250
+
PINCTRL_PIN(29, "PA29"), /* GPIO_A29_TIMER_EXT1_OUTC MP2 */
251
+
PINCTRL_PIN(30, "PA30"), /* GPIO_A30_EXT_CLK */
252
+
PINCTRL_PIN(31, "PA31"), /* GPIO_A31_VDI_MCLK */
253
+
};
254
+
255
+
static const char * const eq5p_eyeq6lplus_gpio_groups[] = {
256
+
/* Bank A */
257
+
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
258
+
"PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15",
259
+
"PA16", "PA17", "PA18", "PA19", "PA20", "PA21", "PA22", "PA23",
260
+
"PA24", "PA25", "PA26", "PA27", "PA28", "PA29", "PA30", "PA31",
261
+
};
262
+
263
+
/* Groups of functions on bank A */
264
+
static const char * const eq5p_eyeq6lplus_timer0_groups[] = { "PA0", "PA1" };
265
+
static const char * const eq5p_eyeq6lplus_timer1_groups[] = { "PA2", "PA3" };
266
+
static const char * const eq5p_eyeq6lplus_uart_ssi_groups[] = { "PA4", "PA5" };
267
+
static const char * const eq5p_eyeq6lplus_spi0_groups[] = { "PA6", "PA7", "PA8", "PA9", "PA10" };
268
+
static const char * const eq5p_eyeq6lplus_uart0_groups[] = { "PA11", "PA12" };
269
+
static const char * const eq5p_eyeq6lplus_timer2_groups[] = { "PA13", "PA14" };
270
+
static const char * const eq5p_eyeq6lplus_timer3_groups[] = { "PA15", "PA16" };
271
+
static const char * const eq5p_eyeq6lplus_timer_ext0_groups[] = { "PA17", "PA18", "PA19", "PA20" };
272
+
static const char * const eq5p_eyeq6lplus_spi1_groups[] = {
273
+
"PA21", "PA22", "PA23", "PA24", "PA25"
274
+
};
275
+
static const char * const eq5p_eyeq6lplus_timer_ext1_groups[] = { "PA26", "PA27", "PA28", "PA29" };
276
+
static const char * const eq5p_eyeq6lplus_ext_ref_clk_groups[] = { "PA30" };
277
+
static const char * const eq5p_eyeq6lplus_mipi_ref_clk_groups[] = { "PA31" };
278
+
279
+
static const struct pinfunction eq5p_eyeq6lplus_functions[] = {
280
+
/* gpios function */
281
+
EQ5P_PINFUNCTION("gpio", eq5p_eyeq6lplus_gpio_groups),
282
+
283
+
/* Bank A alternate functions */
284
+
EQ5P_PINFUNCTION("timer0", eq5p_eyeq6lplus_timer0_groups),
285
+
EQ5P_PINFUNCTION("timer1", eq5p_eyeq6lplus_timer1_groups),
286
+
EQ5P_PINFUNCTION("uart_ssi", eq5p_eyeq6lplus_uart_ssi_groups),
287
+
EQ5P_PINFUNCTION("spi0", eq5p_eyeq6lplus_spi0_groups),
288
+
EQ5P_PINFUNCTION("uart0", eq5p_eyeq6lplus_uart0_groups),
289
+
EQ5P_PINFUNCTION("timer2", eq5p_eyeq6lplus_timer2_groups),
290
+
EQ5P_PINFUNCTION("timer3", eq5p_eyeq6lplus_timer3_groups),
291
+
EQ5P_PINFUNCTION("timer_ext0", eq5p_eyeq6lplus_timer_ext0_groups),
292
+
EQ5P_PINFUNCTION("spi1", eq5p_eyeq6lplus_spi1_groups),
293
+
EQ5P_PINFUNCTION("timer_ext1", eq5p_eyeq6lplus_timer_ext1_groups),
294
+
EQ5P_PINFUNCTION("ext_ref_clk", eq5p_eyeq6lplus_ext_ref_clk_groups),
295
+
EQ5P_PINFUNCTION("mipi_ref_clk", eq5p_eyeq6lplus_mipi_ref_clk_groups),
296
+
};
297
+
298
+
static const struct eq5p_bank eq5p_eyeq6lplus_banks[] = {
299
+
{
300
+
.npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins),
301
+
.regs = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},
302
+
},
303
+
};
304
+
305
+
static const struct eq5p_match_data eq5p_eyeq6lplus_data = {
306
+
.npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins),
307
+
.nfunctions = ARRAY_SIZE(eq5p_eyeq6lplus_functions),
308
+
.nbanks = ARRAY_SIZE(eq5p_eyeq6lplus_banks),
309
+
.pins = eq5p_eyeq6lplus_pins,
310
+
.functions = eq5p_eyeq6lplus_functions,
311
+
.banks = eq5p_eyeq6lplus_banks,
211
312
};
212
313
213
314
static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl,
214
-
enum eq5p_bank bank, enum eq5p_regs reg,
215
-
u32 mask, u32 val)
315
+
const struct eq5p_bank *bank,
316
+
enum eq5p_regs reg, u32 mask, u32 val)
216
317
{
217
-
void __iomem *ptr = pctrl->base + eq5p_regs[bank][reg];
318
+
void __iomem *ptr = pctrl->base + bank->regs[reg];
218
319
219
320
writel((readl(ptr) & ~mask) | (val & mask), ptr);
220
321
}
221
322
222
323
static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl,
223
-
enum eq5p_bank bank, enum eq5p_regs reg, int offset)
324
+
const struct eq5p_bank *bank,
325
+
enum eq5p_regs reg, int offset)
224
326
{
225
-
u32 val = readl(pctrl->base + eq5p_regs[bank][reg]);
327
+
u32 val = readl(pctrl->base + bank->regs[reg]);
226
328
227
329
if (WARN_ON(offset > 31))
228
330
return false;
···
344
218
return (val & BIT(offset)) != 0;
345
219
}
346
220
347
-
static enum eq5p_bank eq5p_pin_to_bank(unsigned int pin)
221
+
static int eq5p_pin_to_bank_offset(const struct eq5p_pinctrl *pctrl, unsigned int pin,
222
+
const struct eq5p_bank **bank, unsigned int *offset)
348
223
{
349
-
if (pin < EQ5P_PIN_OFFSET_BANK_B)
350
-
return EQ5P_BANK_A;
351
-
else
352
-
return EQ5P_BANK_B;
353
-
}
224
+
for (unsigned int i = 0; i < pctrl->data->nbanks; i++) {
225
+
const struct eq5p_bank *_bank = &pctrl->data->banks[i];
226
+
unsigned int npins = _bank->npins;
354
227
355
-
static unsigned int eq5p_pin_to_offset(unsigned int pin)
356
-
{
357
-
if (pin < EQ5P_PIN_OFFSET_BANK_B)
358
-
return pin;
359
-
else
360
-
return pin - EQ5P_PIN_OFFSET_BANK_B;
228
+
if (pin < npins) {
229
+
*bank = _bank;
230
+
*offset = pin;
231
+
return 0;
232
+
}
233
+
pin -= npins;
234
+
}
235
+
236
+
return -EINVAL;
361
237
}
362
238
363
239
static int eq5p_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
364
240
{
365
-
return ARRAY_SIZE(eq5p_pins);
241
+
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
242
+
243
+
return pctrl->data->npins;
366
244
}
367
245
368
246
static const char *eq5p_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
···
390
260
{
391
261
enum pin_config_param param = pinconf_to_config_param(*config);
392
262
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
393
-
unsigned int offset = eq5p_pin_to_offset(pin);
394
-
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
263
+
const struct eq5p_bank *bank;
264
+
unsigned int offset;
395
265
u32 val_ds, arg;
396
266
bool pd, pu;
267
+
int ret;
268
+
269
+
ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);
270
+
if (ret)
271
+
return ret;
397
272
398
273
pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset);
399
274
pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset);
···
416
281
case PIN_CONFIG_DRIVE_STRENGTH:
417
282
offset *= 2; /* two bits per pin */
418
283
if (offset >= 32) {
419
-
val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]);
284
+
val_ds = readl(pctrl->base + bank->regs[EQ5P_DS_HIGH]);
420
285
offset -= 32;
421
286
} else {
422
-
val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]);
287
+
val_ds = readl(pctrl->base + bank->regs[EQ5P_DS_LOW]);
423
288
}
424
289
arg = (val_ds >> offset) & EQ5P_DS_MASK;
425
290
break;
···
437
302
{
438
303
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
439
304
const char *pin_name = pctrl->desc.pins[pin].name;
440
-
unsigned int offset = eq5p_pin_to_offset(pin);
441
-
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
305
+
const struct eq5p_bank *bank;
442
306
const char *func_name, *bias;
443
307
unsigned long ds_config;
308
+
unsigned int offset;
444
309
u32 drive_strength;
445
310
bool pd, pu;
446
311
int i, j;
312
+
313
+
if (eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset)) {
314
+
seq_puts(s, "unknown pin");
315
+
return;
316
+
}
447
317
448
318
/*
449
319
* First, let's get the function name. All pins have only two functions:
···
456
316
*/
457
317
if (eq5p_test_bit(pctrl, bank, EQ5P_IOCR, offset)) {
458
318
func_name = NULL;
459
-
for (i = 0; i < ARRAY_SIZE(eq5p_functions); i++) {
460
-
if (i == GPIO_FUNC_SELECTOR)
319
+
for (i = 0; i < pctrl->data->nfunctions; i++) {
320
+
if (i == EQ5P_GPIO_FUNC_SELECTOR)
461
321
continue;
462
322
463
-
for (j = 0; j < eq5p_functions[i].ngroups; j++) {
323
+
for (j = 0; j < pctrl->data->functions[i].ngroups; j++) {
464
324
/* Groups and pins are the same thing for us. */
465
-
const char *x = eq5p_functions[i].groups[j];
325
+
const char *x = pctrl->data->functions[i].groups[j];
466
326
467
327
if (strcmp(x, pin_name) == 0) {
468
-
func_name = eq5p_functions[i].name;
328
+
func_name = pctrl->data->functions[i].name;
469
329
break;
470
330
}
471
331
}
···
481
341
if (!func_name)
482
342
func_name = "unknown";
483
343
} else {
484
-
func_name = eq5p_functions[GPIO_FUNC_SELECTOR].name;
344
+
func_name = pctrl->data->functions[EQ5P_GPIO_FUNC_SELECTOR].name;
485
345
}
486
346
487
347
/* Second, we retrieve the bias. */
···
516
376
517
377
static int eq5p_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
518
378
{
519
-
return ARRAY_SIZE(eq5p_functions);
379
+
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
380
+
381
+
return pctrl->data->nfunctions;
520
382
}
521
383
522
384
static const char *eq5p_pinmux_get_function_name(struct pinctrl_dev *pctldev,
523
385
unsigned int selector)
524
386
{
525
-
return eq5p_functions[selector].name;
387
+
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
388
+
389
+
return pctrl->data->functions[selector].name;
526
390
}
527
391
528
392
static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
···
534
390
const char * const **groups,
535
391
unsigned int *num_groups)
536
392
{
537
-
*groups = eq5p_functions[selector].groups;
538
-
*num_groups = eq5p_functions[selector].ngroups;
393
+
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
394
+
395
+
*groups = pctrl->data->functions[selector].groups;
396
+
*num_groups = pctrl->data->functions[selector].ngroups;
539
397
return 0;
540
398
}
541
399
···
545
399
unsigned int func_selector, unsigned int pin)
546
400
{
547
401
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
548
-
const char *func_name = eq5p_functions[func_selector].name;
402
+
const char *func_name = pctrl->data->functions[func_selector].name;
549
403
const char *group_name = pctldev->desc->pins[pin].name;
550
-
bool is_gpio = func_selector == GPIO_FUNC_SELECTOR;
551
-
unsigned int offset = eq5p_pin_to_offset(pin);
552
-
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
404
+
bool is_gpio = func_selector == EQ5P_GPIO_FUNC_SELECTOR;
405
+
const struct eq5p_bank *bank;
406
+
unsigned int offset;
553
407
u32 mask, val;
408
+
int ret;
409
+
410
+
ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);
411
+
if (ret)
412
+
return ret;
554
413
555
414
dev_dbg(pctldev->dev, "func=%s group=%s\n", func_name, group_name);
556
415
···
570
419
unsigned int pin)
571
420
{
572
421
/* Pin numbers and group selectors are the same thing in our case. */
573
-
return eq5p_pinmux_set_mux(pctldev, GPIO_FUNC_SELECTOR, pin);
422
+
return eq5p_pinmux_set_mux(pctldev, EQ5P_GPIO_FUNC_SELECTOR, pin);
574
423
}
575
424
576
425
static const struct pinmux_ops eq5p_pinmux_ops = {
···
586
435
unsigned int pin, u32 arg)
587
436
{
588
437
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
589
-
unsigned int offset = eq5p_pin_to_offset(pin);
590
-
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
438
+
const struct eq5p_bank *bank;
439
+
unsigned int offset;
591
440
unsigned int reg;
592
441
u32 mask, val;
442
+
int ret;
443
+
444
+
ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);
445
+
if (ret)
446
+
return ret;
593
447
594
448
if (arg & ~EQ5P_DS_MASK) {
595
449
dev_err(pctldev->dev, "Unsupported drive strength: %u\n", arg);
···
621
465
{
622
466
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
623
467
const char *pin_name = pctldev->desc->pins[pin].name;
624
-
unsigned int offset = eq5p_pin_to_offset(pin);
625
-
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
626
468
struct device *dev = pctldev->dev;
627
-
u32 val = BIT(offset);
469
+
const struct eq5p_bank *bank;
470
+
unsigned int offset;
628
471
unsigned int i;
472
+
u32 val;
473
+
int ret;
629
474
475
+
ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);
476
+
if (ret)
477
+
return ret;
478
+
479
+
val = BIT(offset);
630
480
for (i = 0; i < num_configs; i++) {
631
481
enum pin_config_param param = pinconf_to_config_param(configs[i]);
632
482
u32 arg = pinconf_to_config_argument(configs[i]);
···
695
533
static int eq5p_probe(struct auxiliary_device *adev,
696
534
const struct auxiliary_device_id *id)
697
535
{
536
+
const struct of_device_id *match;
698
537
struct device *dev = &adev->dev;
699
538
struct pinctrl_dev *pctldev;
700
539
struct eq5p_pinctrl *pctrl;
701
540
int ret;
541
+
542
+
/* Get match data based on parent OF node set in clk-eyeq */
543
+
match = of_match_node(dev->driver->of_match_table, dev->of_node);
544
+
if (!match || !match->data)
545
+
return -ENODEV;
702
546
703
547
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
704
548
if (!pctrl)
705
549
return -ENOMEM;
706
550
707
551
pctrl->base = (void __iomem *)dev_get_platdata(dev);
552
+
pctrl->data = match->data;
708
553
pctrl->desc.name = dev_name(dev);
709
-
pctrl->desc.pins = eq5p_pins;
710
-
pctrl->desc.npins = ARRAY_SIZE(eq5p_pins);
554
+
pctrl->desc.pins = pctrl->data->pins;
555
+
pctrl->desc.npins = pctrl->data->npins;
711
556
pctrl->desc.pctlops = &eq5p_pinctrl_ops;
712
557
pctrl->desc.pmxops = &eq5p_pinmux_ops;
713
558
pctrl->desc.confops = &eq5p_pinconf_ops;
···
731
562
return 0;
732
563
}
733
564
565
+
static const struct of_device_id eq5p_match_table[] = {
566
+
{ .compatible = "mobileye,eyeq5-olb", .data = &eq5p_eyeq5_data },
567
+
{ .compatible = "mobileye,eyeq6lplus-olb", .data = &eq5p_eyeq6lplus_data },
568
+
{}
569
+
};
570
+
MODULE_DEVICE_TABLE(of, eq5p_match_table);
571
+
734
572
static const struct auxiliary_device_id eq5p_id_table[] = {
735
573
{ .name = "clk_eyeq.pinctrl" },
736
574
{}
···
747
571
static struct auxiliary_driver eq5p_driver = {
748
572
.probe = eq5p_probe,
749
573
.id_table = eq5p_id_table,
574
+
.driver = {
575
+
.of_match_table = eq5p_match_table,
576
+
}
750
577
};
751
578
module_auxiliary_driver(eq5p_driver);
+2
-2
drivers/reset/Kconfig
+2
-2
drivers/reset/Kconfig
···
85
85
86
86
config RESET_EYEQ
87
87
bool "Mobileye EyeQ reset controller"
88
-
depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
88
+
depends on EYEQ || COMPILE_TEST
89
89
select AUXILIARY_BUS
90
-
default MACH_EYEQ5 || MACH_EYEQ6H
90
+
default EYEQ
91
91
help
92
92
This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L
93
93
and EyeQ6H SoCs.
+31
drivers/reset/reset-eyeq.c
+31
drivers/reset/reset-eyeq.c
···
49
49
* 8. MPC0 9. MPC1 10. MPC2 11. MPC3
50
50
* 12. MPC4
51
51
*
52
+
* Known resets in EyeQ6Lplus domain 0 (type EQR_EYEQ5_PCIE):
53
+
* 0. SPI0 1. SPI1 2. UART0 3. I2C0
54
+
* 4. I2C1 5. TIMER0 6. TIMER1 7. TIMER2
55
+
* 8. TIMER3 9. WD0 10. WD1 11. EXT0
56
+
* 12. EXT1 13. GPIO
57
+
*
58
+
* Known resets in EyeQ6Lplus domain 1 (type EQR_EYEQ5_ACRP):
59
+
* 0. VMP0 1. VMP1 2. VMP2 3. VMP3
60
+
* 4. PMA0 5. PMA1 6. PMAC0 7. PMAC1
61
+
* 8. MPC0 9. MPC1 10. MPC2 11. MPC3
62
+
* 12. MPC4
63
+
*
52
64
* Known resets in EyeQ6H west/east (type EQR_EYEQ6H_SARCR):
53
65
* 0. CAN 1. SPI0 2. SPI1 3. UART0
54
66
* 4. UART1 5. I2C0 6. I2C1 7. -hole-
···
533
521
.domains = eqr_eyeq6l_domains,
534
522
};
535
523
524
+
static const struct eqr_domain_descriptor eqr_eyeq6lplus_domains[] = {
525
+
{
526
+
.type = EQR_EYEQ5_PCIE,
527
+
.valid_mask = 0x3FFF,
528
+
.offset = 0x004,
529
+
},
530
+
{
531
+
.type = EQR_EYEQ5_ACRP,
532
+
.valid_mask = 0x00FF,
533
+
.offset = 0x200,
534
+
},
535
+
};
536
+
537
+
static const struct eqr_match_data eqr_eyeq6lplus_data = {
538
+
.domain_count = ARRAY_SIZE(eqr_eyeq6lplus_domains),
539
+
.domains = eqr_eyeq6lplus_domains,
540
+
};
541
+
536
542
/* West and east OLBs each have an instance. */
537
543
static const struct eqr_domain_descriptor eqr_eyeq6h_we_domains[] = {
538
544
{
···
585
555
static const struct of_device_id eqr_match_table[] = {
586
556
{ .compatible = "mobileye,eyeq5-olb", .data = &eqr_eyeq5_data },
587
557
{ .compatible = "mobileye,eyeq6l-olb", .data = &eqr_eyeq6l_data },
558
+
{ .compatible = "mobileye,eyeq6lplus-olb", .data = &eqr_eyeq6lplus_data },
588
559
{ .compatible = "mobileye,eyeq6h-west-olb", .data = &eqr_eyeq6h_we_data },
589
560
{ .compatible = "mobileye,eyeq6h-east-olb", .data = &eqr_eyeq6h_we_data },
590
561
{ .compatible = "mobileye,eyeq6h-acc-olb", .data = &eqr_eyeq6h_acc_data },
+37
include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h
+37
include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (C) 2025 Mobileye Vision Technologies Ltd.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ6LPLUS_CLK_H
7
+
#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ6LPLUS_CLK_H
8
+
9
+
#define EQ6LPC_PLL_CPU 0
10
+
#define EQ6LPC_PLL_DDR 1
11
+
#define EQ6LPC_PLL_PER 2
12
+
#define EQ6LPC_PLL_VDI 3
13
+
#define EQ6LPC_PLL_ACC 4
14
+
15
+
#define EQ6LPC_CPU_OCC 5
16
+
17
+
#define EQ6LPC_ACC_VDI 6
18
+
#define EQ6LPC_ACC_OCC 7
19
+
#define EQ6LPC_ACC_FCMU 8
20
+
21
+
#define EQ6LPC_DDR_OCC 9
22
+
23
+
#define EQ6LPC_PER_OCC 10
24
+
#define EQ6LPC_PER_I2C_SER 11
25
+
#define EQ6LPC_PER_PCLK 12
26
+
#define EQ6LPC_PER_TSU 13
27
+
#define EQ6LPC_PER_OSPI 14
28
+
#define EQ6LPC_PER_GPIO 15
29
+
#define EQ6LPC_PER_TIMER 16
30
+
#define EQ6LPC_PER_I2C 17
31
+
#define EQ6LPC_PER_UART 18
32
+
#define EQ6LPC_PER_SPI 19
33
+
#define EQ6LPC_PER_PERIPH 20
34
+
35
+
#define EQ6LPC_VDI_OCC 21
36
+
37
+
#endif