tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs

Join the two to register them in one shot.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230120092053.182923-18-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

AngeloGioacchino Del Regno and committed by
Stephen Boyd d7595dde 66c8773b

+15 -22
+15 -22
drivers/clk/mediatek/clk-mt8183.c
··· 613 613 "aud_2_sel" 614 614 }; 615 615 616 - static struct mtk_composite top_aud_muxes[] = { 617 - MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 618 - 0x320, 8, 1), 619 - MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 620 - 0x320, 9, 1), 621 - MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 622 - 0x320, 10, 1), 623 - MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 624 - 0x320, 11, 1), 625 - MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 626 - 0x320, 12, 1), 627 - MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 628 - 0x328, 20, 1), 629 - }; 630 - 631 616 static const char * const mcu_mp0_parents[] = { 632 617 "clk26m", 633 618 "armpll_ll", ··· 643 658 MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), 644 659 }; 645 660 646 - static struct mtk_composite top_aud_divs[] = { 661 + static struct mtk_composite top_aud_comp[] = { 662 + MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 663 + 0x320, 8, 1), 664 + MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 665 + 0x320, 9, 1), 666 + MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 667 + 0x320, 10, 1), 668 + MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 669 + 0x320, 11, 1), 670 + MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 671 + 0x320, 12, 1), 672 + MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 673 + 0x328, 20, 1), 647 674 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 648 675 0x320, 2, 0x324, 8, 0), 649 676 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", ··· 1167 1170 ARRAY_SIZE(top_muxes), node, 1168 1171 &mt8183_clk_lock, top_clk_data); 1169 1172 1170 - mtk_clk_register_composites(&pdev->dev, top_aud_muxes, 1171 - ARRAY_SIZE(top_aud_muxes), base, 1172 - &mt8183_clk_lock, top_clk_data); 1173 - 1174 - mtk_clk_register_composites(&pdev->dev, top_aud_divs, 1175 - ARRAY_SIZE(top_aud_divs), base, 1173 + mtk_clk_register_composites(&pdev->dev, top_aud_comp, 1174 + ARRAY_SIZE(top_aud_comp), base, 1176 1175 &mt8183_clk_lock, top_clk_data); 1177 1176 1178 1177 mtk_clk_register_gates(&pdev->dev, node, top_clks,