tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull late MIPS fixes from Ralf Baechle:
"This fixes a number of lose ends in the MIPS code and various bug
fixes.

Aside of dropping some patch that should not be in this pull request
everything has sat in -next for quite a while and there are no known
issues.

The biggest patch in this patch set moves the allocation of an array
that is aliased to a function (for runtime generated code) to
assembler code. This avoids an issue with certain toolchains when
building for microMIPS."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (35 commits)
MIPS: PCI: Move fixups from __init to __devinit.
MIPS: Fix bug.h MIPS build regression
MIPS: sync-r4k: remove redundant irq operation
MIPS: smp: Warn on too early irq enable
MIPS: call set_cpu_online() on cpu being brought up with irq disabled
MIPS: call ->smp_finish() a little late
MIPS: Yosemite: delay irq enable to ->smp_finish()
MIPS: SMTC: delay irq enable to ->smp_finish()
MIPS: BMIPS: delay irq enable to ->smp_finish()
MIPS: Octeon: delay enable irq to ->smp_finish()
MIPS: Oprofile: Fix build as a module.
MIPS: BCM63XX: Fix BCM6368 IPSec clock bit
MIPS: perf: Fix build error caused by unused counters_per_cpu_to_total()
MIPS: Fix Magic SysRq L kernel crash.
MIPS: BMIPS: Fix duplicate header inclusion.
mips: mark const init data with __initconst instead of __initdata
MIPS: cmpxchg.h: Add missing include
MIPS: Malta may also be equipped with MIPS64 R2 processors.
MIPS: Fix typo multipy -> multiply
MIPS: Cavium: Fix duplicate ARCH_SPARSEMEM_ENABLE in kconfig.
...

Linus Torvalds d75e2c9a 93517374

+273 -169
+2
arch/mips/Kconfig
··· 288 288 select SYS_HAS_CPU_MIPS32_R1 289 289 select SYS_HAS_CPU_MIPS32_R2 290 290 select SYS_HAS_CPU_MIPS64_R1 291 + select SYS_HAS_CPU_MIPS64_R2 291 292 select SYS_HAS_CPU_NEVADA 292 293 select SYS_HAS_CPU_RM7000 293 294 select SYS_HAS_EARLY_PRINTK ··· 1424 1423 config CPU_CAVIUM_OCTEON 1425 1424 bool "Cavium Octeon processor" 1426 1425 depends on SYS_HAS_CPU_CAVIUM_OCTEON 1426 + select ARCH_SPARSEMEM_ENABLE 1427 1427 select CPU_HAS_PREFETCH 1428 1428 select CPU_SUPPORTS_64BIT_KERNEL 1429 1429 select SYS_SUPPORTS_SMP
+1
arch/mips/bcm47xx/Kconfig
··· 21 21 select BCMA 22 22 select BCMA_HOST_SOC 23 23 select BCMA_DRIVER_MIPS 24 + select BCMA_HOST_PCI if PCI 24 25 select BCMA_DRIVER_PCI_HOSTMODE if PCI 25 26 default y 26 27 help
+2 -2
arch/mips/bcm63xx/dev-pcmcia.c
··· 79 79 return ret; 80 80 } 81 81 82 - static const __initdata struct { 82 + static const struct { 83 83 unsigned int cs; 84 84 unsigned int base; 85 85 unsigned int size; 86 - } pcmcia_cs[3] = { 86 + } pcmcia_cs[3] __initconst = { 87 87 { 88 88 .cs = MPI_CS_PCMCIA_COMMON, 89 89 .base = BCM_PCMCIA_COMMON_BASE_PA,
-4
arch/mips/cavium-octeon/Kconfig
··· 82 82 help 83 83 Lock the kernel's implementation of memcpy() into L2. 84 84 85 - config ARCH_SPARSEMEM_ENABLE 86 - def_bool y 87 - select SPARSEMEM_STATIC 88 - 89 85 config IOMMU_HELPER 90 86 bool 91 87
+1 -1
arch/mips/cavium-octeon/smp.c
··· 185 185 octeon_init_cvmcount(); 186 186 187 187 octeon_irq_setup_secondary(); 188 - raw_local_irq_enable(); 189 188 } 190 189 191 190 /** ··· 232 233 233 234 /* to generate the first CPU timer interrupt */ 234 235 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 236 + local_irq_enable(); 235 237 } 236 238 237 239 /**
+1
arch/mips/include/asm/cmpxchg.h
··· 8 8 #ifndef __ASM_CMPXCHG_H 9 9 #define __ASM_CMPXCHG_H 10 10 11 + #include <linux/bug.h> 11 12 #include <linux/irqflags.h> 12 13 #include <asm/war.h> 13 14
+4 -3
arch/mips/include/asm/cpu.h
··· 94 94 #define PRID_IMP_24KE 0x9600 95 95 #define PRID_IMP_74K 0x9700 96 96 #define PRID_IMP_1004K 0x9900 97 + #define PRID_IMP_M14KC 0x9c00 97 98 98 99 /* 99 100 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE ··· 261 260 */ 262 261 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 263 262 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 264 - CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, 263 + CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_M14KC, 265 264 266 265 /* 267 266 * MIPS64 class processors 268 267 */ 269 - CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 268 + CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 270 269 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 271 270 CPU_XLR, CPU_XLP, 272 271 ··· 289 288 #define MIPS_CPU_ISA_M64R2 0x00000100 290 289 291 290 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ 292 - MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) 291 + MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2) 293 292 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 294 293 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) 295 294
+14 -1
arch/mips/include/asm/gic.h
··· 206 206 207 207 #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 208 208 #define GIC_VPE_EIC_SS(intr) \ 209 - (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) 209 + (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr)) 210 210 211 211 #define GIC_VPE_EIC_VEC_BASE 0x0800 212 212 #define GIC_VPE_EIC_VEC(intr) \ ··· 330 330 #define GIC_FLAG_TRANSPARENT 0x02 331 331 }; 332 332 333 + /* 334 + * This is only used in EIC mode. This helps to figure out which 335 + * shared interrupts we need to process when we get a vector interrupt. 336 + */ 337 + #define GIC_MAX_SHARED_INTR 0x5 338 + struct gic_shared_intr_map { 339 + unsigned int num_shared_intr; 340 + unsigned int intr_list[GIC_MAX_SHARED_INTR]; 341 + unsigned int local_intr_mask; 342 + }; 343 + 333 344 extern void gic_init(unsigned long gic_base_addr, 334 345 unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, 335 346 unsigned int intrmap_size, unsigned int irqbase); ··· 349 338 extern void gic_send_ipi(unsigned int intr); 350 339 extern unsigned int plat_ipi_call_int_xlate(unsigned int); 351 340 extern unsigned int plat_ipi_resched_int_xlate(unsigned int); 341 + extern void gic_bind_eic_interrupt(int irq, int set); 342 + extern unsigned int gic_get_timer_pending(void); 352 343 353 344 #endif /* _ASM_GICREGS_H */
+2 -2
arch/mips/include/asm/inst.h
··· 251 251 unsigned int func : 6; 252 252 }; 253 253 254 - struct ma_format { /* FPU multipy and add format (MIPS IV) */ 254 + struct ma_format { /* FPU multiply and add format (MIPS IV) */ 255 255 unsigned int opcode : 6; 256 256 unsigned int fr : 5; 257 257 unsigned int ft : 5; ··· 324 324 unsigned int opcode : 6; 325 325 }; 326 326 327 - struct ma_format { /* FPU multipy and add format (MIPS IV) */ 327 + struct ma_format { /* FPU multiply and add format (MIPS IV) */ 328 328 unsigned int fmt : 2; 329 329 unsigned int func : 4; 330 330 unsigned int fd : 5;
+1
arch/mips/include/asm/irq.h
··· 136 136 * IE7. Since R2 their number has to be read from the c0_intctl register. 137 137 */ 138 138 #define CP0_LEGACY_COMPARE_IRQ 7 139 + #define CP0_LEGACY_PERFCNT_IRQ 7 139 140 140 141 extern int cp0_compare_irq; 141 142 extern int cp0_compare_irq_shift;
+1 -1
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
··· 99 99 #define CKCTL_6368_USBH_CLK_EN (1 << 15) 100 100 #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) 101 101 #define CKCTL_6368_NAND_CLK_EN (1 << 17) 102 - #define CKCTL_6368_IPSEC_CLK_EN (1 << 17) 102 + #define CKCTL_6368_IPSEC_CLK_EN (1 << 18) 103 103 104 104 #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ 105 105 CKCTL_6368_SWPKT_SAR_EN | \
+10
arch/mips/include/asm/mips-boards/maltaint.h
··· 86 86 #define GIC_CPU_INT4 4 /* . */ 87 87 #define GIC_CPU_INT5 5 /* Core Interrupt 5 */ 88 88 89 + /* MALTA GIC local interrupts */ 90 + #define GIC_INT_TMR (GIC_CPU_INT5) 91 + #define GIC_INT_PERFCTR (GIC_CPU_INT5) 92 + 93 + /* GIC constants */ 94 + /* Add 2 to convert non-eic hw int # to eic vector # */ 95 + #define GIC_CPU_TO_VEC_OFFSET (2) 96 + /* If we map an intr to pin X, GIC will actually generate vector X+1 */ 97 + #define GIC_PIN_TO_VEC_OFFSET (1) 98 + 89 99 #define GIC_EXT_INTR(x) x 90 100 91 101 /* External Interrupts used for IPI */
+1 -1
arch/mips/include/asm/mipsmtregs.h
··· 48 48 #define CP0_VPECONF0 $1, 2 49 49 #define CP0_VPECONF1 $1, 3 50 50 #define CP0_YQMASK $1, 4 51 - #define CP0_VPESCHEDULE $1, 5 51 + #define CP0_VPESCHEDULE $1, 5 52 52 #define CP0_VPESCHEFBK $1, 6 53 53 #define CP0_TCSTATUS $2, 1 54 54 #define CP0_TCBIND $2, 2
+4 -2
arch/mips/include/asm/switch_to.h
··· 22 22 * switch_to(n) should switch tasks to task nr n, first 23 23 * checking that n isn't the current task, in which case it does nothing. 24 24 */ 25 - extern asmlinkage void *resume(void *last, void *next, void *next_ti); 25 + extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu); 26 26 27 27 extern unsigned int ll_bit; 28 28 extern struct task_struct *ll_task; ··· 66 66 67 67 #define switch_to(prev, next, last) \ 68 68 do { \ 69 + u32 __usedfpu; \ 69 70 __mips_mt_fpaff_switch_to(prev); \ 70 71 if (cpu_has_dsp) \ 71 72 __save_dsp(prev); \ 72 73 __clear_software_ll_bit(); \ 73 - (last) = resume(prev, next, task_thread_info(next)); \ 74 + __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \ 75 + (last) = resume(prev, next, task_thread_info(next), __usedfpu); \ 74 76 } while (0) 75 77 76 78 #define finish_arch_switch(prev) \
+2 -2
arch/mips/include/asm/thread_info.h
··· 60 60 register struct thread_info *__current_thread_info __asm__("$28"); 61 61 #define current_thread_info() __current_thread_info 62 62 63 + #endif /* !__ASSEMBLY__ */ 64 + 63 65 /* thread information allocation */ 64 66 #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT) 65 67 #define THREAD_SIZE_ORDER (1) ··· 86 84 #define THREAD_MASK (THREAD_SIZE - 1UL) 87 85 88 86 #define STACK_WARN (THREAD_SIZE / 8) 89 - 90 - #endif /* !__ASSEMBLY__ */ 91 87 92 88 #define PREEMPT_ACTIVE 0x10000000 93 89
+10 -1
arch/mips/kernel/cpu-probe.c
··· 4 4 * Copyright (C) xxxx the Anonymous 5 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 - * Copyright (C) 2001, 2004 MIPS Inc. 7 + * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 8 * 9 9 * This program is free software; you can redistribute it and/or 10 10 * modify it under the terms of the GNU General Public License ··· 199 199 cpu_wait = rm7k_wait_irqoff; 200 200 break; 201 201 202 + case CPU_M14KC: 202 203 case CPU_24K: 203 204 case CPU_34K: 204 205 case CPU_1004K: ··· 811 810 c->cputype = CPU_5KC; 812 811 __cpu_name[cpu] = "MIPS 5Kc"; 813 812 break; 813 + case PRID_IMP_5KE: 814 + c->cputype = CPU_5KE; 815 + __cpu_name[cpu] = "MIPS 5KE"; 816 + break; 814 817 case PRID_IMP_20KC: 815 818 c->cputype = CPU_20KC; 816 819 __cpu_name[cpu] = "MIPS 20Kc"; ··· 835 830 case PRID_IMP_74K: 836 831 c->cputype = CPU_74K; 837 832 __cpu_name[cpu] = "MIPS 74Kc"; 833 + break; 834 + case PRID_IMP_M14KC: 835 + c->cputype = CPU_M14KC; 836 + __cpu_name[cpu] = "MIPS M14Kc"; 838 837 break; 839 838 case PRID_IMP_1004K: 840 839 c->cputype = CPU_1004K;
+7 -1
arch/mips/kernel/mips_ksyms.c
··· 5 5 * License. See the file "COPYING" in the main directory of this archive 6 6 * for more details. 7 7 * 8 - * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05 by Ralf Baechle 8 + * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05, 12 by Ralf Baechle 9 9 * Copyright (C) 1999, 2000, 01 Silicon Graphics, Inc. 10 10 */ 11 11 #include <linux/interrupt.h> ··· 33 33 EXPORT_SYMBOL(memmove); 34 34 35 35 EXPORT_SYMBOL(kernel_thread); 36 + 37 + /* 38 + * Functions that operate on entire pages. Mostly used by memory management. 39 + */ 40 + EXPORT_SYMBOL(clear_page); 41 + EXPORT_SYMBOL(copy_page); 36 42 37 43 /* 38 44 * Userspace access stuff.
+1 -1
arch/mips/kernel/octeon_switch.S
··· 31 31 32 32 /* 33 33 * task_struct *resume(task_struct *prev, task_struct *next, 34 - * struct thread_info *next_ti) 34 + * struct thread_info *next_ti, int usedfpu) 35 35 */ 36 36 .align 7 37 37 LEAF(resume)
-5
arch/mips/kernel/perf_event_mipsxx.c
··· 162 162 return counters >> vpe_shift(); 163 163 } 164 164 165 - static unsigned int counters_per_cpu_to_total(unsigned int counters) 166 - { 167 - return counters << vpe_shift(); 168 - } 169 - 170 165 #else /* !CONFIG_MIPS_MT_SMP */ 171 166 #define vpe_id() 0 172 167
+3 -12
arch/mips/kernel/r2300_switch.S
··· 43 43 44 44 /* 45 45 * task_struct *resume(task_struct *prev, task_struct *next, 46 - * struct thread_info *next_ti) ) 46 + * struct thread_info *next_ti, int usedfpu) 47 47 */ 48 48 LEAF(resume) 49 49 mfc0 t1, CP0_STATUS ··· 51 51 cpu_save_nonscratch a0 52 52 sw ra, THREAD_REG31(a0) 53 53 54 - /* 55 - * check if we need to save FPU registers 56 - */ 57 - lw t3, TASK_THREAD_INFO(a0) 58 - lw t0, TI_FLAGS(t3) 59 - li t1, _TIF_USEDFPU 60 - and t2, t0, t1 61 - beqz t2, 1f 62 - nor t1, zero, t1 54 + beqz a3, 1f 63 55 64 - and t0, t0, t1 65 - sw t0, TI_FLAGS(t3) 56 + PTR_L t3, TASK_THREAD_INFO(a0) 66 57 67 58 /* 68 59 * clear saved user stack CU1 bit
+4 -10
arch/mips/kernel/r4k_switch.S
··· 41 41 42 42 /* 43 43 * task_struct *resume(task_struct *prev, task_struct *next, 44 - * struct thread_info *next_ti) 44 + * struct thread_info *next_ti, int usedfpu) 45 45 */ 46 46 .align 5 47 47 LEAF(resume) ··· 53 53 /* 54 54 * check if we need to save FPU registers 55 55 */ 56 + 57 + beqz a3, 1f 58 + 56 59 PTR_L t3, TASK_THREAD_INFO(a0) 57 - LONG_L t0, TI_FLAGS(t3) 58 - li t1, _TIF_USEDFPU 59 - and t2, t0, t1 60 - beqz t2, 1f 61 - nor t1, zero, t1 62 - 63 - and t0, t0, t1 64 - LONG_S t0, TI_FLAGS(t3) 65 - 66 60 /* 67 61 * clear saved user stack CU1 bit 68 62 */
+7 -8
arch/mips/kernel/smp-bmips.c
··· 15 15 #include <linux/smp.h> 16 16 #include <linux/interrupt.h> 17 17 #include <linux/spinlock.h> 18 - #include <linux/init.h> 19 18 #include <linux/cpu.h> 20 19 #include <linux/cpumask.h> 21 20 #include <linux/reboot.h> ··· 196 197 197 198 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); 198 199 #endif 199 - 200 - /* make sure there won't be a timer interrupt for a little while */ 201 - write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 202 - 203 - irq_enable_hazard(); 204 - set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE); 205 - irq_enable_hazard(); 206 200 } 207 201 208 202 /* ··· 204 212 static void bmips_smp_finish(void) 205 213 { 206 214 pr_info("SMP: CPU%d is running\n", smp_processor_id()); 215 + 216 + /* make sure there won't be a timer interrupt for a little while */ 217 + write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 218 + 219 + irq_enable_hazard(); 220 + set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE); 221 + irq_enable_hazard(); 207 222 } 208 223 209 224 /*
+9 -3
arch/mips/kernel/smp.c
··· 122 122 123 123 notify_cpu_starting(cpu); 124 124 125 - mp_ops->smp_finish(); 125 + set_cpu_online(cpu, true); 126 + 126 127 set_cpu_sibling_map(cpu); 127 128 128 129 cpu_set(cpu, cpu_callin_map); 129 130 130 131 synchronise_count_slave(); 132 + 133 + /* 134 + * irq will be enabled in ->smp_finish(), enabling it too early 135 + * is dangerous. 136 + */ 137 + WARN_ON_ONCE(!irqs_disabled()); 138 + mp_ops->smp_finish(); 131 139 132 140 cpu_idle(); 133 141 } ··· 203 195 */ 204 196 while (!cpu_isset(cpu, cpu_callin_map)) 205 197 udelay(100); 206 - 207 - set_cpu_online(cpu, true); 208 198 209 199 return 0; 210 200 }
+7 -6
arch/mips/kernel/smtc.c
··· 322 322 323 323 /* 324 324 * Common setup before any secondaries are started 325 - * Make sure all CPU's are in a sensible state before we boot any of the 325 + * Make sure all CPUs are in a sensible state before we boot any of the 326 326 * secondaries. 327 327 * 328 328 * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly ··· 340 340 /* 341 341 * TCContext gets an offset from the base of the IPIQ array 342 342 * to be used in low-level code to detect the presence of 343 - * an active IPI queue 343 + * an active IPI queue. 344 344 */ 345 345 write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16); 346 346 /* Bind tc to vpe */ 347 347 write_tc_c0_tcbind(vpe); 348 - /* In general, all TCs should have the same cpu_data indications */ 348 + /* In general, all TCs should have the same cpu_data indications. */ 349 349 memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips)); 350 350 /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */ 351 351 if (cpu_data[0].cputype == CPU_34K || ··· 358 358 } 359 359 360 360 /* 361 - * Tweak to get Count registes in as close a sync as possible. 362 - * Value seems good for 34K-class cores. 361 + * Tweak to get Count registes in as close a sync as possible. The 362 + * value seems good for 34K-class cores. 363 363 */ 364 364 365 365 #define CP0_SKEW 8 ··· 615 615 616 616 void smtc_init_secondary(void) 617 617 { 618 - local_irq_enable(); 619 618 } 620 619 621 620 void smtc_smp_finish(void) ··· 629 630 */ 630 631 if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id)) 631 632 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); 633 + 634 + local_irq_enable(); 632 635 633 636 printk("TC %d going on-line as CPU %d\n", 634 637 cpu_data[smp_processor_id()].tc_id, smp_processor_id());
-5
arch/mips/kernel/sync-r4k.c
··· 111 111 void __cpuinit synchronise_count_slave(void) 112 112 { 113 113 int i; 114 - unsigned long flags; 115 114 unsigned int initcount; 116 115 int ncpus; 117 116 ··· 121 122 */ 122 123 return; 123 124 #endif 124 - 125 - local_irq_save(flags); 126 125 127 126 /* 128 127 * Not every cpu is online at the time this gets called, ··· 151 154 } 152 155 /* Arrange for an interrupt in a short while */ 153 156 write_c0_compare(read_c0_count() + COUNTON); 154 - 155 - local_irq_restore(flags); 156 157 } 157 158 #undef NR_LOOPS
+6 -1
arch/mips/kernel/traps.c
··· 132 132 unsigned long ra = regs->regs[31]; 133 133 unsigned long pc = regs->cp0_epc; 134 134 135 + if (!task) 136 + task = current; 137 + 135 138 if (raw_show_trace || !__kernel_text_address(pc)) { 136 139 show_raw_backtrace(sp); 137 140 return; ··· 1252 1249 break; 1253 1250 1254 1251 case CPU_5KC: 1252 + case CPU_5KE: 1255 1253 write_c0_ecc(0x80000000); 1256 1254 back_to_back_c0_hazard(); 1257 1255 /* Set the PE bit (bit 31) in the c0_errctl register. */ ··· 1502 1498 * Timer interrupt 1503 1499 */ 1504 1500 int cp0_compare_irq; 1501 + EXPORT_SYMBOL_GPL(cp0_compare_irq); 1505 1502 int cp0_compare_irq_shift; 1506 1503 1507 1504 /* ··· 1602 1597 cp0_perfcount_irq = -1; 1603 1598 } else { 1604 1599 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1605 - cp0_compare_irq_shift = cp0_compare_irq; 1600 + cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 1606 1601 cp0_perfcount_irq = -1; 1607 1602 } 1608 1603
+2 -1
arch/mips/kernel/vmlinux.lds.S
··· 1 1 #include <asm/asm-offsets.h> 2 2 #include <asm/page.h> 3 + #include <asm/thread_info.h> 3 4 #include <asm-generic/vmlinux.lds.h> 4 5 5 6 #undef mips ··· 73 72 .data : { /* Data */ 74 73 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ 75 74 76 - INIT_TASK_DATA(PAGE_SIZE) 75 + INIT_TASK_DATA(THREAD_SIZE) 77 76 NOSAVE_DATA 78 77 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) 79 78 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
+2 -2
arch/mips/mm/Makefile
··· 3 3 # 4 4 5 5 obj-y += cache.o dma-default.o extable.o fault.o \ 6 - gup.o init.o mmap.o page.o tlbex.o \ 7 - tlbex-fault.o uasm.o 6 + gup.o init.o mmap.o page.o page-funcs.o \ 7 + tlbex.o tlbex-fault.o uasm.o 8 8 9 9 obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o 10 10 obj-$(CONFIG_64BIT) += pgtable-64.o
+3 -2
arch/mips/mm/c-r4k.c
··· 977 977 c->icache.linesz = 2 << lsize; 978 978 else 979 979 c->icache.linesz = lsize; 980 - c->icache.sets = 64 << ((config1 >> 22) & 7); 980 + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); 981 981 c->icache.ways = 1 + ((config1 >> 16) & 7); 982 982 983 983 icache_size = c->icache.sets * ··· 997 997 c->dcache.linesz = 2 << lsize; 998 998 else 999 999 c->dcache.linesz= lsize; 1000 - c->dcache.sets = 64 << ((config1 >> 13) & 7); 1000 + c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); 1001 1001 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1002 1002 1003 1003 dcache_size = c->dcache.sets * ··· 1051 1051 case CPU_R14000: 1052 1052 break; 1053 1053 1054 + case CPU_M14KC: 1054 1055 case CPU_24K: 1055 1056 case CPU_34K: 1056 1057 case CPU_74K:
+50
arch/mips/mm/page-funcs.S
··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Micro-assembler generated clear_page/copy_page functions. 7 + * 8 + * Copyright (C) 2012 MIPS Technologies, Inc. 9 + * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org> 10 + */ 11 + #include <asm/asm.h> 12 + #include <asm/regdef.h> 13 + 14 + #ifdef CONFIG_SIBYTE_DMA_PAGEOPS 15 + #define cpu_clear_page_function_name clear_page_cpu 16 + #define cpu_copy_page_function_name copy_page_cpu 17 + #else 18 + #define cpu_clear_page_function_name clear_page 19 + #define cpu_copy_page_function_name copy_page 20 + #endif 21 + 22 + /* 23 + * Maximum sizes: 24 + * 25 + * R4000 128 bytes S-cache: 0x058 bytes 26 + * R4600 v1.7: 0x05c bytes 27 + * R4600 v2.0: 0x060 bytes 28 + * With prefetching, 16 word strides 0x120 bytes 29 + */ 30 + EXPORT(__clear_page_start) 31 + LEAF(cpu_clear_page_function_name) 32 + 1: j 1b /* Dummy, will be replaced. */ 33 + .space 288 34 + END(cpu_clear_page_function_name) 35 + EXPORT(__clear_page_end) 36 + 37 + /* 38 + * Maximum sizes: 39 + * 40 + * R4000 128 bytes S-cache: 0x11c bytes 41 + * R4600 v1.7: 0x080 bytes 42 + * R4600 v2.0: 0x07c bytes 43 + * With prefetching, 16 word strides 0x540 bytes 44 + */ 45 + EXPORT(__copy_page_start) 46 + LEAF(cpu_copy_page_function_name) 47 + 1: j 1b /* Dummy, will be replaced. */ 48 + .space 1344 49 + END(cpu_copy_page_function_name) 50 + EXPORT(__copy_page_end)
+18 -49
arch/mips/mm/page.c
··· 6 6 * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org) 7 7 * Copyright (C) 2007 Maciej W. Rozycki 8 8 * Copyright (C) 2008 Thiemo Seufer 9 + * Copyright (C) 2012 MIPS Technologies, Inc. 9 10 */ 10 11 #include <linux/init.h> 11 12 #include <linux/kernel.h> ··· 71 70 72 71 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) 73 72 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) 74 - 75 - /* 76 - * Maximum sizes: 77 - * 78 - * R4000 128 bytes S-cache: 0x058 bytes 79 - * R4600 v1.7: 0x05c bytes 80 - * R4600 v2.0: 0x060 bytes 81 - * With prefetching, 16 word strides 0x120 bytes 82 - */ 83 - 84 - static u32 clear_page_array[0x120 / 4]; 85 - 86 - #ifdef CONFIG_SIBYTE_DMA_PAGEOPS 87 - void clear_page_cpu(void *page) __attribute__((alias("clear_page_array"))); 88 - #else 89 - void clear_page(void *page) __attribute__((alias("clear_page_array"))); 90 - #endif 91 - 92 - EXPORT_SYMBOL(clear_page); 93 - 94 - /* 95 - * Maximum sizes: 96 - * 97 - * R4000 128 bytes S-cache: 0x11c bytes 98 - * R4600 v1.7: 0x080 bytes 99 - * R4600 v2.0: 0x07c bytes 100 - * With prefetching, 16 word strides 0x540 bytes 101 - */ 102 - static u32 copy_page_array[0x540 / 4]; 103 - 104 - #ifdef CONFIG_SIBYTE_DMA_PAGEOPS 105 - void 106 - copy_page_cpu(void *to, void *from) __attribute__((alias("copy_page_array"))); 107 - #else 108 - void copy_page(void *to, void *from) __attribute__((alias("copy_page_array"))); 109 - #endif 110 - 111 - EXPORT_SYMBOL(copy_page); 112 - 113 73 114 74 static int pref_bias_clear_store __cpuinitdata; 115 75 static int pref_bias_copy_load __cpuinitdata; ··· 244 282 } 245 283 } 246 284 285 + extern u32 __clear_page_start; 286 + extern u32 __clear_page_end; 287 + extern u32 __copy_page_start; 288 + extern u32 __copy_page_end; 289 + 247 290 void __cpuinit build_clear_page(void) 248 291 { 249 292 int off; 250 - u32 *buf = (u32 *)&clear_page_array; 293 + u32 *buf = &__clear_page_start; 251 294 struct uasm_label *l = labels; 252 295 struct uasm_reloc *r = relocs; 253 296 int i; ··· 323 356 uasm_i_jr(&buf, RA); 324 357 uasm_i_nop(&buf); 325 358 326 - BUG_ON(buf > clear_page_array + ARRAY_SIZE(clear_page_array)); 359 + BUG_ON(buf > &__clear_page_end); 327 360 328 361 uasm_resolve_relocs(relocs, labels); 329 362 330 363 pr_debug("Synthesized clear page handler (%u instructions).\n", 331 - (u32)(buf - clear_page_array)); 364 + (u32)(buf - &__clear_page_start)); 332 365 333 366 pr_debug("\t.set push\n"); 334 367 pr_debug("\t.set noreorder\n"); 335 - for (i = 0; i < (buf - clear_page_array); i++) 336 - pr_debug("\t.word 0x%08x\n", clear_page_array[i]); 368 + for (i = 0; i < (buf - &__clear_page_start); i++) 369 + pr_debug("\t.word 0x%08x\n", (&__clear_page_start)[i]); 337 370 pr_debug("\t.set pop\n"); 338 371 } 339 372 ··· 394 427 void __cpuinit build_copy_page(void) 395 428 { 396 429 int off; 397 - u32 *buf = (u32 *)&copy_page_array; 430 + u32 *buf = &__copy_page_start; 398 431 struct uasm_label *l = labels; 399 432 struct uasm_reloc *r = relocs; 400 433 int i; ··· 562 595 uasm_i_jr(&buf, RA); 563 596 uasm_i_nop(&buf); 564 597 565 - BUG_ON(buf > copy_page_array + ARRAY_SIZE(copy_page_array)); 598 + BUG_ON(buf > &__copy_page_end); 566 599 567 600 uasm_resolve_relocs(relocs, labels); 568 601 569 602 pr_debug("Synthesized copy page handler (%u instructions).\n", 570 - (u32)(buf - copy_page_array)); 603 + (u32)(buf - &__copy_page_start)); 571 604 572 605 pr_debug("\t.set push\n"); 573 606 pr_debug("\t.set noreorder\n"); 574 - for (i = 0; i < (buf - copy_page_array); i++) 575 - pr_debug("\t.word 0x%08x\n", copy_page_array[i]); 607 + for (i = 0; i < (buf - &__copy_page_start); i++) 608 + pr_debug("\t.word 0x%08x\n", (&__copy_page_start)[i]); 576 609 pr_debug("\t.set pop\n"); 577 610 } 578 611 579 612 #ifdef CONFIG_SIBYTE_DMA_PAGEOPS 613 + extern void clear_page_cpu(void *page); 614 + extern void copy_page_cpu(void *to, void *from); 580 615 581 616 /* 582 617 * Pad descriptors to cacheline, since each is exclusively owned by a
+2
arch/mips/mm/tlbex.c
··· 9 9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki 10 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 + * Copyright (C) 2011 MIPS Technologies, Inc. 12 13 * 13 14 * ... and the days got worse and worse and now you see 14 15 * I've gone completly out of my mind. ··· 495 494 case CPU_R14000: 496 495 case CPU_4KC: 497 496 case CPU_4KEC: 497 + case CPU_M14KC: 498 498 case CPU_SB1: 499 499 case CPU_SB1A: 500 500 case CPU_4KSC:
+4 -3
arch/mips/mti-malta/malta-pci.c
··· 241 241 return; 242 242 } 243 243 244 - if (controller->io_resource->start < 0x00001000UL) /* FIXME */ 245 - controller->io_resource->start = 0x00001000UL; 244 + /* Change start address to avoid conflicts with ACPI and SMB devices */ 245 + if (controller->io_resource->start < 0x00002000UL) 246 + controller->io_resource->start = 0x00002000UL; 246 247 247 248 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ 248 249 ioport_resource.end = controller->io_resource->end; ··· 254 253 } 255 254 256 255 /* Enable PCI 2.1 compatibility in PIIX4 */ 257 - static void __init quirk_dlcsetup(struct pci_dev *dev) 256 + static void __devinit quirk_dlcsetup(struct pci_dev *dev) 258 257 { 259 258 u8 odlc, ndlc; 260 259 (void) pci_read_config_byte(dev, 0x82, &odlc);
+1 -1
arch/mips/mti-malta/malta-setup.c
··· 111 111 unsigned int __iomem *jmpr_p = 112 112 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); 113 113 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; 114 - static const int pciclocks[] __initdata = { 114 + static const int pciclocks[] __initconst = { 115 115 33, 20, 25, 30, 12, 16, 37, 10 116 116 }; 117 117 int pciclock = pciclocks[jmpr];
+7 -1
arch/mips/netlogic/xlp/setup.c
··· 82 82 83 83 void xlp_mmu_init(void) 84 84 { 85 + /* enable extended TLB and Large Fixed TLB */ 85 86 write_c0_config6(read_c0_config6() | 0x24); 86 - current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 87 + 88 + /* set page mask of Fixed TLB in config7 */ 87 89 write_c0_config7(PM_DEFAULT_MASK >> 88 90 (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); 89 91 } ··· 102 100 nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); 103 101 #ifdef CONFIG_SMP 104 102 nlm_wakeup_secondary_cpus(0xffffffff); 103 + 104 + /* update TLB size after waking up threads */ 105 + current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 106 + 105 107 register_smp_ops(&nlm_smp_ops); 106 108 #endif 107 109 }
+1
arch/mips/oprofile/common.c
··· 78 78 79 79 switch (current_cpu_type()) { 80 80 case CPU_5KC: 81 + case CPU_M14KC: 81 82 case CPU_20KC: 82 83 case CPU_24K: 83 84 case CPU_25KF:
+4
arch/mips/oprofile/op_model_mipsxx.c
··· 322 322 323 323 op_model_mipsxx_ops.num_counters = counters; 324 324 switch (current_cpu_type()) { 325 + case CPU_M14KC: 326 + op_model_mipsxx_ops.cpu_type = "mips/M14Kc"; 327 + break; 328 + 325 329 case CPU_20KC: 326 330 op_model_mipsxx_ops.cpu_type = "mips/20K"; 327 331 break;
+6 -6
arch/mips/pci/fixup-fuloong2e.c
··· 48 48 return 0; 49 49 } 50 50 51 - static void __init loongson2e_nec_fixup(struct pci_dev *pdev) 51 + static void __devinit loongson2e_nec_fixup(struct pci_dev *pdev) 52 52 { 53 53 unsigned int val; 54 54 ··· 60 60 pci_write_config_dword(pdev, 0xe4, 1 << 5); 61 61 } 62 62 63 - static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev) 63 + static void __devinit loongson2e_686b_func0_fixup(struct pci_dev *pdev) 64 64 { 65 65 unsigned char c; 66 66 ··· 135 135 printk(KERN_INFO"via686b fix: ISA bridge done\n"); 136 136 } 137 137 138 - static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev) 138 + static void __devinit loongson2e_686b_func1_fixup(struct pci_dev *pdev) 139 139 { 140 140 printk(KERN_INFO"via686b fix: IDE\n"); 141 141 ··· 168 168 printk(KERN_INFO"via686b fix: IDE done\n"); 169 169 } 170 170 171 - static void __init loongson2e_686b_func2_fixup(struct pci_dev *pdev) 171 + static void __devinit loongson2e_686b_func2_fixup(struct pci_dev *pdev) 172 172 { 173 173 /* irq routing */ 174 174 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10); 175 175 } 176 176 177 - static void __init loongson2e_686b_func3_fixup(struct pci_dev *pdev) 177 + static void __devinit loongson2e_686b_func3_fixup(struct pci_dev *pdev) 178 178 { 179 179 /* irq routing */ 180 180 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11); 181 181 } 182 182 183 - static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev) 183 + static void __devinit loongson2e_686b_func5_fixup(struct pci_dev *pdev) 184 184 { 185 185 unsigned int val; 186 186 unsigned char c;
+6 -6
arch/mips/pci/fixup-lemote2f.c
··· 96 96 } 97 97 98 98 /* CS5536 SPEC. fixup */ 99 - static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev) 99 + static void __devinit loongson_cs5536_isa_fixup(struct pci_dev *pdev) 100 100 { 101 101 /* the uart1 and uart2 interrupt in PIC is enabled as default */ 102 102 pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1); 103 103 pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1); 104 104 } 105 105 106 - static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev) 106 + static void __devinit loongson_cs5536_ide_fixup(struct pci_dev *pdev) 107 107 { 108 108 /* setting the mutex pin as IDE function */ 109 109 pci_write_config_dword(pdev, PCI_IDE_CFG_REG, 110 110 CS5536_IDE_FLASH_SIGNATURE); 111 111 } 112 112 113 - static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev) 113 + static void __devinit loongson_cs5536_acc_fixup(struct pci_dev *pdev) 114 114 { 115 115 /* enable the AUDIO interrupt in PIC */ 116 116 pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1); ··· 118 118 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0); 119 119 } 120 120 121 - static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev) 121 + static void __devinit loongson_cs5536_ohci_fixup(struct pci_dev *pdev) 122 122 { 123 123 /* enable the OHCI interrupt in PIC */ 124 124 /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */ 125 125 pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1); 126 126 } 127 127 128 - static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev) 128 + static void __devinit loongson_cs5536_ehci_fixup(struct pci_dev *pdev) 129 129 { 130 130 u32 hi, lo; 131 131 ··· 137 137 pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000); 138 138 } 139 139 140 - static void __init loongson_nec_fixup(struct pci_dev *pdev) 140 + static void __devinit loongson_nec_fixup(struct pci_dev *pdev) 141 141 { 142 142 unsigned int val; 143 143
+3 -3
arch/mips/pci/fixup-malta.c
··· 49 49 return 0; 50 50 } 51 51 52 - static void __init malta_piix_func0_fixup(struct pci_dev *pdev) 52 + static void __devinit malta_piix_func0_fixup(struct pci_dev *pdev) 53 53 { 54 54 unsigned char reg_val; 55 - static int piixirqmap[16] __initdata = { /* PIIX PIRQC[A:D] irq mappings */ 55 + static int piixirqmap[16] __devinitdata = { /* PIIX PIRQC[A:D] irq mappings */ 56 56 0, 0, 0, 3, 57 57 4, 5, 6, 7, 58 58 0, 9, 10, 11, ··· 83 83 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, 84 84 malta_piix_func0_fixup); 85 85 86 - static void __init malta_piix_func1_fixup(struct pci_dev *pdev) 86 + static void __devinit malta_piix_func1_fixup(struct pci_dev *pdev) 87 87 { 88 88 unsigned char reg_val; 89 89
+2 -2
arch/mips/pci/fixup-mpc30x.c
··· 22 22 23 23 #include <asm/vr41xx/mpc30x.h> 24 24 25 - static const int internal_func_irqs[] __initdata = { 25 + static const int internal_func_irqs[] __initconst = { 26 26 VRC4173_CASCADE_IRQ, 27 27 VRC4173_AC97_IRQ, 28 28 VRC4173_USB_IRQ, 29 29 }; 30 30 31 - static const int irq_tab_mpc30x[] __initdata = { 31 + static const int irq_tab_mpc30x[] __initconst = { 32 32 [12] = VRC4173_PCMCIA1_IRQ, 33 33 [13] = VRC4173_PCMCIA2_IRQ, 34 34 [29] = MQ200_IRQ,
+3 -3
arch/mips/pci/fixup-sb1250.c
··· 15 15 * Set the BCM1250, etc. PCI host bridge's TRDY timeout 16 16 * to the finite max. 17 17 */ 18 - static void __init quirk_sb1250_pci(struct pci_dev *dev) 18 + static void __devinit quirk_sb1250_pci(struct pci_dev *dev) 19 19 { 20 20 pci_write_config_byte(dev, 0x40, 0xff); 21 21 } ··· 25 25 /* 26 26 * The BCM1250, etc. PCI/HT bridge reports as a host bridge. 27 27 */ 28 - static void __init quirk_sb1250_ht(struct pci_dev *dev) 28 + static void __devinit quirk_sb1250_ht(struct pci_dev *dev) 29 29 { 30 30 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 31 31 } ··· 35 35 /* 36 36 * Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max. 37 37 */ 38 - static void __init quirk_sp1011(struct pci_dev *dev) 38 + static void __devinit quirk_sp1011(struct pci_dev *dev) 39 39 { 40 40 pci_write_config_byte(dev, 0x64, 0xff); 41 41 }
+1 -1
arch/mips/pci/ops-tx4927.c
··· 495 495 } 496 496 497 497 #ifdef CONFIG_TOSHIBA_FPCIB0 498 - static void __init tx4927_quirk_slc90e66_bridge(struct pci_dev *dev) 498 + static void __devinit tx4927_quirk_slc90e66_bridge(struct pci_dev *dev) 499 499 { 500 500 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus); 501 501
+1 -1
arch/mips/pci/pci-ip27.c
··· 212 212 bridge->b_widget.w_tflush; /* Flush */ 213 213 } 214 214 215 - static void __init pci_fixup_ioc3(struct pci_dev *d) 215 + static void __devinit pci_fixup_ioc3(struct pci_dev *d) 216 216 { 217 217 pci_disable_swapping(d); 218 218 }
+51 -10
arch/mips/pci/pci-xlr.c
··· 41 41 #include <linux/irq.h> 42 42 #include <linux/irqdesc.h> 43 43 #include <linux/console.h> 44 + #include <linux/pci_regs.h> 44 45 45 46 #include <asm/io.h> 46 47 ··· 157 156 .io_offset = 0x00000000UL, 158 157 }; 159 158 159 + /* 160 + * The top level PCIe links on the XLS PCIe controller appear as 161 + * bridges. Given a device, this function finds which link it is 162 + * on. 163 + */ 164 + static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev) 165 + { 166 + struct pci_bus *bus, *p; 167 + 168 + /* Find the bridge on bus 0 */ 169 + bus = dev->bus; 170 + for (p = bus->parent; p && p->number != 0; p = p->parent) 171 + bus = p; 172 + 173 + return p ? bus->self : NULL; 174 + } 175 + 160 176 static int get_irq_vector(const struct pci_dev *dev) 161 177 { 178 + struct pci_dev *lnk; 179 + 162 180 if (!nlm_chip_is_xls()) 163 - return PIC_PCIX_IRQ; /* for XLR just one IRQ*/ 181 + return PIC_PCIX_IRQ; /* for XLR just one IRQ */ 164 182 165 183 /* 166 184 * For XLS PCIe, there is an IRQ per Link, find out which 167 185 * link the device is on to assign interrupts 168 - */ 169 - if (dev->bus->self == NULL) 186 + */ 187 + lnk = xls_get_pcie_link(dev); 188 + if (lnk == NULL) 170 189 return 0; 171 190 172 - switch (dev->bus->self->devfn) { 173 - case 0x0: 191 + switch (PCI_SLOT(lnk->devfn)) { 192 + case 0: 174 193 return PIC_PCIE_LINK0_IRQ; 175 - case 0x8: 194 + case 1: 176 195 return PIC_PCIE_LINK1_IRQ; 177 - case 0x10: 196 + case 2: 178 197 if (nlm_chip_is_xls_b()) 179 198 return PIC_PCIE_XLSB0_LINK2_IRQ; 180 199 else 181 200 return PIC_PCIE_LINK2_IRQ; 182 - case 0x18: 201 + case 3: 183 202 if (nlm_chip_is_xls_b()) 184 203 return PIC_PCIE_XLSB0_LINK3_IRQ; 185 204 else 186 205 return PIC_PCIE_LINK3_IRQ; 187 206 } 188 - WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); 207 + WARN(1, "Unexpected devfn %d\n", lnk->devfn); 189 208 return 0; 190 209 } 191 210 ··· 223 202 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) 224 203 { 225 204 struct msi_msg msg; 205 + struct pci_dev *lnk; 226 206 int irq, ret; 207 + u16 val; 208 + 209 + /* MSI not supported on XLR */ 210 + if (!nlm_chip_is_xls()) 211 + return 1; 212 + 213 + /* 214 + * Enable MSI on the XLS PCIe controller bridge which was disabled 215 + * at enumeration, the bridge MSI capability is at 0x50 216 + */ 217 + lnk = xls_get_pcie_link(dev); 218 + if (lnk == NULL) 219 + return 1; 220 + 221 + pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val); 222 + if ((val & PCI_MSI_FLAGS_ENABLE) == 0) { 223 + val |= PCI_MSI_FLAGS_ENABLE; 224 + pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val); 225 + } 227 226 228 227 irq = get_irq_vector(dev); 229 228 if (irq <= 0) ··· 368 327 } 369 328 } else { 370 329 /* XLR PCI controller ACK */ 371 - irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack); 330 + irq_set_handler_data(PIC_PCIX_IRQ, xlr_pci_ack); 372 331 } 373 332 374 333 return 0;
+1 -1
arch/mips/pmc-sierra/yosemite/smp.c
··· 115 115 */ 116 116 static void __cpuinit yos_init_secondary(void) 117 117 { 118 - set_c0_status(ST0_CO | ST0_IE | ST0_IM); 119 118 } 120 119 121 120 static void __cpuinit yos_smp_finish(void) 122 121 { 122 + set_c0_status(ST0_CO | ST0_IM | ST0_IE); 123 123 } 124 124 125 125 /* Hook for after all CPUs are online */
+1 -1
arch/mips/powertv/asic/asic-calliope.c
··· 28 28 29 29 #define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x)) 30 30 31 - const struct register_map calliope_register_map __initdata = { 31 + const struct register_map calliope_register_map __initconst = { 32 32 .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)}, 33 33 .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)}, 34 34 .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
+1 -1
arch/mips/powertv/asic/asic-cronus.c
··· 28 28 29 29 #define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x)) 30 30 31 - const struct register_map cronus_register_map __initdata = { 31 + const struct register_map cronus_register_map __initconst = { 32 32 .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)}, 33 33 .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)}, 34 34 .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)},
+1 -1
arch/mips/powertv/asic/asic-gaia.c
··· 23 23 #include <linux/init.h> 24 24 #include <asm/mach-powertv/asic.h> 25 25 26 - const struct register_map gaia_register_map __initdata = { 26 + const struct register_map gaia_register_map __initconst = { 27 27 .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000}, 28 28 .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038}, 29 29 .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C},
+1 -1
arch/mips/powertv/asic/asic-zeus.c
··· 28 28 29 29 #define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x)) 30 30 31 - const struct register_map zeus_register_map __initdata = { 31 + const struct register_map zeus_register_map __initconst = { 32 32 .eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)}, 33 33 .eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)}, 34 34 .eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)},
+1 -1
arch/mips/txx9/generic/pci.c
··· 269 269 return err; 270 270 } 271 271 272 - static void __init quirk_slc90e66_bridge(struct pci_dev *dev) 272 + static void __devinit quirk_slc90e66_bridge(struct pci_dev *dev) 273 273 { 274 274 int irq; /* PCI/ISA Bridge interrupt */ 275 275 u8 reg_64;