tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch kvm-arm64/vgic-fixes-7.1 into kvmarm-master/next

* kvm-arm64/vgic-fixes-7.1:
: .
: FIrst pass at fixing a number of vgic-v5 bugs that were found
: after the merge of the initial series.
: .
KVM: arm64: Advertise ID_AA64PFR2_EL1.GCIE
KVM: arm64: vgic-v5: Fold PPI state for all exposed PPIs
KVM: arm64: set_id_regs: Allow GICv3 support to be set at runtime
KVM: arm64: Don't advertises GICv3 in ID_PFR1_EL1 if AArch32 isn't supported
KVM: arm64: Correctly plumb ID_AA64PFR2_EL1 into pkvm idreg handling
KVM: arm64: Move GICv5 timer PPI validation into timer_irqs_are_valid()
KVM: arm64: Remove evaluation of timer state in kvm_cpu_has_pending_timer()
KVM: arm64: Kill arch_timer_context::direct field
KVM: arm64: vgic-v5: Correctly set dist->ready once initialised
KVM: arm64: vgic-v5: Make the effective priority mask a strict limit
KVM: arm64: vgic-v5: Cast vgic_apr to u32 to avoid undefined behaviours
KVM: arm64: vgic-v5: Transfer edge pending state to ICH_PPI_PENDRx_EL2
KVM: arm64: vgic-v5: Hold config_lock while finalizing GICv5 PPIs
KVM: arm64: Account for RESx bits in __compute_fgt()
KVM: arm64: Fix writeable mask for ID_AA64PFR2_EL1
arm64: Fix field references for ICH_PPI_DVIR[01]_EL2
KVM: arm64: Don't skip per-vcpu NV initialisation
KVM: arm64: vgic: Don't reset cpuif/redist addresses at finalize time

Signed-off-by: Marc Zyngier <maz@kernel.org>

Marc Zyngier d77f4792 83a39807

+125 -92
+1 -8
arch/arm64/include/asm/kvm_host.h
··· 821 821 822 822 /* PPI state tracking for GICv5-based guests */ 823 823 struct { 824 - /* 825 - * For tracking the PPI pending state, we need both the entry 826 - * state and exit state to correctly detect edges as it is 827 - * possible that an interrupt has been injected in software in 828 - * the interim. 829 - */ 830 - DECLARE_BITMAP(pendr_entry, VGIC_V5_NR_PRIVATE_IRQS); 831 - DECLARE_BITMAP(pendr_exit, VGIC_V5_NR_PRIVATE_IRQS); 824 + DECLARE_BITMAP(pendr, VGIC_V5_NR_PRIVATE_IRQS); 832 825 833 826 /* The saved state of the regs when leaving the guest */ 834 827 DECLARE_BITMAP(activer_exit, VGIC_V5_NR_PRIVATE_IRQS);
+1
arch/arm64/kernel/cpufeature.c
··· 325 325 326 326 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 327 327 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 328 + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_GCIE_SHIFT, 4, ID_AA64PFR2_EL1_GCIE_NI), 328 329 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 329 330 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 330 331 ARM64_FTR_END,
+14 -18
arch/arm64/kvm/arch_timer.c
··· 183 183 map->emul_ptimer = vcpu_ptimer(vcpu); 184 184 } 185 185 186 - map->direct_vtimer->direct = true; 187 - if (map->direct_ptimer) 188 - map->direct_ptimer->direct = true; 189 - 190 186 trace_kvm_get_timer_map(vcpu->vcpu_id, map); 191 187 } 192 188 ··· 402 406 403 407 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 404 408 { 405 - struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); 406 - struct arch_timer_context *ptimer = vcpu_ptimer(vcpu); 407 - 408 - return kvm_timer_should_fire(vtimer) || kvm_timer_should_fire(ptimer) || 409 - (vcpu_has_wfit_active(vcpu) && wfit_delay_ns(vcpu) == 0); 409 + return vcpu_has_wfit_active(vcpu) && wfit_delay_ns(vcpu) == 0; 410 410 } 411 411 412 412 /* ··· 454 462 return; 455 463 456 464 /* Skip injecting on GICv5 for directly injected (DVI'd) timers */ 457 - if (vgic_is_v5(vcpu->kvm) && timer_ctx->direct) 458 - return; 465 + if (vgic_is_v5(vcpu->kvm)) { 466 + struct timer_map map; 467 + 468 + get_timer_map(vcpu, &map); 469 + 470 + if (map.direct_ptimer == timer_ctx || 471 + map.direct_vtimer == timer_ctx) 472 + return; 473 + } 459 474 460 475 kvm_vgic_inject_irq(vcpu->kvm, vcpu, 461 476 timer_irq(timer_ctx), ··· 1543 1544 if (kvm_vgic_set_owner(vcpu, irq, ctx)) 1544 1545 break; 1545 1546 1547 + /* With GICv5, the default PPI is what you get -- nothing else */ 1548 + if (vgic_is_v5(vcpu->kvm) && irq != get_vgic_ppi(vcpu->kvm, default_ppi[i])) 1549 + break; 1550 + 1546 1551 /* 1547 1552 * We know by construction that we only have PPIs, so all values 1548 1553 * are less than 32 for non-GICv5 VGICs. On GICv5, they are ··· 1681 1678 default: 1682 1679 return -ENXIO; 1683 1680 } 1684 - 1685 - /* 1686 - * The PPIs for the Arch Timers are architecturally defined for 1687 - * GICv5. Reject anything that changes them from the specified value. 1688 - */ 1689 - if (vgic_is_v5(vcpu->kvm) && vcpu->kvm->arch.timer_data.ppi[idx] != irq) 1690 - return -EINVAL; 1691 1681 1692 1682 /* 1693 1683 * We cannot validate the IRQ unicity before we run, so take it at
+2 -2
arch/arm64/kvm/config.c
··· 1663 1663 clear |= ~nested & m->nmask; 1664 1664 } 1665 1665 1666 - val |= set; 1667 - val &= ~clear; 1666 + val |= set | m->res1; 1667 + val &= ~(clear | m->res0); 1668 1668 *vcpu_fgt(vcpu, reg) = val; 1669 1669 } 1670 1670
+1 -1
arch/arm64/kvm/hyp/nvhe/sys_regs.c
··· 447 447 /* CRm=4 */ 448 448 AARCH64(SYS_ID_AA64PFR0_EL1), 449 449 AARCH64(SYS_ID_AA64PFR1_EL1), 450 - ID_UNALLOCATED(4,2), 450 + AARCH64(SYS_ID_AA64PFR2_EL1), 451 451 ID_UNALLOCATED(4,3), 452 452 AARCH64(SYS_ID_AA64ZFR0_EL1), 453 453 ID_UNALLOCATED(4,5),
+3 -3
arch/arm64/kvm/hyp/vgic-v5-sr.c
··· 37 37 38 38 bitmap_write(host_data_ptr(vgic_v5_ppi_state)->activer_exit, 39 39 read_sysreg_s(SYS_ICH_PPI_ACTIVER0_EL2), 0, 64); 40 - bitmap_write(host_data_ptr(vgic_v5_ppi_state)->pendr_exit, 40 + bitmap_write(host_data_ptr(vgic_v5_ppi_state)->pendr, 41 41 read_sysreg_s(SYS_ICH_PPI_PENDR0_EL2), 0, 64); 42 42 43 43 cpu_if->vgic_ppi_priorityr[0] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR0_EL2); ··· 52 52 if (VGIC_V5_NR_PRIVATE_IRQS == 128) { 53 53 bitmap_write(host_data_ptr(vgic_v5_ppi_state)->activer_exit, 54 54 read_sysreg_s(SYS_ICH_PPI_ACTIVER1_EL2), 64, 64); 55 - bitmap_write(host_data_ptr(vgic_v5_ppi_state)->pendr_exit, 55 + bitmap_write(host_data_ptr(vgic_v5_ppi_state)->pendr, 56 56 read_sysreg_s(SYS_ICH_PPI_PENDR1_EL2), 64, 64); 57 57 58 58 cpu_if->vgic_ppi_priorityr[8] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR8_EL2); ··· 87 87 SYS_ICH_PPI_ENABLER0_EL2); 88 88 89 89 /* Update the pending state of the NON-DVI'd PPIs, only */ 90 - bitmap_andnot(pendr, host_data_ptr(vgic_v5_ppi_state)->pendr_entry, 90 + bitmap_andnot(pendr, host_data_ptr(vgic_v5_ppi_state)->pendr, 91 91 cpu_if->vgic_ppi_dvir, VGIC_V5_NR_PRIVATE_IRQS); 92 92 write_sysreg_s(bitmap_read(pendr, 0, 64), SYS_ICH_PPI_PENDR0_EL2); 93 93
+10 -10
arch/arm64/kvm/sys_regs.c
··· 3304 3304 ID_AA64PFR1_EL1_MPAM_frac | 3305 3305 ID_AA64PFR1_EL1_MTE)), 3306 3306 ID_FILTERED(ID_AA64PFR2_EL1, id_aa64pfr2_el1, 3307 - ~(ID_AA64PFR2_EL1_FPMR | 3308 - ID_AA64PFR2_EL1_MTEFAR | 3309 - ID_AA64PFR2_EL1_MTESTOREONLY | 3310 - ID_AA64PFR2_EL1_GCIE)), 3307 + (ID_AA64PFR2_EL1_FPMR | 3308 + ID_AA64PFR2_EL1_MTEFAR | 3309 + ID_AA64PFR2_EL1_MTESTOREONLY | 3310 + ID_AA64PFR2_EL1_GCIE)), 3311 3311 ID_UNALLOCATED(4,3), 3312 3312 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 3313 3313 ID_HIDDEN(ID_AA64SMFR0_EL1), ··· 5772 5772 5773 5773 guard(mutex)(&kvm->arch.config_lock); 5774 5774 5775 + if (vcpu_has_nv(vcpu)) { 5776 + int ret = kvm_init_nv_sysregs(vcpu); 5777 + if (ret) 5778 + return ret; 5779 + } 5780 + 5775 5781 if (kvm_vm_has_ran_once(kvm)) 5776 5782 return 0; 5777 5783 ··· 5824 5818 * problem for GICv5-based guests in the future. 5825 5819 */ 5826 5820 kvm_vgic_finalize_idregs(kvm); 5827 - } 5828 - 5829 - if (vcpu_has_nv(vcpu)) { 5830 - int ret = kvm_init_nv_sysregs(vcpu); 5831 - if (ret) 5832 - return ret; 5833 5821 } 5834 5822 5835 5823 return 0;
+22 -10
arch/arm64/kvm/vgic/vgic-init.c
··· 147 147 kvm->arch.vgic.implementation_rev = KVM_VGIC_IMP_REV_LATEST; 148 148 kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; 149 149 150 + switch (type) { 151 + case KVM_DEV_TYPE_ARM_VGIC_V2: 152 + kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; 153 + break; 154 + case KVM_DEV_TYPE_ARM_VGIC_V3: 155 + INIT_LIST_HEAD(&kvm->arch.vgic.rd_regions); 156 + break; 157 + } 158 + 150 159 /* 151 160 * We've now created the GIC. Update the system register state 152 161 * to accurately reflect what we've created. ··· 657 648 needs_dist = false; 658 649 } 659 650 660 - if (ret || !needs_dist) 651 + if (ret) 661 652 goto out; 662 653 663 - dist_base = dist->vgic_dist_base; 664 - mutex_unlock(&kvm->arch.config_lock); 654 + if (needs_dist) { 655 + dist_base = dist->vgic_dist_base; 656 + mutex_unlock(&kvm->arch.config_lock); 665 657 666 - ret = vgic_register_dist_iodev(kvm, dist_base, type); 667 - if (ret) { 668 - kvm_err("Unable to register VGIC dist MMIO regions\n"); 669 - goto out_slots; 658 + ret = vgic_register_dist_iodev(kvm, dist_base, type); 659 + if (ret) { 660 + kvm_err("Unable to register VGIC dist MMIO regions\n"); 661 + goto out_slots; 662 + } 663 + } else { 664 + mutex_unlock(&kvm->arch.config_lock); 670 665 } 671 666 672 667 smp_store_release(&dist->ready, true); ··· 697 684 698 685 switch (type) { 699 686 case KVM_DEV_TYPE_ARM_VGIC_V2: 700 - kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; 701 687 break; 702 688 case KVM_DEV_TYPE_ARM_VGIC_V3: 703 - INIT_LIST_HEAD(&kvm->arch.vgic.rd_regions); 704 689 aa64pfr0 |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 705 - pfr1 |= SYS_FIELD_PREP_ENUM(ID_PFR1_EL1, GIC, GICv3); 690 + if (kvm_supports_32bit_el0()) 691 + pfr1 |= SYS_FIELD_PREP_ENUM(ID_PFR1_EL1, GIC, GICv3); 706 692 break; 707 693 case KVM_DEV_TYPE_ARM_VGIC_V5: 708 694 aa64pfr2 |= SYS_FIELD_PREP_ENUM(ID_AA64PFR2_EL1, GCIE, IMP);
+24 -28
arch/arm64/kvm/vgic/vgic-v5.c
··· 172 172 if (!vgic_is_v5(kvm)) 173 173 return 0; 174 174 175 + guard(mutex)(&kvm->arch.config_lock); 176 + 177 + /* 178 + * If SW_PPI has been advertised, then we know we already 179 + * initialised the whole thing, and we can return early. Yes, 180 + * this is pretty hackish as far as state tracking goes... 181 + */ 182 + if (test_bit(GICV5_ARCH_PPI_SW_PPI, kvm->arch.vgic.gicv5_vm.vgic_ppi_mask)) 183 + return 0; 184 + 175 185 /* The PPI state for all VCPUs should be the same. Pick the first. */ 176 186 vcpu0 = kvm_get_vcpu(kvm, 0); 177 187 ··· 212 202 static u32 vgic_v5_get_effective_priority_mask(struct kvm_vcpu *vcpu) 213 203 { 214 204 struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5; 215 - u32 highest_ap, priority_mask; 205 + u32 highest_ap, priority_mask, apr; 216 206 217 207 /* 218 208 * If the guest's CPU has not opted to receive interrupts, then the ··· 227 217 * priority. Explicitly use the 32-bit version here as we have 32 228 218 * priorities. 32 then means that there are no active priorities. 229 219 */ 230 - highest_ap = cpu_if->vgic_apr ? __builtin_ctz(cpu_if->vgic_apr) : 32; 220 + apr = cpu_if->vgic_apr; 221 + highest_ap = apr ? __builtin_ctz(apr) : 32; 231 222 232 223 /* 233 224 * An interrupt is of sufficient priority if it is equal to or ··· 366 355 irq = vgic_get_vcpu_irq(vcpu, intid); 367 356 368 357 scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) 369 - has_pending = (irq->enabled && irq_is_pending(irq) && 370 - irq->priority <= priority_mask); 358 + if (irq->enabled && irq->priority < priority_mask) 359 + has_pending = irq->hw ? vgic_get_phys_line_level(irq) : irq_is_pending(irq); 371 360 372 361 vgic_put_irq(vcpu->kvm, irq); 373 362 ··· 385 374 void vgic_v5_fold_ppi_state(struct kvm_vcpu *vcpu) 386 375 { 387 376 struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5; 388 - DECLARE_BITMAP(changed_active, VGIC_V5_NR_PRIVATE_IRQS); 389 - DECLARE_BITMAP(changed_pending, VGIC_V5_NR_PRIVATE_IRQS); 390 - DECLARE_BITMAP(changed_bits, VGIC_V5_NR_PRIVATE_IRQS); 391 - unsigned long *activer, *pendr_entry, *pendr; 377 + unsigned long *activer, *pendr; 392 378 int i; 393 379 394 380 activer = host_data_ptr(vgic_v5_ppi_state)->activer_exit; 395 - pendr_entry = host_data_ptr(vgic_v5_ppi_state)->pendr_entry; 396 - pendr = host_data_ptr(vgic_v5_ppi_state)->pendr_exit; 381 + pendr = host_data_ptr(vgic_v5_ppi_state)->pendr; 397 382 398 - bitmap_xor(changed_active, cpu_if->vgic_ppi_activer, activer, 399 - VGIC_V5_NR_PRIVATE_IRQS); 400 - bitmap_xor(changed_pending, pendr_entry, pendr, 401 - VGIC_V5_NR_PRIVATE_IRQS); 402 - bitmap_or(changed_bits, changed_active, changed_pending, 403 - VGIC_V5_NR_PRIVATE_IRQS); 404 - 405 - for_each_set_bit(i, changed_bits, VGIC_V5_NR_PRIVATE_IRQS) { 383 + for_each_set_bit(i, vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_mask, 384 + VGIC_V5_NR_PRIVATE_IRQS) { 406 385 u32 intid = vgic_v5_make_ppi(i); 407 386 struct vgic_irq *irq; 408 387 ··· 436 435 437 436 irq = vgic_get_vcpu_irq(vcpu, intid); 438 437 439 - scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) 438 + scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) { 440 439 __assign_bit(i, pendr, irq_is_pending(irq)); 440 + if (irq->config == VGIC_CONFIG_EDGE) 441 + irq->pending_latch = false; 442 + } 441 443 442 444 vgic_put_irq(vcpu->kvm, irq); 443 445 } ··· 452 448 * incoming changes are merged with the outgoing changes on the return 453 449 * path. 454 450 */ 455 - bitmap_copy(host_data_ptr(vgic_v5_ppi_state)->pendr_entry, pendr, 456 - VGIC_V5_NR_PRIVATE_IRQS); 457 - 458 - /* 459 - * Make sure that we can correctly detect "edges" in the PPI 460 - * state. There's a path where we never actually enter the guest, and 461 - * failure to do this risks losing pending state 462 - */ 463 - bitmap_copy(host_data_ptr(vgic_v5_ppi_state)->pendr_exit, pendr, 451 + bitmap_copy(host_data_ptr(vgic_v5_ppi_state)->pendr, pendr, 464 452 VGIC_V5_NR_PRIVATE_IRQS); 465 453 } 466 454
+2 -2
arch/arm64/tools/sysreg
··· 4888 4888 EndSysregFields 4889 4889 4890 4890 Sysreg ICH_PPI_DVIR0_EL2 3 4 12 10 0 4891 - Fields ICH_PPI_DVIx_EL2 4891 + Fields ICH_PPI_DVIRx_EL2 4892 4892 EndSysreg 4893 4893 4894 4894 Sysreg ICH_PPI_DVIR1_EL2 3 4 12 10 1 4895 - Fields ICH_PPI_DVIx_EL2 4895 + Fields ICH_PPI_DVIRx_EL2 4896 4896 EndSysreg 4897 4897 4898 4898 SysregFields ICH_PPI_ENABLERx_EL2
-3
include/kvm/arm_arch_timer.h
··· 76 76 77 77 /* Duplicated state from arch_timer.c for convenience */ 78 78 u32 host_timer_irq; 79 - 80 - /* Is this a direct timer? */ 81 - bool direct; 82 79 }; 83 80 84 81 struct timer_map {
+45 -7
tools/testing/selftests/kvm/arm64/set_id_regs.c
··· 37 37 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value. 38 38 */ 39 39 int64_t safe_val; 40 + 41 + /* Allowed to be changed by the host after run */ 42 + bool mutable; 40 43 }; 41 44 42 45 struct test_feature_reg { ··· 47 44 const struct reg_ftr_bits *ftr_bits; 48 45 }; 49 46 50 - #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \ 47 + #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL, MUT) \ 51 48 { \ 52 49 .name = #NAME, \ 53 50 .sign = SIGNED, \ ··· 55 52 .shift = SHIFT, \ 56 53 .mask = MASK, \ 57 54 .safe_val = SAFE_VAL, \ 55 + .mutable = MUT, \ 58 56 } 59 57 60 58 #define REG_FTR_BITS(type, reg, field, safe_val) \ 61 59 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \ 62 - reg##_##field##_MASK, safe_val) 60 + reg##_##field##_MASK, safe_val, false) 61 + 62 + #define REG_FTR_BITS_MUTABLE(type, reg, field, safe_val) \ 63 + __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \ 64 + reg##_##field##_MASK, safe_val, true) 63 65 64 66 #define S_REG_FTR_BITS(type, reg, field, safe_val) \ 65 67 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \ 66 - reg##_##field##_MASK, safe_val) 68 + reg##_##field##_MASK, safe_val, false) 67 69 68 70 #define REG_FTR_END \ 69 71 { \ ··· 142 134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0), 143 135 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0), 144 136 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0), 145 - REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0), 137 + /* GICv3 support will be forced at run time if available */ 138 + REG_FTR_BITS_MUTABLE(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0), 146 139 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 1), 147 140 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 1), 148 141 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 1), ··· 643 634 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac no longer 0xF\n"); 644 635 } 645 636 637 + static uint64_t reset_mutable_bits(uint32_t id, uint64_t val) 638 + { 639 + struct test_feature_reg *reg = NULL; 640 + 641 + for (int i = 0; i < ARRAY_SIZE(test_regs); i++) { 642 + if (test_regs[i].reg == id) { 643 + reg = &test_regs[i]; 644 + break; 645 + } 646 + } 647 + 648 + if (!reg) 649 + return val; 650 + 651 + for (const struct reg_ftr_bits *bits = reg->ftr_bits; bits->type != FTR_END; bits++) { 652 + if (bits->mutable) { 653 + val &= ~bits->mask; 654 + val |= bits->safe_val << bits->shift; 655 + } 656 + } 657 + 658 + return val; 659 + } 660 + 646 661 static void test_guest_reg_read(struct kvm_vcpu *vcpu) 647 662 { 648 663 bool done = false; 649 664 struct ucall uc; 650 665 651 666 while (!done) { 667 + uint64_t val; 668 + 652 669 vcpu_run(vcpu); 653 670 654 671 switch (get_ucall(vcpu, &uc)) { ··· 682 647 REPORT_GUEST_ASSERT(uc); 683 648 break; 684 649 case UCALL_SYNC: 650 + val = test_reg_vals[encoding_to_range_idx(uc.args[2])]; 651 + val = reset_mutable_bits(uc.args[2], val); 652 + 685 653 /* Make sure the written values are seen by guest */ 686 - TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])], 687 - uc.args[3]); 654 + TEST_ASSERT_EQ(val, reset_mutable_bits(uc.args[2], uc.args[3])); 688 655 break; 689 656 case UCALL_DONE: 690 657 done = true; ··· 777 740 uint64_t observed; 778 741 779 742 observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding)); 780 - TEST_ASSERT_EQ(test_reg_vals[idx], observed); 743 + TEST_ASSERT_EQ(reset_mutable_bits(encoding, test_reg_vals[idx]), 744 + reset_mutable_bits(encoding, observed)); 781 745 } 782 746 783 747 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu)