tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/i915/display: Add DC Balance flip count operations

Track dc balance flip count with params per crtc. Increment
DC Balance Flip count before every flip to indicate DMC
firmware about new flip occurrence which needs to be adjusted
for dc balancing. This is tracked separately from legacy
FLIP_COUNT register also Reset DC balance flip count value
while disabling VRR adaptive mode, this is to start with
fresh counts when VRR adaptive refresh mode is triggered again.

--v2:
- Call during intel_update_crtc.(Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-11-mitulkumar.ajitkumar.golani@intel.com

authored by

Mitul Golani and committed by
Ankit Nautiyal d780bbeb 80d14983

+24
+3
drivers/gpu/drm/i915/display/intel_display.c
··· 6864 6864 intel_crtc_update_active_timings(new_crtc_state, 6865 6865 new_crtc_state->vrr.enable); 6866 6866 6867 + if (new_crtc_state->vrr.dc_balance.enable) 6868 + intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc); 6869 + 6867 6870 /* 6868 6871 * We usually enable FIFO underrun interrupts as part of the 6869 6872 * CRTC enable sequence during modesets. But when we inherit a
+4
drivers/gpu/drm/i915/display/intel_display_types.h
··· 1531 1531 struct intel_link_m_n m_n, m2_n2; 1532 1532 } drrs; 1533 1533 1534 + struct { 1535 + u64 flip_count; 1536 + } dc_balance; 1537 + 1534 1538 int scanline_offset; 1535 1539 1536 1540 struct {
+15
drivers/gpu/drm/i915/display/intel_vrr.c
··· 647 647 } 648 648 649 649 void 650 + intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state, 651 + struct intel_crtc *crtc) 652 + { 653 + struct intel_display *display = to_intel_display(crtc_state); 654 + enum pipe pipe = crtc->pipe; 655 + 656 + if (!crtc_state->vrr.dc_balance.enable) 657 + return; 658 + 659 + intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 660 + ++crtc->dc_balance.flip_count); 661 + } 662 + 663 + void 650 664 intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state, 651 665 struct intel_crtc *crtc) 652 666 { ··· 670 656 if (!old_crtc_state->vrr.dc_balance.enable) 671 657 return; 672 658 659 + intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0); 673 660 intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0); 674 661 } 675 662
+2
drivers/gpu/drm/i915/display/intel_vrr.h
··· 29 29 const struct intel_crtc_state *crtc_state); 30 30 void intel_vrr_check_push_sent(struct intel_dsb *dsb, 31 31 const struct intel_crtc_state *crtc_state); 32 + void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state, 33 + struct intel_crtc *crtc); 32 34 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state); 33 35 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state); 34 36 void intel_vrr_get_config(struct intel_crtc_state *crtc_state);