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usb: dwc3-am62: Fix PHY core voltage selection

TRM information is outdated and design team has confirmed
that PHY_CORE_VOLTAGE should be 0 irrespective of
VDD_CORE voltage.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20240227-for-v6-9-am62-usb-errata-3-0-v4-3-0ada8ddb0767@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Roger Quadros and committed by
Greg Kroah-Hartman
d78ff375 4ead695e

+9 -1
+9 -1
drivers/usb/dwc3/dwc3-am62.c
··· 97 97 #define USBSS_VBUS_STAT_SESSVALID BIT(2) 98 98 #define USBSS_VBUS_STAT_VBUSVALID BIT(0) 99 99 100 - /* Mask for PHY PLL REFCLK */ 100 + /* USB_PHY_CTRL register bits in CTRL_MMR */ 101 + #define PHY_CORE_VOLTAGE_MASK BIT(31) 101 102 #define PHY_PLL_REFCLK_MASK GENMASK(3, 0) 102 103 103 104 #define DWC3_AM62_AUTOSUSPEND_DELAY 100 ··· 162 161 return ret; 163 162 164 163 am62->offset = args.args[0]; 164 + 165 + /* Core voltage. PHY_CORE_VOLTAGE bit Recommended to be 0 always */ 166 + ret = regmap_update_bits(am62->syscon, am62->offset, PHY_CORE_VOLTAGE_MASK, 0); 167 + if (ret) { 168 + dev_err(dev, "failed to set phy core voltage\n"); 169 + return ret; 170 + } 165 171 166 172 ret = regmap_update_bits(am62->syscon, am62->offset, PHY_PLL_REFCLK_MASK, am62->rate_code); 167 173 if (ret) {