Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: Extend gpu devcore dumps with pgtbl info
In the case of iova fault triggered devcore dumps, include additional
debug information based on what we think is the current page tables,
including the TTBR0 value (which should match what we have in
adreno_smmu_fault_info unless things have gone horribly wrong), and
the pagetable entries traversed in the process of resolving the
faulting iova.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/628117/
+51
-1
+10
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+10
drivers/gpu/drm/msm/adreno/adreno_gpu.c
···
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883
drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ");
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drm_printf(p, " - type=%s\n", info->type);
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drm_printf(p, " - source=%s\n", info->block);
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+
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/* Information extracted from what we think are the current
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* pgtables. Hopefully the TTBR0 matches what we've extracted
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* from the SMMU registers in smmu_info!
890
+
*/
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drm_puts(p, "pgtable-fault-info:\n");
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drm_printf(p, " - ttbr0: %.16llx\n", (u64)info->pgtbl_ttbr0);
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drm_printf(p, " - asid: %d\n", info->asid);
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drm_printf(p, " - ptes: %.16llx %.16llx %.16llx %.16llx\n",
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info->ptes[0], info->ptes[1], info->ptes[2], info->ptes[3]);
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}
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drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
+9
drivers/gpu/drm/msm/msm_gpu.c
+9
drivers/gpu/drm/msm/msm_gpu.c
···
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if (submit) {
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int i;
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+
if (state->fault_info.ttbr0) {
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struct msm_gpu_fault_info *info = &state->fault_info;
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struct msm_mmu *mmu = submit->aspace->mmu;
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+
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msm_iommu_pagetable_params(mmu, &info->pgtbl_ttbr0,
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+
&info->asid);
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msm_iommu_pagetable_walk(mmu, info->iova, info->ptes);
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+
}
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+
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state->bos = kcalloc(submit->nr_bos,
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sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
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+8
drivers/gpu/drm/msm/msm_gpu.h
+8
drivers/gpu/drm/msm/msm_gpu.h
···
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int flags;
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const char *type;
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const char *block;
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+
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/* Information about what we think/expect is the current SMMU state,
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* for example expected_ttbr0 should match smmu_info.ttbr0 which
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* was read back from SMMU registers.
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+
*/
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phys_addr_t pgtbl_ttbr0;
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u64 ptes[4];
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int asid;
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};
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/**
+22
drivers/gpu/drm/msm/msm_iommu.c
+22
drivers/gpu/drm/msm/msm_iommu.c
···
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return &iommu->domain->geometry;
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}
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+
int
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msm_iommu_pagetable_walk(struct msm_mmu *mmu, unsigned long iova, uint64_t ptes[4])
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{
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struct msm_iommu_pagetable *pagetable;
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struct arm_lpae_io_pgtable_walk_data wd = {};
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+
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if (mmu->type != MSM_MMU_IOMMU_PAGETABLE)
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return -EINVAL;
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+
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pagetable = to_pagetable(mmu);
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+
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if (!pagetable->pgtbl_ops->pgtable_walk)
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return -EINVAL;
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+
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pagetable->pgtbl_ops->pgtable_walk(pagetable->pgtbl_ops, iova, &wd);
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+
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for (int i = 0; i < ARRAY_SIZE(wd.ptes); i++)
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ptes[i] = wd.ptes[i];
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return 0;
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+
}
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+
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static const struct msm_mmu_funcs pagetable_funcs = {
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.map = msm_iommu_pagetable_map,
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.unmap = msm_iommu_pagetable_unmap,
+2
-1
drivers/gpu/drm/msm/msm_mmu.h
+2
-1
drivers/gpu/drm/msm/msm_mmu.h
···
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struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent);
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int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
57
-
int *asid);
57
+
int *asid);
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+
int msm_iommu_pagetable_walk(struct msm_mmu *mmu, unsigned long iova, uint64_t ptes[4]);
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struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu);
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#endif /* __MSM_MMU_H__ */