thermal: intel: int340x: processor: Move MMIO primitives to MMIO driver

MMIO-specific primitives differ from those used by the TPMI interface.
The MSR and MMIO interfaces shared the same primitives in the common
driver, but MMIO does not require many MSR-specific entries (like PSYS).
Keeping these in the common driver does not add any value and requires
interface-specific handling logic that makes the common layer
unnecessarily complex.

Move the MMIO primitive definitions and associated bitmasks into the
MMIO interface driver. This change includes:

1. Add MMIO-local struct rapl_primitive_info instance without
MSR-specific entries and assign it to priv->rpi during MMIO
initialization.
2. Remove the RAPL MMIO case from rapl_config() in the common driver.

No functional changes are intended.

Co-developed-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: https://patch.msgid.link/20260331211950.3329932-6-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

authored by

Kuppuswamy Sathyanarayanan and committed by

Rafael J. Wysocki 2 months ago d7a718ff b874996a

+72 -1

2 changed files

expand all

drivers

powercap

intel_rapl_common.c

thermal

intel

int340x_thermal

processor_thermal_rapl.c

-1

drivers/powercap/intel_rapl_common.c

··· 670 670 { 671 671 switch (rp->priv->type) { 672 672 /* MMIO I/F shares the same register layout as MSR registers */ 673 - case RAPL_IF_MMIO: 674 673 case RAPL_IF_MSR: 675 674 rp->priv->rpi = rpi_msr; 676 675 break;

+72

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

··· 11 11 12 12 static struct rapl_if_priv rapl_mmio_priv; 13 13 14 + /* bitmasks for RAPL MSRs, used by primitive access functions */ 15 + #define MMIO_ENERGY_STATUS_MASK GENMASK(31, 0) 16 + 17 + #define MMIO_POWER_LIMIT1_MASK GENMASK(14, 0) 18 + #define MMIO_POWER_LIMIT1_ENABLE BIT(15) 19 + #define MMIO_POWER_LIMIT1_CLAMP BIT(16) 20 + 21 + #define MMIO_POWER_LIMIT2_MASK GENMASK_ULL(46, 32) 22 + #define MMIO_POWER_LIMIT2_ENABLE BIT_ULL(47) 23 + #define MMIO_POWER_LIMIT2_CLAMP BIT_ULL(48) 24 + 25 + #define MMIO_POWER_LOW_LOCK BIT(31) 26 + #define MMIO_POWER_HIGH_LOCK BIT_ULL(63) 27 + 28 + #define MMIO_POWER_LIMIT4_MASK GENMASK(12, 0) 29 + 30 + #define MMIO_TIME_WINDOW1_MASK GENMASK_ULL(23, 17) 31 + #define MMIO_TIME_WINDOW2_MASK GENMASK_ULL(55, 49) 32 + 33 + #define MMIO_POWER_INFO_MAX_MASK GENMASK_ULL(46, 32) 34 + #define MMIO_POWER_INFO_MIN_MASK GENMASK_ULL(30, 16) 35 + #define MMIO_POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48) 36 + #define MMIO_POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0) 37 + 38 + #define MMIO_PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) 39 + #define MMIO_PP_POLICY_MASK GENMASK(4, 0) 40 + 41 + /* RAPL primitives for MMIO I/F */ 42 + static struct rapl_primitive_info rpi_mmio[NR_RAPL_PRIMITIVES] = { 43 + /* name, mask, shift, msr index, unit divisor */ 44 + [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, MMIO_POWER_LIMIT1_MASK, 0, 45 + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 46 + [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, MMIO_POWER_LIMIT2_MASK, 32, 47 + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 48 + [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, MMIO_POWER_LIMIT4_MASK, 0, 49 + RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), 50 + [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, MMIO_ENERGY_STATUS_MASK, 0, 51 + RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), 52 + [FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_LOW_LOCK, 31, 53 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 54 + [FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_HIGH_LOCK, 63, 55 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 56 + [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, MMIO_POWER_LIMIT1_ENABLE, 15, 57 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 58 + [PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, MMIO_POWER_LIMIT1_CLAMP, 16, 59 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 60 + [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, MMIO_POWER_LIMIT2_ENABLE, 47, 61 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 62 + [PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, MMIO_POWER_LIMIT2_CLAMP, 48, 63 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 64 + [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, MMIO_TIME_WINDOW1_MASK, 17, 65 + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 66 + [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, MMIO_TIME_WINDOW2_MASK, 49, 67 + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 68 + [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, 69 + MMIO_POWER_INFO_THERMAL_SPEC_MASK, 0, 70 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 71 + [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, MMIO_POWER_INFO_MAX_MASK, 32, 72 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 73 + [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, MMIO_POWER_INFO_MIN_MASK, 16, 74 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 75 + [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, 76 + MMIO_POWER_INFO_MAX_TIME_WIN_MASK, 48, 77 + RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), 78 + [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, 79 + MMIO_PERF_STATUS_THROTTLE_TIME_MASK, 0, 80 + RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), 81 + [PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, MMIO_PP_POLICY_MASK, 0, 82 + RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), 83 + }; 84 + 14 85 static const struct rapl_mmio_regs rapl_mmio_default = { 15 86 .reg_unit = 0x5938, 16 87 .regs[RAPL_DOMAIN_PACKAGE] = { 0x59a0, 0x593c, 0x58f0, 0, 0x5930, 0x59b0}, ··· 146 75 rapl_mmio_priv.read_raw = rapl_mmio_read_raw; 147 76 rapl_mmio_priv.write_raw = rapl_mmio_write_raw; 148 77 rapl_mmio_priv.defaults = &rapl_defaults_mmio; 78 + rapl_mmio_priv.rpi = rpi_mmio; 149 79 150 80 rapl_mmio_priv.control_type = powercap_register_control_type(NULL, "intel-rapl-mmio", NULL); 151 81 if (IS_ERR(rapl_mmio_priv.control_type)) {

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