Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'timers-v6.12-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull clockevent/clocksource updates from Daniel Lezcano:
- Add the DT binding for the rk3576 compatible (Detlev Casanova)
- Use for_each_available_child_of_node_scoped() to remove the
of_node_put() calls in the loop (Zhang Zekun)
- Add the ability to register external callbacks for suspend/resume on
ACPI PM driver and enable to turn it off when suspended (Marek
Maslanka)
- Use the devm_clk_get_enabled() variant on the ingenic timer (Huan
Yang)
- Add missing iounmap() on errors in msm_dt_timer_init() (Ankit
Agrawal)
- Add missing clk_disable_unprepare() in init routine error code path
on the asm9260 and the cadence_ttc timers (Gaosheng Cui)
- Use request_percpu_irq() instead of request_irq() in order to fix a
wrong address space access reported by sparse (Uros Bizjak)
- Fix comment format for the pmc_core_acpi_pm_timer_suspend_resume()
function (Marek Maslanka)
Link: https://lore.kernel.org/all/6054852d-975f-4e83-850e-815f263a40c5@linaro.org
+129
-21
+1
Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml
+1
Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml
+32
drivers/clocksource/acpi_pm.c
+32
drivers/clocksource/acpi_pm.c
···
25
25
#include <asm/io.h>
26
26
#include <asm/time.h>
27
27
28
+
static void *suspend_resume_cb_data;
29
+
30
+
static void (*suspend_resume_callback)(void *data, bool suspend);
31
+
28
32
/*
29
33
* The I/O port the PMTMR resides at.
30
34
* The location is detected during setup_arch(),
···
62
58
return v2;
63
59
}
64
60
61
+
void acpi_pmtmr_register_suspend_resume_callback(void (*cb)(void *data, bool suspend), void *data)
62
+
{
63
+
suspend_resume_callback = cb;
64
+
suspend_resume_cb_data = data;
65
+
}
66
+
EXPORT_SYMBOL_GPL(acpi_pmtmr_register_suspend_resume_callback);
67
+
68
+
void acpi_pmtmr_unregister_suspend_resume_callback(void)
69
+
{
70
+
suspend_resume_callback = NULL;
71
+
suspend_resume_cb_data = NULL;
72
+
}
73
+
EXPORT_SYMBOL_GPL(acpi_pmtmr_unregister_suspend_resume_callback);
74
+
75
+
static void acpi_pm_suspend(struct clocksource *cs)
76
+
{
77
+
if (suspend_resume_callback)
78
+
suspend_resume_callback(suspend_resume_cb_data, true);
79
+
}
80
+
81
+
static void acpi_pm_resume(struct clocksource *cs)
82
+
{
83
+
if (suspend_resume_callback)
84
+
suspend_resume_callback(suspend_resume_cb_data, false);
85
+
}
86
+
65
87
static u64 acpi_pm_read(struct clocksource *cs)
66
88
{
67
89
return (u64)read_pmtmr();
···
99
69
.read = acpi_pm_read,
100
70
.mask = (u64)ACPI_PM_MASK,
101
71
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
72
+
.suspend = acpi_pm_suspend,
73
+
.resume = acpi_pm_resume,
102
74
};
103
75
104
76
+3
-8
drivers/clocksource/arm_arch_timer.c
+3
-8
drivers/clocksource/arm_arch_timer.c
···
1594
1594
{
1595
1595
struct arch_timer_mem *timer_mem;
1596
1596
struct arch_timer_mem_frame *frame;
1597
-
struct device_node *frame_node;
1598
1597
struct resource res;
1599
1598
int ret = -EINVAL;
1600
1599
u32 rate;
···
1607
1608
timer_mem->cntctlbase = res.start;
1608
1609
timer_mem->size = resource_size(&res);
1609
1610
1610
-
for_each_available_child_of_node(np, frame_node) {
1611
+
for_each_available_child_of_node_scoped(np, frame_node) {
1611
1612
u32 n;
1612
1613
struct arch_timer_mem_frame *frame;
1613
1614
1614
1615
if (of_property_read_u32(frame_node, "frame-number", &n)) {
1615
1616
pr_err(FW_BUG "Missing frame-number.\n");
1616
-
of_node_put(frame_node);
1617
1617
goto out;
1618
1618
}
1619
1619
if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1620
1620
pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1621
1621
ARCH_TIMER_MEM_MAX_FRAMES - 1);
1622
-
of_node_put(frame_node);
1623
1622
goto out;
1624
1623
}
1625
1624
frame = &timer_mem->frame[n];
1626
1625
1627
1626
if (frame->valid) {
1628
1627
pr_err(FW_BUG "Duplicated frame-number.\n");
1629
-
of_node_put(frame_node);
1630
1628
goto out;
1631
1629
}
1632
1630
1633
-
if (of_address_to_resource(frame_node, 0, &res)) {
1634
-
of_node_put(frame_node);
1631
+
if (of_address_to_resource(frame_node, 0, &res))
1635
1632
goto out;
1636
-
}
1633
+
1637
1634
frame->cntbase = res.start;
1638
1635
frame->size = resource_size(&res);
1639
1636
+1
drivers/clocksource/asm9260_timer.c
+1
drivers/clocksource/asm9260_timer.c
+1
-6
drivers/clocksource/ingenic-ost.c
+1
-6
drivers/clocksource/ingenic-ost.c
···
93
93
return PTR_ERR(map);
94
94
}
95
95
96
-
ost->clk = devm_clk_get(dev, "ost");
96
+
ost->clk = devm_clk_get_enabled(dev, "ost");
97
97
if (IS_ERR(ost->clk))
98
98
return PTR_ERR(ost->clk);
99
-
100
-
err = clk_prepare_enable(ost->clk);
101
-
if (err)
102
-
return err;
103
99
104
100
/* Clear counter high/low registers */
105
101
if (soc_info->is64bit)
···
125
129
err = clocksource_register_hz(cs, rate);
126
130
if (err) {
127
131
dev_err(dev, "clocksource registration failed");
128
-
clk_disable_unprepare(ost->clk);
129
132
return err;
130
133
}
131
134
+3
-4
drivers/clocksource/jcore-pit.c
+3
-4
drivers/clocksource/jcore-pit.c
···
120
120
121
121
static irqreturn_t jcore_timer_interrupt(int irq, void *dev_id)
122
122
{
123
-
struct jcore_pit *pit = this_cpu_ptr(dev_id);
123
+
struct jcore_pit *pit = dev_id;
124
124
125
125
if (clockevent_state_oneshot(&pit->ced))
126
126
jcore_pit_disable(pit);
···
168
168
return -ENOMEM;
169
169
}
170
170
171
-
err = request_irq(pit_irq, jcore_timer_interrupt,
172
-
IRQF_TIMER | IRQF_PERCPU,
173
-
"jcore_pit", jcore_pit_percpu);
171
+
err = request_percpu_irq(pit_irq, jcore_timer_interrupt,
172
+
"jcore_pit", jcore_pit_percpu);
174
173
if (err) {
175
174
pr_err("pit irq request failed: %d\n", err);
176
175
free_percpu(jcore_pit_percpu);
+4
-2
drivers/clocksource/timer-cadence-ttc.c
+4
-2
drivers/clocksource/timer-cadence-ttc.c
···
435
435
&ttcce->ttc.clk_rate_change_nb);
436
436
if (err) {
437
437
pr_warn("Unable to register clock notifier.\n");
438
-
goto out_kfree;
438
+
goto out_clk_unprepare;
439
439
}
440
440
441
441
ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
···
465
465
err = request_irq(irq, ttc_clock_event_interrupt,
466
466
IRQF_TIMER, ttcce->ce.name, ttcce);
467
467
if (err)
468
-
goto out_kfree;
468
+
goto out_clk_unprepare;
469
469
470
470
clockevents_config_and_register(&ttcce->ce,
471
471
ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
472
472
473
473
return 0;
474
474
475
+
out_clk_unprepare:
476
+
clk_disable_unprepare(ttcce->ttc.clk);
475
477
out_kfree:
476
478
kfree(ttcce);
477
479
return err;
+6
-1
drivers/clocksource/timer-qcom.c
+6
-1
drivers/clocksource/timer-qcom.c
···
233
233
}
234
234
235
235
if (of_property_read_u32(np, "clock-frequency", &freq)) {
236
+
iounmap(cpu0_base);
236
237
pr_err("Unknown frequency\n");
237
238
return -EINVAL;
238
239
}
···
244
243
freq /= 4;
245
244
writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
246
245
247
-
return msm_timer_init(freq, 32, irq, !!percpu_offset);
246
+
ret = msm_timer_init(freq, 32, irq, !!percpu_offset);
247
+
if (ret)
248
+
iounmap(cpu0_base);
249
+
250
+
return ret;
248
251
}
249
252
TIMER_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
250
253
TIMER_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
+2
drivers/platform/x86/intel/pmc/adl.c
+2
drivers/platform/x86/intel/pmc/adl.c
···
295
295
.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
296
296
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
297
297
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
298
+
.acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET,
299
+
.acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE,
298
300
.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
299
301
.lpm_num_modes = ADL_LPM_NUM_MODES,
300
302
.lpm_num_maps = ADL_LPM_NUM_MAPS,
+2
drivers/platform/x86/intel/pmc/cnp.c
+2
drivers/platform/x86/intel/pmc/cnp.c
···
200
200
.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
201
201
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
202
202
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
203
+
.acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET,
204
+
.acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE,
203
205
.ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
204
206
.etr3_offset = ETR3_OFFSET,
205
207
};
+45
drivers/platform/x86/intel/pmc/core.c
+45
drivers/platform/x86/intel/pmc/core.c
···
11
11
12
12
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
13
14
+
#include <linux/acpi_pmtmr.h>
14
15
#include <linux/bitfield.h>
15
16
#include <linux/debugfs.h>
16
17
#include <linux/delay.h>
···
1209
1208
return val == 1;
1210
1209
}
1211
1210
1211
+
/*
1212
+
* Enable or disable ACPI PM Timer
1213
+
*
1214
+
* This function is intended to be a callback for ACPI PM suspend/resume event.
1215
+
* The ACPI PM Timer is enabled on resume only if it was enabled during suspend.
1216
+
*/
1217
+
static void pmc_core_acpi_pm_timer_suspend_resume(void *data, bool suspend)
1218
+
{
1219
+
struct pmc_dev *pmcdev = data;
1220
+
struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
1221
+
const struct pmc_reg_map *map = pmc->map;
1222
+
bool enabled;
1223
+
u32 reg;
1224
+
1225
+
if (!map->acpi_pm_tmr_ctl_offset)
1226
+
return;
1227
+
1228
+
guard(mutex)(&pmcdev->lock);
1229
+
1230
+
if (!suspend && !pmcdev->enable_acpi_pm_timer_on_resume)
1231
+
return;
1232
+
1233
+
reg = pmc_core_reg_read(pmc, map->acpi_pm_tmr_ctl_offset);
1234
+
enabled = !(reg & map->acpi_pm_tmr_disable_bit);
1235
+
if (suspend)
1236
+
reg |= map->acpi_pm_tmr_disable_bit;
1237
+
else
1238
+
reg &= ~map->acpi_pm_tmr_disable_bit;
1239
+
pmc_core_reg_write(pmc, map->acpi_pm_tmr_ctl_offset, reg);
1240
+
1241
+
pmcdev->enable_acpi_pm_timer_on_resume = suspend && enabled;
1242
+
}
1212
1243
1213
1244
static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
1214
1245
{
···
1437
1404
struct pmc_dev *pmcdev;
1438
1405
const struct x86_cpu_id *cpu_id;
1439
1406
int (*core_init)(struct pmc_dev *pmcdev);
1407
+
const struct pmc_reg_map *map;
1440
1408
struct pmc *primary_pmc;
1441
1409
int ret;
1442
1410
···
1496
1462
pm_report_max_hw_sleep(FIELD_MAX(SLP_S0_RES_COUNTER_MASK) *
1497
1463
pmc_core_adjust_slp_s0_step(primary_pmc, 1));
1498
1464
1465
+
map = primary_pmc->map;
1466
+
if (map->acpi_pm_tmr_ctl_offset)
1467
+
acpi_pmtmr_register_suspend_resume_callback(pmc_core_acpi_pm_timer_suspend_resume,
1468
+
pmcdev);
1469
+
1499
1470
device_initialized = true;
1500
1471
dev_info(&pdev->dev, " initialized\n");
1501
1472
···
1510
1471
static void pmc_core_remove(struct platform_device *pdev)
1511
1472
{
1512
1473
struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
1474
+
const struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
1475
+
const struct pmc_reg_map *map = pmc->map;
1476
+
1477
+
if (map->acpi_pm_tmr_ctl_offset)
1478
+
acpi_pmtmr_unregister_suspend_resume_callback();
1479
+
1513
1480
pmc_core_dbgfs_unregister(pmcdev);
1514
1481
pmc_core_clean_structure(pdev);
1515
1482
}
+8
drivers/platform/x86/intel/pmc/core.h
+8
drivers/platform/x86/intel/pmc/core.h
···
68
68
#define SPT_PMC_LTR_SCC 0x3A0
69
69
#define SPT_PMC_LTR_ISH 0x3A4
70
70
71
+
#define SPT_PMC_ACPI_PM_TMR_CTL_OFFSET 0x18FC
72
+
71
73
/* Sunrise Point: PGD PFET Enable Ack Status Registers */
72
74
enum ppfear_regs {
73
75
SPT_PMC_XRAM_PPFEAR0A = 0x590,
···
149
147
150
148
#define SPT_PMC_VRIC1_SLPS0LVEN BIT(13)
151
149
#define SPT_PMC_VRIC1_XTALSDQDIS BIT(22)
150
+
151
+
#define SPT_PMC_BIT_ACPI_PM_TMR_DISABLE BIT(1)
152
152
153
153
/* Cannonlake Power Management Controller register offsets */
154
154
#define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4
···
355
351
const u8 *lpm_reg_index;
356
352
const u32 pson_residency_offset;
357
353
const u32 pson_residency_counter_step;
354
+
const u32 acpi_pm_tmr_ctl_offset;
355
+
const u32 acpi_pm_tmr_disable_bit;
358
356
};
359
357
360
358
/**
···
430
424
u32 die_c6_offset;
431
425
struct telem_endpoint *punit_ep;
432
426
struct pmc_info *regmap_list;
427
+
428
+
bool enable_acpi_pm_timer_on_resume;
433
429
};
434
430
435
431
enum pmc_index {
+2
drivers/platform/x86/intel/pmc/icl.c
+2
drivers/platform/x86/intel/pmc/icl.c
···
46
46
.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
47
47
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
48
48
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
49
+
.acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET,
50
+
.acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE,
49
51
.ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
50
52
.etr3_offset = ETR3_OFFSET,
51
53
};
+2
drivers/platform/x86/intel/pmc/mtl.c
+2
drivers/platform/x86/intel/pmc/mtl.c
···
462
462
.ppfear_buckets = MTL_SOCM_PPFEAR_NUM_ENTRIES,
463
463
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
464
464
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
465
+
.acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET,
466
+
.acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE,
465
467
.lpm_num_maps = ADL_LPM_NUM_MAPS,
466
468
.ltr_ignore_max = MTL_SOCM_NUM_IP_IGN_ALLOWED,
467
469
.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
+2
drivers/platform/x86/intel/pmc/spt.c
+2
drivers/platform/x86/intel/pmc/spt.c
···
130
130
.ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
131
131
.pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
132
132
.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
133
+
.acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET,
134
+
.acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE,
133
135
.ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
134
136
.pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
135
137
};
+2
drivers/platform/x86/intel/pmc/tgl.c
+2
drivers/platform/x86/intel/pmc/tgl.c
···
197
197
.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
198
198
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
199
199
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
200
+
.acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET,
201
+
.acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE,
200
202
.ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
201
203
.lpm_num_maps = TGL_LPM_NUM_MAPS,
202
204
.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
+13
include/linux/acpi_pmtmr.h
+13
include/linux/acpi_pmtmr.h
···
26
26
return acpi_pm_read_verified() & ACPI_PM_MASK;
27
27
}
28
28
29
+
/**
30
+
* Register callback for suspend and resume event
31
+
*
32
+
* @cb Callback triggered on suspend and resume
33
+
* @data Data passed with the callback
34
+
*/
35
+
void acpi_pmtmr_register_suspend_resume_callback(void (*cb)(void *data, bool suspend), void *data);
36
+
37
+
/**
38
+
* Remove registered callback for suspend and resume event
39
+
*/
40
+
void acpi_pmtmr_unregister_suspend_resume_callback(void);
41
+
29
42
#else
30
43
31
44
static inline u32 acpi_pm_read_early(void)