tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-arm-dt-for-v5.19

Renesas RZ/V2M DT Binding Definitions

Clock definitions for the Renesas RZ/V2M (R9A09G011) SoC, shared by
driver and DT source files.

Geert Uytterhoeven d7f49cb4 a1721bbb

+352
+352
include/dt-bindings/clock/r9a09g011-cpg.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + * 3 + * Copyright (C) 2022 Renesas Electronics Corp. 4 + */ 5 + #ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ 6 + #define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ 7 + 8 + #include <dt-bindings/clock/renesas-cpg-mssr.h> 9 + 10 + /* Module Clocks */ 11 + #define R9A09G011_SYS_CLK 0 12 + #define R9A09G011_PFC_PCLK 1 13 + #define R9A09G011_PMC_CORE_CLOCK 2 14 + #define R9A09G011_GIC_CLK 3 15 + #define R9A09G011_RAMA_ACLK 4 16 + #define R9A09G011_ROMA_ACLK 5 17 + #define R9A09G011_SEC_ACLK 6 18 + #define R9A09G011_SEC_PCLK 7 19 + #define R9A09G011_SEC_TCLK 8 20 + #define R9A09G011_DMAA_ACLK 9 21 + #define R9A09G011_TSU0_PCLK 10 22 + #define R9A09G011_TSU1_PCLK 11 23 + 24 + #define R9A09G011_CST_TRACECLK 12 25 + #define R9A09G011_CST_SB_CLK 13 26 + #define R9A09G011_CST_AHB_CLK 14 27 + #define R9A09G011_CST_ATB_SB_CLK 15 28 + #define R9A09G011_CST_TS_SB_CLK 16 29 + 30 + #define R9A09G011_SDI0_ACLK 17 31 + #define R9A09G011_SDI0_IMCLK 18 32 + #define R9A09G011_SDI0_IMCLK2 19 33 + #define R9A09G011_SDI0_CLK_HS 20 34 + #define R9A09G011_SDI1_ACLK 21 35 + #define R9A09G011_SDI1_IMCLK 22 36 + #define R9A09G011_SDI1_IMCLK2 23 37 + #define R9A09G011_SDI1_CLK_HS 24 38 + #define R9A09G011_EMM_ACLK 25 39 + #define R9A09G011_EMM_IMCLK 26 40 + #define R9A09G011_EMM_IMCLK2 27 41 + #define R9A09G011_EMM_CLK_HS 28 42 + #define R9A09G011_NFI_ACLK 29 43 + #define R9A09G011_NFI_NF_CLK 30 44 + 45 + #define R9A09G011_PCI_ACLK 31 46 + #define R9A09G011_PCI_CLK_PMU 32 47 + #define R9A09G011_PCI_APB_CLK 33 48 + #define R9A09G011_USB_ACLK_H 34 49 + #define R9A09G011_USB_ACLK_P 35 50 + #define R9A09G011_USB_PCLK 36 51 + #define R9A09G011_ETH0_CLK_AXI 37 52 + #define R9A09G011_ETH0_CLK_CHI 38 53 + #define R9A09G011_ETH0_GPTP_EXT 39 54 + 55 + #define R9A09G011_SDT_CLK 40 56 + #define R9A09G011_SDT_CLKAPB 41 57 + #define R9A09G011_SDT_CLK48 42 58 + #define R9A09G011_GRP_CLK 43 59 + #define R9A09G011_CIF_P0_CLK 44 60 + #define R9A09G011_CIF_P1_CLK 45 61 + #define R9A09G011_CIF_APB_CLK 46 62 + #define R9A09G011_DCI_CLKAXI 47 63 + #define R9A09G011_DCI_CLKAPB 48 64 + #define R9A09G011_DCI_CLKDCI2 49 65 + 66 + #define R9A09G011_HMI_PCLK 50 67 + #define R9A09G011_LCI_PCLK 51 68 + #define R9A09G011_LCI_ACLK 52 69 + #define R9A09G011_LCI_VCLK 53 70 + #define R9A09G011_LCI_LPCLK 54 71 + 72 + #define R9A09G011_AUI_CLK 55 73 + #define R9A09G011_AUI_CLKAXI 56 74 + #define R9A09G011_AUI_CLKAPB 57 75 + #define R9A09G011_AUMCLK 58 76 + #define R9A09G011_GMCLK0 59 77 + #define R9A09G011_GMCLK1 60 78 + #define R9A09G011_MTR_CLK0 61 79 + #define R9A09G011_MTR_CLK1 62 80 + #define R9A09G011_MTR_CLKAPB 63 81 + #define R9A09G011_GFT_CLK 64 82 + #define R9A09G011_GFT_CLKAPB 65 83 + #define R9A09G011_GFT_MCLK 66 84 + 85 + #define R9A09G011_ATGA_CLK 67 86 + #define R9A09G011_ATGA_CLKAPB 68 87 + #define R9A09G011_ATGB_CLK 69 88 + #define R9A09G011_ATGB_CLKAPB 70 89 + #define R9A09G011_SYC_CNT_CLK 71 90 + 91 + #define R9A09G011_CPERI_GRPA_PCLK 72 92 + #define R9A09G011_TIM0_CLK 73 93 + #define R9A09G011_TIM1_CLK 74 94 + #define R9A09G011_TIM2_CLK 75 95 + #define R9A09G011_TIM3_CLK 76 96 + #define R9A09G011_TIM4_CLK 77 97 + #define R9A09G011_TIM5_CLK 78 98 + #define R9A09G011_TIM6_CLK 79 99 + #define R9A09G011_TIM7_CLK 80 100 + #define R9A09G011_IIC_PCLK0 81 101 + 102 + #define R9A09G011_CPERI_GRPB_PCLK 82 103 + #define R9A09G011_TIM8_CLK 83 104 + #define R9A09G011_TIM9_CLK 84 105 + #define R9A09G011_TIM10_CLK 85 106 + #define R9A09G011_TIM11_CLK 86 107 + #define R9A09G011_TIM12_CLK 87 108 + #define R9A09G011_TIM13_CLK 88 109 + #define R9A09G011_TIM14_CLK 89 110 + #define R9A09G011_TIM15_CLK 90 111 + #define R9A09G011_IIC_PCLK1 91 112 + 113 + #define R9A09G011_CPERI_GRPC_PCLK 92 114 + #define R9A09G011_TIM16_CLK 93 115 + #define R9A09G011_TIM17_CLK 94 116 + #define R9A09G011_TIM18_CLK 95 117 + #define R9A09G011_TIM19_CLK 96 118 + #define R9A09G011_TIM20_CLK 97 119 + #define R9A09G011_TIM21_CLK 98 120 + #define R9A09G011_TIM22_CLK 99 121 + #define R9A09G011_TIM23_CLK 100 122 + #define R9A09G011_WDT0_PCLK 101 123 + #define R9A09G011_WDT0_CLK 102 124 + #define R9A09G011_WDT1_PCLK 103 125 + #define R9A09G011_WDT1_CLK 104 126 + 127 + #define R9A09G011_CPERI_GRPD_PCLK 105 128 + #define R9A09G011_TIM24_CLK 106 129 + #define R9A09G011_TIM25_CLK 107 130 + #define R9A09G011_TIM26_CLK 108 131 + #define R9A09G011_TIM27_CLK 109 132 + #define R9A09G011_TIM28_CLK 110 133 + #define R9A09G011_TIM29_CLK 111 134 + #define R9A09G011_TIM30_CLK 112 135 + #define R9A09G011_TIM31_CLK 113 136 + 137 + #define R9A09G011_CPERI_GRPE_PCLK 114 138 + #define R9A09G011_PWM0_CLK 115 139 + #define R9A09G011_PWM1_CLK 116 140 + #define R9A09G011_PWM2_CLK 117 141 + #define R9A09G011_PWM3_CLK 118 142 + #define R9A09G011_PWM4_CLK 119 143 + #define R9A09G011_PWM5_CLK 120 144 + #define R9A09G011_PWM6_CLK 121 145 + #define R9A09G011_PWM7_CLK 122 146 + 147 + #define R9A09G011_CPERI_GRPF_PCLK 123 148 + #define R9A09G011_PWM8_CLK 124 149 + #define R9A09G011_PWM9_CLK 125 150 + #define R9A09G011_PWM10_CLK 126 151 + #define R9A09G011_PWM11_CLK 127 152 + #define R9A09G011_PWM12_CLK 128 153 + #define R9A09G011_PWM13_CLK 129 154 + #define R9A09G011_PWM14_CLK 130 155 + #define R9A09G011_PWM15_CLK 131 156 + 157 + #define R9A09G011_CPERI_GRPG_PCLK 132 158 + #define R9A09G011_CPERI_GRPH_PCLK 133 159 + #define R9A09G011_URT_PCLK 134 160 + #define R9A09G011_URT0_CLK 135 161 + #define R9A09G011_URT1_CLK 136 162 + #define R9A09G011_CSI0_CLK 137 163 + #define R9A09G011_CSI1_CLK 138 164 + #define R9A09G011_CSI2_CLK 139 165 + #define R9A09G011_CSI3_CLK 140 166 + #define R9A09G011_CSI4_CLK 141 167 + #define R9A09G011_CSI5_CLK 142 168 + 169 + #define R9A09G011_ICB_ACLK1 143 170 + #define R9A09G011_ICB_GIC_CLK 144 171 + #define R9A09G011_ICB_MPCLK1 145 172 + #define R9A09G011_ICB_SPCLK1 146 173 + #define R9A09G011_ICB_CLK48 147 174 + #define R9A09G011_ICB_CLK48_2 148 175 + #define R9A09G011_ICB_CLK48_3 149 176 + #define R9A09G011_ICB_CLK48_4L 150 177 + #define R9A09G011_ICB_CLK48_4R 151 178 + #define R9A09G011_ICB_CLK48_5 152 179 + #define R9A09G011_ICB_CST_ATB_SB_CLK 153 180 + #define R9A09G011_ICB_CST_CS_CLK 154 181 + #define R9A09G011_ICB_CLK100_1 155 182 + #define R9A09G011_ICB_ETH0_CLK_AXI 156 183 + #define R9A09G011_ICB_DCI_CLKAXI 157 184 + #define R9A09G011_ICB_SYC_CNT_CLK 158 185 + 186 + #define R9A09G011_ICB_DRPA_ACLK 159 187 + #define R9A09G011_ICB_RFX_ACLK 160 188 + #define R9A09G011_ICB_RFX_PCLK5 161 189 + #define R9A09G011_ICB_MMC_ACLK 162 190 + 191 + #define R9A09G011_ICB_MPCLK3 163 192 + #define R9A09G011_ICB_CIMA_CLK 164 193 + #define R9A09G011_ICB_CIMB_CLK 165 194 + #define R9A09G011_ICB_BIMA_CLK 166 195 + #define R9A09G011_ICB_FCD_CLKAXI 167 196 + #define R9A09G011_ICB_VD_ACLK4 168 197 + #define R9A09G011_ICB_MPCLK4 169 198 + #define R9A09G011_ICB_VCD_PCLK4 170 199 + 200 + #define R9A09G011_CA53_CLK 171 201 + #define R9A09G011_CA53_ACLK 172 202 + #define R9A09G011_CA53_APCLK_DBG 173 203 + #define R9A09G011_CST_APB_CA53_CLK 174 204 + #define R9A09G011_CA53_ATCLK 175 205 + #define R9A09G011_CST_CS_CLK 176 206 + #define R9A09G011_CA53_TSCLK 177 207 + #define R9A09G011_CST_TS_CLK 178 208 + #define R9A09G011_CA53_APCLK_REG 179 209 + 210 + #define R9A09G011_DRPA_ACLK 180 211 + #define R9A09G011_DRPA_DCLK 181 212 + #define R9A09G011_DRPA_INITCLK 182 213 + 214 + #define R9A09G011_RAMB0_ACLK 183 215 + #define R9A09G011_RAMB1_ACLK 184 216 + #define R9A09G011_RAMB2_ACLK 185 217 + #define R9A09G011_RAMB3_ACLK 186 218 + 219 + #define R9A09G011_CIMA_CLKAPB 187 220 + #define R9A09G011_CIMA_CLK 188 221 + #define R9A09G011_CIMB_CLK 189 222 + #define R9A09G011_FAFA_CLK 190 223 + #define R9A09G011_STG_CLKAXI 191 224 + #define R9A09G011_STG_CLK0 192 225 + 226 + #define R9A09G011_BIMA_CLKAPB 193 227 + #define R9A09G011_BIMA_CLK 194 228 + #define R9A09G011_FAFB_CLK 195 229 + #define R9A09G011_FCD_CLK 196 230 + #define R9A09G011_FCD_CLKAXI 197 231 + 232 + #define R9A09G011_RIM_CLK 198 233 + #define R9A09G011_VCD_ACLK 199 234 + #define R9A09G011_VCD_PCLK 200 235 + #define R9A09G011_JPG0_CLK 201 236 + #define R9A09G011_JPG0_ACLK 202 237 + 238 + #define R9A09G011_MMC_CORE_DDRC_CLK 203 239 + #define R9A09G011_MMC_ACLK 204 240 + #define R9A09G011_MMC_PCLK 205 241 + #define R9A09G011_DDI_APBCLK 206 242 + 243 + /* Resets */ 244 + #define R9A09G011_SYS_RST_N 0 245 + #define R9A09G011_PFC_PRESETN 1 246 + #define R9A09G011_RAMA_ARESETN 2 247 + #define R9A09G011_ROM_ARESETN 3 248 + #define R9A09G011_DMAA_ARESETN 4 249 + #define R9A09G011_SEC_ARESETN 5 250 + #define R9A09G011_SEC_PRESETN 6 251 + #define R9A09G011_SEC_RSTB 7 252 + #define R9A09G011_TSU0_RESETN 8 253 + #define R9A09G011_TSU1_RESETN 9 254 + #define R9A09G011_PMC_RESET_N 10 255 + 256 + #define R9A09G011_CST_NTRST 11 257 + #define R9A09G011_CST_NPOTRST 12 258 + #define R9A09G011_CST_NTRST2 13 259 + #define R9A09G011_CST_CS_RESETN 14 260 + #define R9A09G011_CST_TS_RESETN 15 261 + #define R9A09G011_CST_TRESETN 16 262 + #define R9A09G011_CST_SB_RESETN 17 263 + #define R9A09G011_CST_AHB_RESETN 18 264 + #define R9A09G011_CST_TS_SB_RESETN 19 265 + #define R9A09G011_CST_APB_CA53_RESETN 20 266 + #define R9A09G011_CST_ATB_SB_RESETN 21 267 + 268 + #define R9A09G011_SDI0_IXRST 22 269 + #define R9A09G011_SDI1_IXRST 23 270 + #define R9A09G011_EMM_IXRST 24 271 + #define R9A09G011_NFI_MARESETN 25 272 + #define R9A09G011_NFI_REG_RST_N 26 273 + #define R9A09G011_USB_PRESET_N 27 274 + #define R9A09G011_USB_DRD_RESET 28 275 + #define R9A09G011_USB_ARESETN_P 29 276 + #define R9A09G011_USB_ARESETN_H 30 277 + #define R9A09G011_ETH0_RST_HW_N 31 278 + #define R9A09G011_PCI_ARESETN 32 279 + 280 + #define R9A09G011_SDT_RSTSYSAX 33 281 + #define R9A09G011_GRP_RESETN 34 282 + #define R9A09G011_CIF_RST_N 35 283 + #define R9A09G011_DCU_RSTSYSAX 36 284 + #define R9A09G011_HMI_RST_N 37 285 + #define R9A09G011_HMI_PRESETN 38 286 + #define R9A09G011_LCI_PRESETN 39 287 + #define R9A09G011_LCI_ARESETN 40 288 + 289 + #define R9A09G011_AUI_RSTSYSAX 41 290 + #define R9A09G011_MTR_RSTSYSAX 42 291 + #define R9A09G011_GFT_RSTSYSAX 43 292 + #define R9A09G011_ATGA_RSTSYSAX 44 293 + #define R9A09G011_ATGB_RSTSYSAX 45 294 + #define R9A09G011_SYC_RST_N 46 295 + 296 + #define R9A09G011_TIM_GPA_PRESETN 47 297 + #define R9A09G011_TIM_GPB_PRESETN 48 298 + #define R9A09G011_TIM_GPC_PRESETN 49 299 + #define R9A09G011_TIM_GPD_PRESETN 50 300 + #define R9A09G011_PWM_GPE_PRESETN 51 301 + #define R9A09G011_PWM_GPF_PRESETN 52 302 + #define R9A09G011_CSI_GPG_PRESETN 53 303 + #define R9A09G011_CSI_GPH_PRESETN 54 304 + #define R9A09G011_IIC_GPA_PRESETN 55 305 + #define R9A09G011_IIC_GPB_PRESETN 56 306 + #define R9A09G011_URT_PRESETN 57 307 + #define R9A09G011_WDT0_PRESETN 58 308 + #define R9A09G011_WDT1_PRESETN 59 309 + 310 + #define R9A09G011_ICB_PD_AWO_RST_N 60 311 + #define R9A09G011_ICB_PD_MMC_RST_N 61 312 + #define R9A09G011_ICB_PD_VD0_RST_N 62 313 + #define R9A09G011_ICB_PD_VD1_RST_N 63 314 + #define R9A09G011_ICB_PD_RFX_RST_N 64 315 + 316 + #define R9A09G011_CA53_NCPUPORESET0 65 317 + #define R9A09G011_CA53_NCPUPORESET1 66 318 + #define R9A09G011_CA53_NCORERESET0 67 319 + #define R9A09G011_CA53_NCORERESET1 68 320 + #define R9A09G011_CA53_NPRESETDBG 69 321 + #define R9A09G011_CA53_L2RESET 70 322 + #define R9A09G011_CA53_NMISCRESET_HM 71 323 + #define R9A09G011_CA53_NMISCRESET_SM 72 324 + #define R9A09G011_CA53_NARESET 73 325 + 326 + #define R9A09G011_DRPA_ARESETN 74 327 + 328 + #define R9A09G011_RAMB0_ARESETN 75 329 + #define R9A09G011_RAMB1_ARESETN 76 330 + #define R9A09G011_RAMB2_ARESETN 77 331 + #define R9A09G011_RAMB3_ARESETN 78 332 + 333 + #define R9A09G011_CIMA_RSTSYSAX 79 334 + #define R9A09G011_CIMB_RSTSYSAX 80 335 + #define R9A09G011_FAFA_RSTSYSAX 81 336 + #define R9A09G011_STG_RSTSYSAX 82 337 + 338 + #define R9A09G011_BIMA_RSTSYSAX 83 339 + #define R9A09G011_FAFB_RSTSYSAX 84 340 + #define R9A09G011_FCD_RSTSYSAX 85 341 + #define R9A09G011_RIM_RSTSYSAX 86 342 + #define R9A09G011_VCD_RESETN 87 343 + #define R9A09G011_JPG_XRESET 88 344 + 345 + #define R9A09G011_MMC_CORE_DDRC_RSTN 89 346 + #define R9A09G011_MMC_ARESETN_N 90 347 + #define R9A09G011_MMC_PRESETN 91 348 + #define R9A09G011_DDI_PWROK 92 349 + #define R9A09G011_DDI_RESET 93 350 + #define R9A09G011_DDI_RESETN_APB 94 351 + 352 + #endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */