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Merge branch 'amd-xgbe-add-support-for-p100a-platform'
Raju Rangoju says:
====================
amd-xgbe: add support for P100a platform
This patch series adds support for the AMD P100a platform featuring
the ethernet controller PCI device ID 0x1122.
The P100a platform uses different register access patterns and speed
encoding compared to previous generation hardware (Yellow Carp,etc.)
Key differences include:
1. Different XPCS window offset calculation due to changed memory mapping
2. 2.5G speed uses XGMII mode (ss=0x06) instead of GMII (ss=0x02)
3. Extended port speed bits (6-bit instead of 5-bit) for 5G support
The series is organized as follows:
Patch 1: Defines macros for MAC version numbers and speed select values
to replace hardcoded magic numbers
Patch 2: Adds the core P100a platform support with PCI ID,
register configuration, and version-specific behavior
Tested on AMD P100a platform verifying:
- 10G/2.5G/1G/100M link establishment
- PHY initialization and auto-negotiation
- No register access errors
====================
Link: https://patch.msgid.link/20260302044409.1388430-1-Raju.Rangoju@amd.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+87
-11
+3
-1
drivers/net/ethernet/amd/xgbe/xgbe-common.h
+3
-1
drivers/net/ethernet/amd/xgbe/xgbe-common.h
···
832
832
#define PCS_V2_YC_WINDOW_SELECT 0x18064
833
833
#define PCS_V3_RN_WINDOW_DEF 0xf8078
834
834
#define PCS_V3_RN_WINDOW_SELECT 0xf807c
835
+
#define PCS_P100a_WINDOW_DEF 0x8060
836
+
#define PCS_P100a_WINDOW_SELECT 0x8080
835
837
836
838
#define PCS_RN_SMN_BASE_ADDR 0x11e00000
837
839
#define PCS_RN_PORT_ADDR_SIZE 0x100000
···
970
968
#define XP_PROP_0_PORT_MODE_INDEX 8
971
969
#define XP_PROP_0_PORT_MODE_WIDTH 4
972
970
#define XP_PROP_0_PORT_SPEEDS_INDEX 22
973
-
#define XP_PROP_0_PORT_SPEEDS_WIDTH 5
971
+
#define XP_PROP_0_PORT_SPEEDS_WIDTH 6
974
972
#define XP_PROP_1_MAX_RX_DMA_INDEX 24
975
973
#define XP_PROP_1_MAX_RX_DMA_WIDTH 5
976
974
#define XP_PROP_1_MAX_RX_QUEUES_INDEX 8
+33
-6
drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+33
-6
drivers/net/ethernet/amd/xgbe/xgbe-dev.c
···
718
718
719
719
static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed)
720
720
{
721
-
unsigned int ss;
721
+
unsigned int ss, ver;
722
722
723
723
switch (speed) {
724
724
case SPEED_10:
725
-
ss = 0x07;
725
+
ss = XGBE_MAC_SS_10M;
726
726
break;
727
727
case SPEED_1000:
728
-
ss = 0x03;
728
+
ss = XGBE_MAC_SS_1G;
729
729
break;
730
730
case SPEED_2500:
731
-
ss = 0x02;
731
+
/* P100a uses XGMII mode for 2.5G, older platforms use GMII */
732
+
ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
733
+
if (ver == XGBE_MAC_VER_33)
734
+
ss = XGBE_MAC_SS_2_5G_XGMII;
735
+
else
736
+
ss = XGBE_MAC_SS_2_5G_GMII;
732
737
break;
733
738
case SPEED_10000:
734
-
ss = 0x00;
739
+
ss = XGBE_MAC_SS_10G;
735
740
break;
736
741
default:
737
742
return -EINVAL;
···
1075
1070
unsigned int *index,
1076
1071
unsigned int *offset)
1077
1072
{
1073
+
unsigned int ver;
1074
+
1078
1075
/* The PCS registers are accessed using mmio. The underlying
1079
1076
* management interface uses indirect addressing to access the MMD
1080
1077
* register sets. This requires accessing of the PCS register in two
···
1088
1081
*/
1089
1082
mmd_address <<= 1;
1090
1083
*index = mmd_address & ~pdata->xpcs_window_mask;
1091
-
*offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
1084
+
1085
+
ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
1086
+
1087
+
/* The P100a platform uses a different memory mapping scheme for XPCS
1088
+
* register access. The offset calculation differs between platforms:
1089
+
*
1090
+
* For P100a platforms: The offset is calculated by adding the
1091
+
* mmd_address to the xpcs_window and then applying the xpcs_window_mask
1092
+
* For older platforms: The offset is calculated by applying the
1093
+
* xpcs_window_mask to the mmd_address and then adding it to the
1094
+
* xpcs_window.
1095
+
*
1096
+
* This is critical because using the wrong calculation causes register
1097
+
* accesses to target the wrong registers, leading to incorrect behavior
1098
+
*/
1099
+
if (ver == XGBE_MAC_VER_33)
1100
+
*offset = (pdata->xpcs_window + mmd_address) &
1101
+
pdata->xpcs_window_mask;
1102
+
else
1103
+
*offset = pdata->xpcs_window +
1104
+
(mmd_address & pdata->xpcs_window_mask);
1092
1105
}
1093
1106
1094
1107
static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
+8
drivers/net/ethernet/amd/xgbe/xgbe-pci.c
+8
drivers/net/ethernet/amd/xgbe/xgbe-pci.c
···
168
168
rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
169
169
if (rdev && rdev->vendor == PCI_VENDOR_ID_AMD) {
170
170
switch (rdev->device) {
171
+
case XGBE_P100a_PCI_DEVICE_ID:
172
+
pdata->xpcs_window_def_reg = PCS_P100a_WINDOW_DEF;
173
+
pdata->xpcs_window_sel_reg = PCS_P100a_WINDOW_SELECT;
174
+
175
+
/* P100a devices do not need rrc and cdr workaround */
176
+
pdata->vdata->an_cdr_workaround = 0;
177
+
pdata->vdata->enable_rrc = 0;
178
+
break;
171
179
case XGBE_RV_PCI_DEVICE_ID:
172
180
pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
173
181
pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
+19
-3
drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
+19
-3
drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
···
2132
2132
2133
2133
/* Rx-Adaptation is not supported on older platforms(< 0x30H) */
2134
2134
ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2135
-
if (ver < 0x30)
2135
+
if (ver < XGBE_MAC_VER_30)
2136
+
return false;
2137
+
2138
+
/* Rx adaptation not yet supported on P100a */
2139
+
if (ver == XGBE_MAC_VER_33)
2136
2140
return false;
2137
2141
2138
2142
/* Re-driver models 4223 && 4227 do not support Rx-Adaptation */
···
2262
2258
2263
2259
static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2264
2260
{
2261
+
unsigned int ver;
2262
+
2265
2263
struct xgbe_phy_data *phy_data = pdata->phy_data;
2266
2264
2267
2265
xgbe_phy_set_redrv_mode(pdata);
2268
2266
2269
-
/* 2.5G/KX */
2270
-
xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G, XGBE_MB_SUBCMD_NONE);
2267
+
ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2268
+
2269
+
/*
2270
+
* P100a uses XGMII mode for 2.5G which requires the 2.5G_KX subcommand.
2271
+
* Older platforms use GMII mode.
2272
+
*/
2273
+
if (ver == XGBE_MAC_VER_33)
2274
+
xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G,
2275
+
XGBE_MB_SUBCMD_2_5G_KX);
2276
+
else
2277
+
xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G,
2278
+
XGBE_MB_SUBCMD_NONE);
2271
2279
2272
2280
phy_data->cur_mode = XGBE_MODE_KX_2500;
2273
2281
+24
-1
drivers/net/ethernet/amd/xgbe/xgbe.h
+24
-1
drivers/net/ethernet/amd/xgbe/xgbe.h
···
262
262
#define XGBE_RV_PCI_DEVICE_ID 0x15d0
263
263
#define XGBE_YC_PCI_DEVICE_ID 0x14b5
264
264
#define XGBE_RN_PCI_DEVICE_ID 0x1630
265
+
#define XGBE_P100a_PCI_DEVICE_ID 0x1122
265
266
266
267
/* Generic low and high masks */
267
268
#define XGBE_GEN_HI_MASK GENMASK(31, 16)
268
269
#define XGBE_GEN_LO_MASK GENMASK(15, 0)
270
+
271
+
/* MAC hardware version numbers (SNPSVER field in MAC_VR register) */
272
+
#define XGBE_MAC_VER_30 0x30 /* Baseline Rx adaptation support */
273
+
#define XGBE_MAC_VER_33 0x33 /* P100a platform */
274
+
275
+
/* MAC Speed Select (SS) values for MAC_TCR register
276
+
* These values are written to the SS field to configure link speed.
277
+
* Note: P100a uses XGMII mode (0x06) for 2.5G instead of GMII (0x02)
278
+
*/
279
+
/* Note: 100M and 2.5G GMII share the same value (0x02) but are
280
+
* differentiated by the mode/interface type at the PHY level
281
+
*/
282
+
283
+
#define XGBE_MAC_SS_10G 0x00 /* 10Gbps - XGMII mode */
284
+
#define XGBE_MAC_SS_2_5G_GMII 0x02 /* 2.5Gbps - GMII mode (YC) */
285
+
#define XGBE_MAC_SS_2_5G_XGMII 0x06 /* 2.5Gbps - XGMII mode (P100a) */
286
+
#define XGBE_MAC_SS_1G 0x03 /* 1Gbps */
287
+
#define XGBE_MAC_SS_100M 0x02 /* 100Mbps */
288
+
#define XGBE_MAC_SS_10M 0x07 /* 10Mbps */
269
289
270
290
struct xgbe_prv_data;
271
291
···
578
558
XGBE_MB_SUBCMD_10MBITS = 0,
579
559
XGBE_MB_SUBCMD_100MBITS,
580
560
XGBE_MB_SUBCMD_1G_SGMII,
581
-
XGBE_MB_SUBCMD_1G_KX
561
+
XGBE_MB_SUBCMD_1G_KX,
562
+
563
+
/* 2.5GbE Mode subcommands */
564
+
XGBE_MB_SUBCMD_2_5G_KX = 1
582
565
};
583
566
584
567
struct xgbe_phy {