tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Olof Johansson:
"A collection of fixes from the last few weeks. Most of them are
smaller tweaks and fixes to DT and hardware descriptions for boards.
Some of the more significant ones are:

- eMMC and RGMII stability tweaks for rk3288

- DDC fixes for Rock PI 4

- Audio fixes for two TI am335x eval boards

- D_CAN clock fix for am335x

- Compilation fixes for clang

- !HOTPLUG_CPU compilation fix for one of the new platforms this
release (milbeaut)

- A revert of a gpio fix for nomadik that instead was fixed in the
gpio subsystem

- Whitespace fix for the DT JSON schema (no tabs allowed)"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
ARM: milbeaut: fix build with !CONFIG_HOTPLUG_CPU
ARM: iop: don't use using 64-bit DMA masks
ARM: orion: don't use using 64-bit DMA masks
Revert "ARM: dts: nomadik: Fix polarity of SPI CS"
dt-bindings: cpu: Fix JSON schema
arm/mach-at91/pm : fix possible object reference leak
ARM: dts: at91: Fix typo in ISC_D0 on PC9
ARM: dts: Fix dcan clkctrl clock for am3
reset: meson-audio-arb: Fix missing .owner setting of reset_controller_dev
dt-bindings: reset: meson-g12a: Add missing USB2 PHY resets
ARM: dts: rockchip: Remove #address/#size-cells from rk3288-veyron gpio-keys
ARM: dts: rockchip: Remove #address/#size-cells from rk3288 mipi_dsi
ARM: dts: rockchip: Fix gpu opp node names for rk3288
ARM: dts: am335x-evmsk: Correct the regulators for the audio codec
ARM: dts: am335x-evm: Correct the regulators for the audio codec
ARM: OMAP2+: add missing of_node_put after of_device_is_available
ARM: OMAP1: ams-delta: Fix broken GPIO ID allocation
arm64: dts: stratix10: add the sysmgr-syscon property from the gmac's
arm64: dts: rockchip: fix rk3328 sdmmc0 write errors
arm64: dts: rockchip: fix rk3328 rgmii high tx error rate
...

Linus Torvalds d8491223 429fba10

+131 -82
+1 -1
Documentation/devicetree/bindings/arm/cpus.yaml
··· 228 228 - renesas,r9a06g032-smp 229 229 - rockchip,rk3036-smp 230 230 - rockchip,rk3066-smp 231 - - socionext,milbeaut-m10v-smp 231 + - socionext,milbeaut-m10v-smp 232 232 - ste,dbx500-smp 233 233 234 234 cpu-release-addr:
+22 -4
arch/arm/boot/dts/am335x-evm.dts
··· 57 57 enable-active-high; 58 58 }; 59 59 60 + /* TPS79501 */ 61 + v1_8d_reg: fixedregulator-v1_8d { 62 + compatible = "regulator-fixed"; 63 + regulator-name = "v1_8d"; 64 + vin-supply = <&vbat>; 65 + regulator-min-microvolt = <1800000>; 66 + regulator-max-microvolt = <1800000>; 67 + }; 68 + 69 + /* TPS79501 */ 70 + v3_3d_reg: fixedregulator-v3_3d { 71 + compatible = "regulator-fixed"; 72 + regulator-name = "v3_3d"; 73 + vin-supply = <&vbat>; 74 + regulator-min-microvolt = <3300000>; 75 + regulator-max-microvolt = <3300000>; 76 + }; 77 + 60 78 matrix_keypad: matrix_keypad0 { 61 79 compatible = "gpio-matrix-keypad"; 62 80 debounce-delay-ms = <5>; ··· 517 499 status = "okay"; 518 500 519 501 /* Regulators */ 520 - AVDD-supply = <&vaux2_reg>; 521 - IOVDD-supply = <&vaux2_reg>; 522 - DRVDD-supply = <&vaux2_reg>; 523 - DVDD-supply = <&vbat>; 502 + AVDD-supply = <&v3_3d_reg>; 503 + IOVDD-supply = <&v3_3d_reg>; 504 + DRVDD-supply = <&v3_3d_reg>; 505 + DVDD-supply = <&v1_8d_reg>; 524 506 }; 525 507 }; 526 508
+22 -4
arch/arm/boot/dts/am335x-evmsk.dts
··· 73 73 enable-active-high; 74 74 }; 75 75 76 + /* TPS79518 */ 77 + v1_8d_reg: fixedregulator-v1_8d { 78 + compatible = "regulator-fixed"; 79 + regulator-name = "v1_8d"; 80 + vin-supply = <&vbat>; 81 + regulator-min-microvolt = <1800000>; 82 + regulator-max-microvolt = <1800000>; 83 + }; 84 + 85 + /* TPS78633 */ 86 + v3_3d_reg: fixedregulator-v3_3d { 87 + compatible = "regulator-fixed"; 88 + regulator-name = "v3_3d"; 89 + vin-supply = <&vbat>; 90 + regulator-min-microvolt = <3300000>; 91 + regulator-max-microvolt = <3300000>; 92 + }; 93 + 76 94 leds { 77 95 pinctrl-names = "default"; 78 96 pinctrl-0 = <&user_leds_s0>; ··· 519 501 status = "okay"; 520 502 521 503 /* Regulators */ 522 - AVDD-supply = <&vaux2_reg>; 523 - IOVDD-supply = <&vaux2_reg>; 524 - DRVDD-supply = <&vaux2_reg>; 525 - DVDD-supply = <&vbat>; 504 + AVDD-supply = <&v3_3d_reg>; 505 + IOVDD-supply = <&v3_3d_reg>; 506 + DRVDD-supply = <&v3_3d_reg>; 507 + DVDD-supply = <&v1_8d_reg>; 526 508 }; 527 509 }; 528 510
+2 -2
arch/arm/boot/dts/am33xx-l4.dtsi
··· 1762 1762 reg = <0xcc000 0x4>; 1763 1763 reg-names = "rev"; 1764 1764 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1765 - clocks = <&l4ls_clkctrl AM3_D_CAN0_CLKCTRL 0>; 1765 + clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>; 1766 1766 clock-names = "fck"; 1767 1767 #address-cells = <1>; 1768 1768 #size-cells = <1>; ··· 1785 1785 reg = <0xd0000 0x4>; 1786 1786 reg-names = "rev"; 1787 1787 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1788 - clocks = <&l4ls_clkctrl AM3_D_CAN1_CLKCTRL 0>; 1788 + clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>; 1789 1789 clock-names = "fck"; 1790 1790 #address-cells = <1>; 1791 1791 #size-cells = <1>;
+2 -1
arch/arm/boot/dts/rk3288-tinker.dtsi
··· 254 254 }; 255 255 256 256 vccio_sd: LDO_REG5 { 257 + regulator-boot-on; 257 258 regulator-min-microvolt = <1800000>; 258 259 regulator-max-microvolt = <3300000>; 259 260 regulator-name = "vccio_sd"; ··· 431 430 bus-width = <4>; 432 431 cap-mmc-highspeed; 433 432 cap-sd-highspeed; 434 - card-detect-delay = <200>; 433 + broken-cd; 435 434 disable-wp; /* wp not hooked up */ 436 435 pinctrl-names = "default"; 437 436 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
-2
arch/arm/boot/dts/rk3288-veyron.dtsi
··· 25 25 26 26 gpio_keys: gpio-keys { 27 27 compatible = "gpio-keys"; 28 - #address-cells = <1>; 29 - #size-cells = <0>; 30 28 31 29 pinctrl-names = "default"; 32 30 pinctrl-0 = <&pwr_key_l>;
+9 -11
arch/arm/boot/dts/rk3288.dtsi
··· 70 70 compatible = "arm,cortex-a12"; 71 71 reg = <0x501>; 72 72 resets = <&cru SRST_CORE1>; 73 - operating-points = <&cpu_opp_table>; 73 + operating-points-v2 = <&cpu_opp_table>; 74 74 #cooling-cells = <2>; /* min followed by max */ 75 75 clock-latency = <40000>; 76 76 clocks = <&cru ARMCLK>; ··· 80 80 compatible = "arm,cortex-a12"; 81 81 reg = <0x502>; 82 82 resets = <&cru SRST_CORE2>; 83 - operating-points = <&cpu_opp_table>; 83 + operating-points-v2 = <&cpu_opp_table>; 84 84 #cooling-cells = <2>; /* min followed by max */ 85 85 clock-latency = <40000>; 86 86 clocks = <&cru ARMCLK>; ··· 90 90 compatible = "arm,cortex-a12"; 91 91 reg = <0x503>; 92 92 resets = <&cru SRST_CORE3>; 93 - operating-points = <&cpu_opp_table>; 93 + operating-points-v2 = <&cpu_opp_table>; 94 94 #cooling-cells = <2>; /* min followed by max */ 95 95 clock-latency = <40000>; 96 96 clocks = <&cru ARMCLK>; ··· 1119 1119 clock-names = "ref", "pclk"; 1120 1120 power-domains = <&power RK3288_PD_VIO>; 1121 1121 rockchip,grf = <&grf>; 1122 - #address-cells = <1>; 1123 - #size-cells = <0>; 1124 1122 status = "disabled"; 1125 1123 1126 1124 ports { ··· 1280 1282 gpu_opp_table: gpu-opp-table { 1281 1283 compatible = "operating-points-v2"; 1282 1284 1283 - opp@100000000 { 1285 + opp-100000000 { 1284 1286 opp-hz = /bits/ 64 <100000000>; 1285 1287 opp-microvolt = <950000>; 1286 1288 }; 1287 - opp@200000000 { 1289 + opp-200000000 { 1288 1290 opp-hz = /bits/ 64 <200000000>; 1289 1291 opp-microvolt = <950000>; 1290 1292 }; 1291 - opp@300000000 { 1293 + opp-300000000 { 1292 1294 opp-hz = /bits/ 64 <300000000>; 1293 1295 opp-microvolt = <1000000>; 1294 1296 }; 1295 - opp@400000000 { 1297 + opp-400000000 { 1296 1298 opp-hz = /bits/ 64 <400000000>; 1297 1299 opp-microvolt = <1100000>; 1298 1300 }; 1299 - opp@500000000 { 1301 + opp-500000000 { 1300 1302 opp-hz = /bits/ 64 <500000000>; 1301 1303 opp-microvolt = <1200000>; 1302 1304 }; 1303 - opp@600000000 { 1305 + opp-600000000 { 1304 1306 opp-hz = /bits/ 64 <600000000>; 1305 1307 opp-microvolt = <1250000>; 1306 1308 };
+1 -1
arch/arm/boot/dts/sama5d2-pinfunc.h
··· 518 518 #define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) 519 519 #define PIN_PC9__FIQ PINMUX_PIN(PIN_PC9, 1, 3) 520 520 #define PIN_PC9__GTSUCOMP PINMUX_PIN(PIN_PC9, 2, 1) 521 - #define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 2, 1) 521 + #define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 3, 1) 522 522 #define PIN_PC9__TIOA4 PINMUX_PIN(PIN_PC9, 4, 2) 523 523 #define PIN_PC10 74 524 524 #define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0)
+4 -5
arch/arm/boot/dts/ste-nomadik-nhk15.dts
··· 213 213 gpio-sck = <&gpio0 5 GPIO_ACTIVE_HIGH>; 214 214 gpio-mosi = <&gpio0 4 GPIO_ACTIVE_HIGH>; 215 215 /* 216 - * This chipselect is active high. Just setting the flags 217 - * to GPIO_ACTIVE_HIGH is not enough for the SPI DT bindings, 218 - * it will be ignored, only the special "spi-cs-high" flag 219 - * really counts. 216 + * It's not actually active high, but the frameworks assume 217 + * the polarity of the passed-in GPIO is "normal" (active 218 + * high) then actively drives the line low to select the 219 + * chip. 220 220 */ 221 221 cs-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; 222 - spi-cs-high; 223 222 num-chipselects = <1>; 224 223 225 224 /*
+4 -2
arch/arm/mach-at91/pm.c
··· 591 591 592 592 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); 593 593 if (!np) 594 - goto securam_fail; 594 + goto securam_fail_no_ref_dev; 595 595 596 596 pdev = of_find_device_by_node(np); 597 597 of_node_put(np); 598 598 if (!pdev) { 599 599 pr_warn("%s: failed to find securam device!\n", __func__); 600 - goto securam_fail; 600 + goto securam_fail_no_ref_dev; 601 601 } 602 602 603 603 sram_pool = gen_pool_get(&pdev->dev, NULL); ··· 620 620 return 0; 621 621 622 622 securam_fail: 623 + put_device(&pdev->dev); 624 + securam_fail_no_ref_dev: 623 625 iounmap(pm_data.sfrbu); 624 626 pm_data.sfrbu = NULL; 625 627 return ret;
+4 -4
arch/arm/mach-iop13xx/setup.c
··· 300 300 } 301 301 }; 302 302 303 - static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(64); 303 + static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(32); 304 304 static struct iop_adma_platform_data iop13xx_adma_0_data = { 305 305 .hw_id = 0, 306 306 .pool_size = PAGE_SIZE, ··· 324 324 .resource = iop13xx_adma_0_resources, 325 325 .dev = { 326 326 .dma_mask = &iop13xx_adma_dmamask, 327 - .coherent_dma_mask = DMA_BIT_MASK(64), 327 + .coherent_dma_mask = DMA_BIT_MASK(32), 328 328 .platform_data = (void *) &iop13xx_adma_0_data, 329 329 }, 330 330 }; ··· 336 336 .resource = iop13xx_adma_1_resources, 337 337 .dev = { 338 338 .dma_mask = &iop13xx_adma_dmamask, 339 - .coherent_dma_mask = DMA_BIT_MASK(64), 339 + .coherent_dma_mask = DMA_BIT_MASK(32), 340 340 .platform_data = (void *) &iop13xx_adma_1_data, 341 341 }, 342 342 }; ··· 348 348 .resource = iop13xx_adma_2_resources, 349 349 .dev = { 350 350 .dma_mask = &iop13xx_adma_dmamask, 351 - .coherent_dma_mask = DMA_BIT_MASK(64), 351 + .coherent_dma_mask = DMA_BIT_MASK(32), 352 352 .platform_data = (void *) &iop13xx_adma_2_data, 353 353 }, 354 354 };
+5 -5
arch/arm/mach-iop13xx/tpmi.c
··· 152 152 } 153 153 }; 154 154 155 - u64 iop13xx_tpmi_mask = DMA_BIT_MASK(64); 155 + u64 iop13xx_tpmi_mask = DMA_BIT_MASK(32); 156 156 static struct platform_device iop13xx_tpmi_0_device = { 157 157 .name = "iop-tpmi", 158 158 .id = 0, ··· 160 160 .resource = iop13xx_tpmi_0_resources, 161 161 .dev = { 162 162 .dma_mask = &iop13xx_tpmi_mask, 163 - .coherent_dma_mask = DMA_BIT_MASK(64), 163 + .coherent_dma_mask = DMA_BIT_MASK(32), 164 164 }, 165 165 }; 166 166 ··· 171 171 .resource = iop13xx_tpmi_1_resources, 172 172 .dev = { 173 173 .dma_mask = &iop13xx_tpmi_mask, 174 - .coherent_dma_mask = DMA_BIT_MASK(64), 174 + .coherent_dma_mask = DMA_BIT_MASK(32), 175 175 }, 176 176 }; 177 177 ··· 182 182 .resource = iop13xx_tpmi_2_resources, 183 183 .dev = { 184 184 .dma_mask = &iop13xx_tpmi_mask, 185 - .coherent_dma_mask = DMA_BIT_MASK(64), 185 + .coherent_dma_mask = DMA_BIT_MASK(32), 186 186 }, 187 187 }; 188 188 ··· 193 193 .resource = iop13xx_tpmi_3_resources, 194 194 .dev = { 195 195 .dma_mask = &iop13xx_tpmi_mask, 196 - .coherent_dma_mask = DMA_BIT_MASK(64), 196 + .coherent_dma_mask = DMA_BIT_MASK(32), 197 197 }, 198 198 }; 199 199
+4
arch/arm/mach-milbeaut/platsmp.c
··· 65 65 writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4); 66 66 } 67 67 68 + #ifdef CONFIG_HOTPLUG_CPU 68 69 static void m10v_cpu_die(unsigned int l_cpu) 69 70 { 70 71 gic_cpu_if_down(0); ··· 84 83 85 84 return 1; 86 85 } 86 + #endif 87 87 88 88 static struct smp_operations m10v_smp_ops __initdata = { 89 89 .smp_prepare_cpus = m10v_smp_init, 90 90 .smp_boot_secondary = m10v_boot_secondary, 91 + #ifdef CONFIG_HOTPLUG_CPU 91 92 .cpu_die = m10v_cpu_die, 92 93 .cpu_kill = m10v_cpu_kill, 94 + #endif 93 95 }; 94 96 CPU_METHOD_OF_DECLARE(m10v_smp, "socionext,milbeaut-m10v-smp", &m10v_smp_ops); 95 97
+2
arch/arm/mach-omap1/board-ams-delta.c
··· 182 182 183 183 static struct bgpio_pdata latch1_pdata = { 184 184 .label = LATCH1_LABEL, 185 + .base = -1, 185 186 .ngpio = LATCH1_NGPIO, 186 187 }; 187 188 ··· 220 219 221 220 static struct bgpio_pdata latch2_pdata = { 222 221 .label = LATCH2_LABEL, 222 + .base = -1, 223 223 .ngpio = LATCH2_NGPIO, 224 224 }; 225 225
+3 -1
arch/arm/mach-omap2/display.c
··· 250 250 if (!node) 251 251 return 0; 252 252 253 - if (!of_device_is_available(node)) 253 + if (!of_device_is_available(node)) { 254 + of_node_put(node); 254 255 return 0; 256 + } 255 257 256 258 pdev = of_find_device_by_node(node); 257 259
+3 -3
arch/arm/plat-iop/adma.c
··· 143 143 .resource = iop3xx_dma_0_resources, 144 144 .dev = { 145 145 .dma_mask = &iop3xx_adma_dmamask, 146 - .coherent_dma_mask = DMA_BIT_MASK(64), 146 + .coherent_dma_mask = DMA_BIT_MASK(32), 147 147 .platform_data = (void *) &iop3xx_dma_0_data, 148 148 }, 149 149 }; ··· 155 155 .resource = iop3xx_dma_1_resources, 156 156 .dev = { 157 157 .dma_mask = &iop3xx_adma_dmamask, 158 - .coherent_dma_mask = DMA_BIT_MASK(64), 158 + .coherent_dma_mask = DMA_BIT_MASK(32), 159 159 .platform_data = (void *) &iop3xx_dma_1_data, 160 160 }, 161 161 }; ··· 167 167 .resource = iop3xx_aau_resources, 168 168 .dev = { 169 169 .dma_mask = &iop3xx_adma_dmamask, 170 - .coherent_dma_mask = DMA_BIT_MASK(64), 170 + .coherent_dma_mask = DMA_BIT_MASK(32), 171 171 .platform_data = (void *) &iop3xx_aau_data, 172 172 }, 173 173 };
+2 -2
arch/arm/plat-orion/common.c
··· 622 622 .resource = orion_xor0_shared_resources, 623 623 .dev = { 624 624 .dma_mask = &orion_xor_dmamask, 625 - .coherent_dma_mask = DMA_BIT_MASK(64), 625 + .coherent_dma_mask = DMA_BIT_MASK(32), 626 626 .platform_data = &orion_xor0_pdata, 627 627 }, 628 628 }; ··· 683 683 .resource = orion_xor1_shared_resources, 684 684 .dev = { 685 685 .dma_mask = &orion_xor_dmamask, 686 - .coherent_dma_mask = DMA_BIT_MASK(64), 686 + .coherent_dma_mask = DMA_BIT_MASK(32), 687 687 .platform_data = &orion_xor1_pdata, 688 688 }, 689 689 };
+3
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
··· 162 162 rx-fifo-depth = <16384>; 163 163 snps,multicast-filter-bins = <256>; 164 164 iommus = <&smmu 1>; 165 + altr,sysmgr-syscon = <&sysmgr 0x44 0>; 165 166 status = "disabled"; 166 167 }; 167 168 ··· 180 179 rx-fifo-depth = <16384>; 181 180 snps,multicast-filter-bins = <256>; 182 181 iommus = <&smmu 2>; 182 + altr,sysmgr-syscon = <&sysmgr 0x48 0>; 183 183 status = "disabled"; 184 184 }; 185 185 ··· 198 196 rx-fifo-depth = <16384>; 199 197 snps,multicast-filter-bins = <256>; 200 198 iommus = <&smmu 3>; 199 + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 201 200 status = "disabled"; 202 201 }; 203 202
+2 -2
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
··· 108 108 snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; 109 109 snps,reset-active-low; 110 110 snps,reset-delays-us = <0 10000 50000>; 111 - tx_delay = <0x25>; 112 - rx_delay = <0x11>; 111 + tx_delay = <0x24>; 112 + rx_delay = <0x18>; 113 113 status = "okay"; 114 114 }; 115 115
+1 -2
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
··· 46 46 47 47 vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { 48 48 compatible = "regulator-fixed"; 49 - enable-active-high; 50 - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; 49 + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; 51 50 pinctrl-names = "default"; 52 51 pinctrl-0 = <&usb20_host_drv>; 53 52 regulator-name = "vcc_host1_5v";
+29 -29
arch/arm64/boot/dts/rockchip/rk3328.dtsi
··· 1445 1445 1446 1446 sdmmc0 { 1447 1447 sdmmc0_clk: sdmmc0-clk { 1448 - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>; 1448 + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1449 1449 }; 1450 1450 1451 1451 sdmmc0_cmd: sdmmc0-cmd { 1452 - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>; 1452 + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1453 1453 }; 1454 1454 1455 1455 sdmmc0_dectn: sdmmc0-dectn { ··· 1461 1461 }; 1462 1462 1463 1463 sdmmc0_bus1: sdmmc0-bus1 { 1464 - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>; 1464 + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1465 1465 }; 1466 1466 1467 1467 sdmmc0_bus4: sdmmc0-bus4 { 1468 - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>, 1469 - <1 RK_PA1 1 &pcfg_pull_up_4ma>, 1470 - <1 RK_PA2 1 &pcfg_pull_up_4ma>, 1471 - <1 RK_PA3 1 &pcfg_pull_up_4ma>; 1468 + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1469 + <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1470 + <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1471 + <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1472 1472 }; 1473 1473 1474 1474 sdmmc0_gpio: sdmmc0-gpio { ··· 1642 1642 rgmiim1_pins: rgmiim1-pins { 1643 1643 rockchip,pins = 1644 1644 /* mac_txclk */ 1645 - <1 RK_PB4 2 &pcfg_pull_none_12ma>, 1645 + <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1646 1646 /* mac_rxclk */ 1647 - <1 RK_PB5 2 &pcfg_pull_none_2ma>, 1647 + <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1648 1648 /* mac_mdio */ 1649 - <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1649 + <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1650 1650 /* mac_txen */ 1651 - <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1651 + <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1652 1652 /* mac_clk */ 1653 - <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1653 + <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1654 1654 /* mac_rxdv */ 1655 - <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1655 + <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1656 1656 /* mac_mdc */ 1657 - <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1657 + <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1658 1658 /* mac_rxd1 */ 1659 - <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1659 + <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1660 1660 /* mac_rxd0 */ 1661 - <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1661 + <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1662 1662 /* mac_txd1 */ 1663 - <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1663 + <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1664 1664 /* mac_txd0 */ 1665 - <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1665 + <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1666 1666 /* mac_rxd3 */ 1667 - <1 RK_PB6 2 &pcfg_pull_none_2ma>, 1667 + <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1668 1668 /* mac_rxd2 */ 1669 - <1 RK_PB7 2 &pcfg_pull_none_2ma>, 1669 + <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1670 1670 /* mac_txd3 */ 1671 - <1 RK_PC0 2 &pcfg_pull_none_12ma>, 1671 + <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1672 1672 /* mac_txd2 */ 1673 - <1 RK_PC1 2 &pcfg_pull_none_12ma>, 1673 + <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1674 1674 1675 1675 /* mac_txclk */ 1676 - <0 RK_PB0 1 &pcfg_pull_none>, 1676 + <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1677 1677 /* mac_txen */ 1678 - <0 RK_PB4 1 &pcfg_pull_none>, 1678 + <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1679 1679 /* mac_clk */ 1680 - <0 RK_PD0 1 &pcfg_pull_none>, 1680 + <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1681 1681 /* mac_txd1 */ 1682 - <0 RK_PC0 1 &pcfg_pull_none>, 1682 + <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1683 1683 /* mac_txd0 */ 1684 - <0 RK_PC1 1 &pcfg_pull_none>, 1684 + <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1685 1685 /* mac_txd3 */ 1686 - <0 RK_PC7 1 &pcfg_pull_none>, 1686 + <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1687 1687 /* mac_txd2 */ 1688 - <0 RK_PC6 1 &pcfg_pull_none>; 1688 + <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1689 1689 }; 1690 1690 1691 1691 rmiim1_pins: rmiim1-pins {
+1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
··· 158 158 }; 159 159 160 160 &hdmi { 161 + ddc-i2c-bus = <&i2c3>; 161 162 pinctrl-names = "default"; 162 163 pinctrl-0 = <&hdmi_cec>; 163 164 status = "okay";
+1
drivers/reset/reset-meson-audio-arb.c
··· 130 130 arb->rstc.nr_resets = ARRAY_SIZE(axg_audio_arb_reset_bits); 131 131 arb->rstc.ops = &meson_audio_arb_rstc_ops; 132 132 arb->rstc.of_node = dev->of_node; 133 + arb->rstc.owner = THIS_MODULE; 133 134 134 135 /* 135 136 * Enable general :
+4 -1
include/dt-bindings/reset/amlogic,meson-g12a-reset.h
··· 51 51 #define RESET_SD_EMMC_A 44 52 52 #define RESET_SD_EMMC_B 45 53 53 #define RESET_SD_EMMC_C 46 54 - /* 47-60 */ 54 + /* 47 */ 55 + #define RESET_USB_PHY20 48 56 + #define RESET_USB_PHY21 49 57 + /* 50-60 */ 55 58 #define RESET_AUDIO_CODEC 61 56 59 /* 62-63 */ 57 60 /* RESET2 */