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clk: ingenic: Make PLL clock enable_bit and stable_bit optional

When the enable bit is undefined, the clock is assumed to be always
on and enable/disable is a no-op. When the stable bit is undefined,
the PLL stable check is a no-op.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-3-aidanmacdonald.0x0@gmail.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Aidan MacDonald and committed by
Stephen Boyd d84bf9d6 83b975b5

+19 -5
+13 -1
drivers/clk/ingenic/cgu.c
··· 189 189 { 190 190 u32 ctl; 191 191 192 + if (pll_info->stable_bit < 0) 193 + return 0; 194 + 192 195 return readl_poll_timeout(cgu->base + pll_info->reg, ctl, 193 196 ctl & BIT(pll_info->stable_bit), 194 197 0, 100 * USEC_PER_MSEC); ··· 233 230 writel(ctl, cgu->base + pll_info->reg); 234 231 235 232 /* If the PLL is enabled, verify that it's stable */ 236 - if (ctl & BIT(pll_info->enable_bit)) 233 + if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) 237 234 ret = ingenic_pll_check_stable(cgu, pll_info); 238 235 239 236 spin_unlock_irqrestore(&cgu->lock, flags); ··· 250 247 unsigned long flags; 251 248 int ret; 252 249 u32 ctl; 250 + 251 + if (pll_info->enable_bit < 0) 252 + return 0; 253 253 254 254 spin_lock_irqsave(&cgu->lock, flags); 255 255 if (pll_info->bypass_bit >= 0) { ··· 284 278 unsigned long flags; 285 279 u32 ctl; 286 280 281 + if (pll_info->enable_bit < 0) 282 + return; 283 + 287 284 spin_lock_irqsave(&cgu->lock, flags); 288 285 ctl = readl(cgu->base + pll_info->reg); 289 286 ··· 303 294 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); 304 295 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; 305 296 u32 ctl; 297 + 298 + if (pll_info->enable_bit < 0) 299 + return true; 306 300 307 301 ctl = readl(cgu->base + pll_info->reg); 308 302
+6 -4
drivers/clk/ingenic/cgu.h
··· 42 42 * @bypass_reg: the offset of the bypass control register within the CGU 43 43 * @bypass_bit: the index of the bypass bit in the PLL control register, or 44 44 * -1 if there is no bypass bit 45 - * @enable_bit: the index of the enable bit in the PLL control register 46 - * @stable_bit: the index of the stable bit in the PLL control register 45 + * @enable_bit: the index of the enable bit in the PLL control register, or 46 + * -1 if there is no enable bit (ie, the PLL is always on) 47 + * @stable_bit: the index of the stable bit in the PLL control register, or 48 + * -1 if there is no stable bit 47 49 */ 48 50 struct ingenic_cgu_pll_info { 49 51 unsigned reg; ··· 56 54 u8 od_shift, od_bits, od_max; 57 55 unsigned bypass_reg; 58 56 s8 bypass_bit; 59 - u8 enable_bit; 60 - u8 stable_bit; 57 + s8 enable_bit; 58 + s8 stable_bit; 61 59 void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, 62 60 unsigned long rate, unsigned long parent_rate, 63 61 unsigned int *m, unsigned int *n, unsigned int *od);