+3 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

reviewed

··· 2279 2279 * Return: 2280 2280 * return the latest index. 2281 2281 */ 2282 2282 - u32 amdgpu_gfx_csb_preamble_start(volatile u32 *buffer) 2282 2282 + u32 amdgpu_gfx_csb_preamble_start(u32 *buffer) 2283 2283 { 2284 2284 u32 count = 0; 2285 2285 ··· 2303 2303 * Return: 2304 2304 * return the latest index. 2305 2305 */ 2306 2306 - u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, volatile u32 *buffer, u32 count) 2306 2306 + u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count) 2307 2307 { 2308 2308 const struct cs_section_def *sect = NULL; 2309 2309 const struct cs_extent_def *ext = NULL; ··· 2330 2330 * @buffer: This is an output variable that gets the PACKET3 preamble end. 2331 2331 * @count: Index to start set the preemble end. 2332 2332 */ 2333 2333 - void amdgpu_gfx_csb_preamble_end(volatile u32 *buffer, u32 count) 2333 2333 + void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count) 2334 2334 { 2335 2335 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2336 2336 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);

+3 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

reviewed

··· 642 642 void amdgpu_gfx_profile_idle_work_handler(struct work_struct *work); 643 643 void amdgpu_gfx_profile_ring_begin_use(struct amdgpu_ring *ring); 644 644 void amdgpu_gfx_profile_ring_end_use(struct amdgpu_ring *ring); 645 645 - u32 amdgpu_gfx_csb_preamble_start(volatile u32 *buffer); 646 646 - u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, volatile u32 *buffer, u32 count); 647 647 - void amdgpu_gfx_csb_preamble_end(volatile u32 *buffer, u32 count); 645 645 + u32 amdgpu_gfx_csb_preamble_start(u32 *buffer); 646 646 + u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count); 647 647 + void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count); 648 648 649 649 void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev); 650 650 void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev);

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

reviewed

··· 251 251 * and it also provides a pointer to it which is used by the firmware 252 252 * to load the clear state in some cases. 253 253 */ 254 254 - void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer); 254 254 + void (*get_csb_buffer)(struct amdgpu_device *adev, u32 *buffer); 255 255 int (*get_cp_table_num)(struct amdgpu_device *adev); 256 256 int (*resume)(struct amdgpu_device *adev); 257 257 void (*stop)(struct amdgpu_device *adev); ··· 281 281 /* for clear state */ 282 282 struct amdgpu_bo *clear_state_obj; 283 283 uint64_t clear_state_gpu_addr; 284 284 - volatile uint32_t *cs_ptr; 284 284 + uint32_t *cs_ptr; 285 285 const struct cs_section_def *cs_data; 286 286 u32 clear_state_size; 287 287 /* for cp tables */

+1 -2

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

reviewed

··· 4322 4322 return count; 4323 4323 } 4324 4324 4325 4325 - static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4326 4326 - volatile u32 *buffer) 4325 4325 + static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 4327 4326 { 4328 4327 u32 count = 0; 4329 4328 int ctx_reg_offset;

+1 -2

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

reviewed

··· 850 850 return count; 851 851 } 852 852 853 853 - static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 854 854 - volatile u32 *buffer) 853 853 + static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 855 854 { 856 855 u32 count = 0; 857 856 int ctx_reg_offset;

+1 -2

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

reviewed

··· 685 685 return count; 686 686 } 687 687 688 688 - static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 689 689 - volatile u32 *buffer) 688 688 + static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 690 689 { 691 690 u32 count = 0, clustercount = 0, i; 692 691 const struct cs_section_def *sect = NULL;

+3 -4

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

reviewed

··· 86 86 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); 87 87 88 88 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 89 89 - static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 89 89 + static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer); 90 90 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 91 91 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 92 92 ··· 2354 2354 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2355 2355 { 2356 2356 const u32 *src_ptr; 2357 2357 - volatile u32 *dst_ptr; 2357 2357 + u32 *dst_ptr; 2358 2358 u32 dws; 2359 2359 u64 reg_list_mc_addr; 2360 2360 const struct cs_section_def *cs_data; ··· 2855 2855 return count; 2856 2856 } 2857 2857 2858 2858 - static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, 2859 2859 - volatile u32 *buffer) 2858 2858 + static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 2860 2859 { 2861 2860 u32 count = 0; 2862 2861

+2 -3

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

reviewed

··· 883 883 }; 884 884 885 885 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); 886 886 - static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 886 886 + static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer); 887 887 static void gfx_v7_0_init_pg(struct amdgpu_device *adev); 888 888 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); 889 889 ··· 3882 3882 return count; 3883 3883 } 3884 3884 3885 3885 - static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, 3886 3886 - volatile u32 *buffer) 3885 3885 + static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 3887 3886 { 3888 3887 u32 count = 0; 3889 3888

+1 -2

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

reviewed

··· 1220 1220 return err; 1221 1221 } 1222 1222 1223 1223 - static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, 1224 1224 - volatile u32 *buffer) 1223 1223 + static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 1225 1224 { 1226 1225 u32 count = 0; 1227 1226

+1 -2

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

reviewed

··· 1648 1648 return count; 1649 1649 } 1650 1650 1651 1651 - static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 1652 1652 - volatile u32 *buffer) 1651 1651 + static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 1653 1652 { 1654 1653 u32 count = 0; 1655 1654