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dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks

On the affected Qualcomm platforms the display clock controller has
additional DP input clocks, describe them in DT schema.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-1-ad153c747a97@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson d85dc696 65424b99

+28
+28
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
··· 27 27 - qcom,sm8350-dispcc 28 28 29 29 clocks: 30 + minItems: 7 30 31 items: 31 32 - description: Board XO source 32 33 - description: Byte clock from DSI PHY0 ··· 36 35 - description: Pixel clock from DSI PHY1 37 36 - description: Link clock from DP PHY 38 37 - description: VCO DIV clock from DP PHY 38 + - description: Link clock from eDP PHY 39 + - description: VCO DIV clock from eDP PHY 40 + - description: Link clock from DP1 PHY 41 + - description: VCO DIV clock from DP1 PHY 42 + - description: Link clock from DP2 PHY 43 + - description: VCO DIV clock from DP2 PHY 39 44 40 45 clock-names: 46 + minItems: 7 41 47 items: 42 48 - const: bi_tcxo 43 49 - const: dsi0_phy_pll_out_byteclk ··· 53 45 - const: dsi1_phy_pll_out_dsiclk 54 46 - const: dp_phy_pll_link_clk 55 47 - const: dp_phy_pll_vco_div_clk 48 + - const: edp_phy_pll_link_clk 49 + - const: edp_phy_pll_vco_div_clk 50 + - const: dptx1_phy_pll_link_clk 51 + - const: dptx1_phy_pll_vco_div_clk 52 + - const: dptx2_phy_pll_link_clk 53 + - const: dptx2_phy_pll_vco_div_clk 56 54 57 55 '#clock-cells': 58 56 const: 1 ··· 90 76 - '#clock-cells' 91 77 - '#reset-cells' 92 78 - '#power-domain-cells' 79 + 80 + allOf: 81 + - if: 82 + not: 83 + properties: 84 + compatible: 85 + contains: 86 + const: qcom,sc8180x-dispcc 87 + then: 88 + properties: 89 + clocks: 90 + maxItems: 7 91 + clock-names: 92 + maxItems: 7 93 93 94 94 additionalProperties: false 95 95