tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev

* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev:
sata_mv: Fix broken Marvell 7042 support.
libata: Fix early use of port printk. (Was Re: ata4294967295: failed to start port (errno=-19))
ata_piix: add more toshiba laptops to broken suspend list
libata: More IVB horkage from TSST
libata: report protocol and full CDB on error
Several fixes for the AVR32 PATA driver
sata_mv: fix compilation error when enabling DEBUG
Set proper ATA UDMA mode for bf548 according to system clock.

Linus Torvalds d894f451 4200b66c

+149 -61
+28
drivers/ata/ata_piix.c
··· 967 967 }, 968 968 }, 969 969 { 970 + .ident = "TECRA M3", 971 + .matches = { 972 + DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 973 + DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), 974 + }, 975 + }, 976 + { 970 977 .ident = "TECRA M5", 971 978 .matches = { 972 979 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), ··· 988 981 }, 989 982 }, 990 983 { 984 + .ident = "TECRA A8", 985 + .matches = { 986 + DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 987 + DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), 988 + }, 989 + }, 990 + { 991 + .ident = "Satellite R25", 992 + .matches = { 993 + DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 994 + DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), 995 + }, 996 + }, 997 + { 991 998 .ident = "Satellite U200", 992 999 .matches = { 993 1000 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 994 1001 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 1002 + }, 1003 + }, 1004 + { 1005 + .ident = "Satellite U200", 1006 + .matches = { 1007 + DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1008 + DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), 995 1009 }, 996 1010 }, 997 1011 {
+5 -3
drivers/ata/libata-core.c
··· 4185 4185 /* Devices which get the IVB wrong */ 4186 4186 { "QUANTUM FIREBALLlct10 05", "A03.0900", ATA_HORKAGE_IVB, }, 4187 4187 { "TSSTcorp CDDVDW SH-S202J", "SB00", ATA_HORKAGE_IVB, }, 4188 + { "TSSTcorp CDDVDW SH-S202J", "SB01", ATA_HORKAGE_IVB, }, 4189 + { "TSSTcorp CDDVDW SH-S202N", "SB00", ATA_HORKAGE_IVB, }, 4190 + { "TSSTcorp CDDVDW SH-S202N", "SB01", ATA_HORKAGE_IVB, }, 4188 4191 4189 4192 /* End Marker */ 4190 4193 { } ··· 6967 6964 if (ap->ops->port_start) { 6968 6965 rc = ap->ops->port_start(ap); 6969 6966 if (rc) { 6970 - ata_port_printk(ap, KERN_ERR, "failed to " 6971 - "start port (errno=%d)\n", rc); 6967 + if (rc != -ENODEV) 6968 + dev_printk(KERN_ERR, host->dev, "failed to start port %d (errno=%d)\n", i, rc); 6972 6969 goto err_out; 6973 6970 } 6974 6971 } 6975 - 6976 6972 ata_eh_freeze_port(ap); 6977 6973 } 6978 6974
+33 -9
drivers/ata/libata-eh.c
··· 1850 1850 ehc->i.serror & SERR_DEV_XCHG ? "DevExch " : ""); 1851 1851 1852 1852 for (tag = 0; tag < ATA_MAX_QUEUE; tag++) { 1853 - static const char *dma_str[] = { 1854 - [DMA_BIDIRECTIONAL] = "bidi", 1855 - [DMA_TO_DEVICE] = "out", 1856 - [DMA_FROM_DEVICE] = "in", 1857 - [DMA_NONE] = "", 1858 - }; 1859 1853 struct ata_queued_cmd *qc = __ata_qc_from_tag(ap, tag); 1860 1854 struct ata_taskfile *cmd = &qc->tf, *res = &qc->result_tf; 1855 + const u8 *cdb = qc->cdb; 1856 + char data_buf[20] = ""; 1857 + char cdb_buf[70] = ""; 1861 1858 1862 1859 if (!(qc->flags & ATA_QCFLAG_FAILED) || 1863 1860 qc->dev->link != link || !qc->err_mask) 1864 1861 continue; 1865 1862 1863 + if (qc->dma_dir != DMA_NONE) { 1864 + static const char *dma_str[] = { 1865 + [DMA_BIDIRECTIONAL] = "bidi", 1866 + [DMA_TO_DEVICE] = "out", 1867 + [DMA_FROM_DEVICE] = "in", 1868 + }; 1869 + static const char *prot_str[] = { 1870 + [ATA_PROT_PIO] = "pio", 1871 + [ATA_PROT_DMA] = "dma", 1872 + [ATA_PROT_NCQ] = "ncq", 1873 + [ATA_PROT_ATAPI] = "pio", 1874 + [ATA_PROT_ATAPI_DMA] = "dma", 1875 + }; 1876 + 1877 + snprintf(data_buf, sizeof(data_buf), " %s %u %s", 1878 + prot_str[qc->tf.protocol], qc->nbytes, 1879 + dma_str[qc->dma_dir]); 1880 + } 1881 + 1882 + if (is_atapi_taskfile(&qc->tf)) 1883 + snprintf(cdb_buf, sizeof(cdb_buf), 1884 + "cdb %02x %02x %02x %02x %02x %02x %02x %02x " 1885 + "%02x %02x %02x %02x %02x %02x %02x %02x\n ", 1886 + cdb[0], cdb[1], cdb[2], cdb[3], 1887 + cdb[4], cdb[5], cdb[6], cdb[7], 1888 + cdb[8], cdb[9], cdb[10], cdb[11], 1889 + cdb[12], cdb[13], cdb[14], cdb[15]); 1890 + 1866 1891 ata_dev_printk(qc->dev, KERN_ERR, 1867 1892 "cmd %02x/%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x/%02x " 1868 - "tag %d cdb 0x%x data %u %s\n " 1893 + "tag %d%s\n %s" 1869 1894 "res %02x/%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x/%02x " 1870 1895 "Emask 0x%x (%s)%s\n", 1871 1896 cmd->command, cmd->feature, cmd->nsect, 1872 1897 cmd->lbal, cmd->lbam, cmd->lbah, 1873 1898 cmd->hob_feature, cmd->hob_nsect, 1874 1899 cmd->hob_lbal, cmd->hob_lbam, cmd->hob_lbah, 1875 - cmd->device, qc->tag, qc->cdb[0], qc->nbytes, 1876 - dma_str[qc->dma_dir], 1900 + cmd->device, qc->tag, data_buf, cdb_buf, 1877 1901 res->command, res->feature, res->nsect, 1878 1902 res->lbal, res->lbam, res->lbah, 1879 1903 res->hob_feature, res->hob_nsect,
+33 -28
drivers/ata/pata_at32.c
··· 28 28 #include <asm/arch/smc.h> 29 29 30 30 #define DRV_NAME "pata_at32" 31 - #define DRV_VERSION "0.0.2" 31 + #define DRV_VERSION "0.0.3" 32 32 33 33 /* 34 34 * CompactFlash controller memory layout relative to the base address: ··· 64 64 * Mode 2 | 8.3 | 240 ns | 0x07 65 65 * Mode 3 | 11.1 | 180 ns | 0x0f 66 66 * Mode 4 | 16.7 | 120 ns | 0x1f 67 + * 68 + * Alter PIO_MASK below according to table to set maximal PIO mode. 67 69 */ 68 70 #define PIO_MASK (0x1f) 69 71 ··· 87 85 */ 88 86 static int pata_at32_setup_timing(struct device *dev, 89 87 struct at32_ide_info *info, 90 - const struct ata_timing *timing) 88 + const struct ata_timing *ata) 91 89 { 92 - /* These two values are found through testing */ 93 - const int min_recover = 25; 94 - const int ncs_hold = 15; 95 - 96 90 struct smc_config *smc = &info->smc; 91 + struct smc_timing timing; 97 92 98 93 int active; 99 94 int recover; 100 95 96 + memset(&timing, 0, sizeof(struct smc_timing)); 97 + 101 98 /* Total cycle time */ 102 - smc->read_cycle = timing->cyc8b; 99 + timing.read_cycle = ata->cyc8b; 103 100 104 101 /* DIOR <= CFIOR timings */ 105 - smc->nrd_setup = timing->setup; 106 - smc->nrd_pulse = timing->act8b; 102 + timing.nrd_setup = ata->setup; 103 + timing.nrd_pulse = ata->act8b; 104 + timing.nrd_recover = ata->rec8b; 107 105 108 - /* Compute recover, extend total cycle if needed */ 109 - active = smc->nrd_setup + smc->nrd_pulse; 106 + /* Convert nanosecond timing to clock cycles */ 107 + smc_set_timing(smc, &timing); 108 + 109 + /* Add one extra cycle setup due to signal ring */ 110 + smc->nrd_setup = smc->nrd_setup + 1; 111 + 112 + active = smc->nrd_setup + smc->nrd_pulse; 110 113 recover = smc->read_cycle - active; 111 114 112 - if (recover < min_recover) { 113 - smc->read_cycle = active + min_recover; 114 - recover = min_recover; 115 - } 115 + /* Need at least two cycles recovery */ 116 + if (recover < 2) 117 + smc->read_cycle = active + 2; 116 118 117 119 /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */ 118 - smc->ncs_read_setup = 0; 119 - smc->ncs_read_pulse = active + ncs_hold; 120 + smc->ncs_read_setup = 1; 121 + smc->ncs_read_pulse = smc->read_cycle - 2; 120 122 121 123 /* Write timings same as read timings */ 122 124 smc->write_cycle = smc->read_cycle; ··· 129 123 smc->ncs_write_setup = smc->ncs_read_setup; 130 124 smc->ncs_write_pulse = smc->ncs_read_pulse; 131 125 132 - /* Do some debugging output */ 133 - dev_dbg(dev, "SMC: C=%d S=%d P=%d R=%d NCSS=%d NCSP=%d NCSR=%d\n", 126 + /* Do some debugging output of ATA and SMC timings */ 127 + dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n", 128 + ata->cyc8b, ata->setup, ata->act8b, ata->rec8b); 129 + 130 + dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n", 134 131 smc->read_cycle, smc->nrd_setup, smc->nrd_pulse, 135 - recover, smc->ncs_read_setup, smc->ncs_read_pulse, 136 - smc->read_cycle - smc->ncs_read_pulse); 132 + smc->ncs_read_setup, smc->ncs_read_pulse); 137 133 138 134 /* Finally, configure the SMC */ 139 135 return smc_set_configuration(info->cs, smc); ··· 190 182 }; 191 183 192 184 static struct ata_port_operations at32_port_ops = { 193 - .port_disable = ata_port_disable, 194 185 .set_piomode = pata_at32_set_piomode, 195 186 .tf_load = ata_tf_load, 196 187 .tf_read = ata_tf_read, ··· 210 203 211 204 .irq_clear = pata_at32_irq_clear, 212 205 .irq_on = ata_irq_on, 213 - .irq_ack = ata_irq_ack, 214 206 215 207 .port_start = ata_sff_port_start, 216 208 }; ··· 229 223 /* Setup ATA bindings */ 230 224 ap->ops = &at32_port_ops; 231 225 ap->pio_mask = PIO_MASK; 232 - ap->flags = ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS 233 - | ATA_FLAG_PIO_POLLING; 226 + ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS; 234 227 235 228 /* 236 229 * Since all 8-bit taskfile transfers has to go on the lower ··· 362 357 info->smc.tdf_mode = 0; /* TDF optimization disabled */ 363 358 info->smc.tdf_cycles = 0; /* No TDF wait cycles */ 364 359 365 - /* Setup ATA timing */ 360 + /* Setup SMC to ATA timing */ 366 361 ret = pata_at32_setup_timing(dev, info, &initial_timing); 367 362 if (ret) 368 363 goto err_setup_timing; 369 364 370 - /* Setup ATA addresses */ 365 + /* Map ATA address space */ 371 366 ret = -ENOMEM; 372 367 info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16); 373 368 info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16); ··· 378 373 pata_at32_debug_bus(dev, info); 379 374 #endif 380 375 381 - /* Register ATA device */ 376 + /* Setup and register ATA device */ 382 377 ret = pata_at32_init_one(dev, info); 383 378 if (ret) 384 379 goto err_ata_device;
+7
drivers/ata/pata_bf54x.c
··· 1489 1489 int board_idx = 0; 1490 1490 struct resource *res; 1491 1491 struct ata_host *host; 1492 + unsigned int fsclk = get_sclk(); 1493 + int udma_mode = 5; 1492 1494 const struct ata_port_info *ppi[] = 1493 1495 { &bfin_port_info[board_idx], NULL }; 1494 1496 ··· 1508 1506 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1509 1507 if (res == NULL) 1510 1508 return -EINVAL; 1509 + 1510 + while (bfin_port_info[board_idx].udma_mask>0 && udma_fsclk[udma_mode] > fsclk) { 1511 + udma_mode--; 1512 + bfin_port_info[board_idx].udma_mask >>= 1; 1513 + } 1511 1514 1512 1515 /* 1513 1516 * Now that that's out of the way, wire up the port..
+43 -21
drivers/ata/sata_mv.c
··· 164 164 MV_PCI_ERR_ATTRIBUTE = 0x1d48, 165 165 MV_PCI_ERR_COMMAND = 0x1d50, 166 166 167 - PCI_IRQ_CAUSE_OFS = 0x1d58, 168 - PCI_IRQ_MASK_OFS = 0x1d5c, 167 + PCI_IRQ_CAUSE_OFS = 0x1d58, 168 + PCI_IRQ_MASK_OFS = 0x1d5c, 169 169 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 170 + 171 + PCIE_IRQ_CAUSE_OFS = 0x1900, 172 + PCIE_IRQ_MASK_OFS = 0x1910, 173 + PCIE_UNMASK_ALL_IRQS = 0x70a, /* assorted bits */ 170 174 171 175 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 172 176 HC_MAIN_IRQ_MASK_OFS = 0x1d64, ··· 307 303 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 308 304 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 309 305 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 306 + MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 310 307 311 308 /* Port private flags (pp_flags) */ 312 309 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ ··· 393 388 u32 pre; 394 389 }; 395 390 396 - struct mv_host_priv; 391 + struct mv_host_priv { 392 + u32 hp_flags; 393 + struct mv_port_signal signal[8]; 394 + const struct mv_hw_ops *ops; 395 + u32 irq_cause_ofs; 396 + u32 irq_mask_ofs; 397 + u32 unmask_all_irqs; 398 + }; 399 + 397 400 struct mv_hw_ops { 398 401 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 399 402 unsigned int port); ··· 412 399 unsigned int n_hc); 413 400 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 414 401 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio); 415 - }; 416 - 417 - struct mv_host_priv { 418 - u32 hp_flags; 419 - struct mv_port_signal signal[8]; 420 - const struct mv_hw_ops *ops; 421 402 }; 422 403 423 404 static void mv_irq_clear(struct ata_port *ap); ··· 638 631 /* Adaptec 1430SA */ 639 632 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 640 633 641 - { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 642 - 643 - /* add Marvell 7042 support */ 634 + /* Marvell 7042 support */ 644 635 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 636 + 637 + /* Highpoint RocketRAID PCIe series */ 638 + { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 639 + { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 645 640 646 641 { } /* terminate list */ 647 642 }; ··· 1657 1648 1658 1649 static void mv_pci_error(struct ata_host *host, void __iomem *mmio) 1659 1650 { 1651 + struct mv_host_priv *hpriv = host->private_data; 1660 1652 struct ata_port *ap; 1661 1653 struct ata_queued_cmd *qc; 1662 1654 struct ata_eh_info *ehi; 1663 1655 unsigned int i, err_mask, printed = 0; 1664 1656 u32 err_cause; 1665 1657 1666 - err_cause = readl(mmio + PCI_IRQ_CAUSE_OFS); 1658 + err_cause = readl(mmio + hpriv->irq_cause_ofs); 1667 1659 1668 1660 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 1669 1661 err_cause); ··· 1672 1662 DPRINTK("All regs @ PCI error\n"); 1673 1663 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 1674 1664 1675 - writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); 1665 + writelfl(0, mmio + hpriv->irq_cause_ofs); 1676 1666 1677 1667 for (i = 0; i < host->n_ports; i++) { 1678 1668 ap = host->ports[i]; ··· 1936 1926 #define ZERO(reg) writel(0, mmio + (reg)) 1937 1927 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio) 1938 1928 { 1929 + struct ata_host *host = dev_get_drvdata(&pdev->dev); 1930 + struct mv_host_priv *hpriv = host->private_data; 1939 1931 u32 tmp; 1940 1932 1941 1933 tmp = readl(mmio + MV_PCI_MODE); ··· 1949 1937 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 1950 1938 ZERO(HC_MAIN_IRQ_MASK_OFS); 1951 1939 ZERO(MV_PCI_SERR_MASK); 1952 - ZERO(PCI_IRQ_CAUSE_OFS); 1953 - ZERO(PCI_IRQ_MASK_OFS); 1940 + ZERO(hpriv->irq_cause_ofs); 1941 + ZERO(hpriv->irq_mask_ofs); 1954 1942 ZERO(MV_PCI_ERR_LOW_ADDRESS); 1955 1943 ZERO(MV_PCI_ERR_HIGH_ADDRESS); 1956 1944 ZERO(MV_PCI_ERR_ATTRIBUTE); ··· 2182 2170 mv_scr_read(ap, SCR_ERROR, &serror); 2183 2171 mv_scr_read(ap, SCR_CONTROL, &scontrol); 2184 2172 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " 2185 - "SCtrl 0x%08x\n", status, serror, scontrol); 2173 + "SCtrl 0x%08x\n", sstatus, serror, scontrol); 2186 2174 } 2187 2175 #endif 2188 2176 ··· 2502 2490 break; 2503 2491 2504 2492 case chip_7042: 2493 + hp_flags |= MV_HP_PCIE; 2505 2494 case chip_6042: 2506 2495 hpriv->ops = &mv6xxx_ops; 2507 2496 hp_flags |= MV_HP_GEN_IIE; ··· 2529 2516 } 2530 2517 2531 2518 hpriv->hp_flags = hp_flags; 2519 + if (hp_flags & MV_HP_PCIE) { 2520 + hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 2521 + hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 2522 + hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 2523 + } else { 2524 + hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 2525 + hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 2526 + hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 2527 + } 2532 2528 2533 2529 return 0; 2534 2530 } ··· 2617 2595 } 2618 2596 2619 2597 /* Clear any currently outstanding host interrupt conditions */ 2620 - writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); 2598 + writelfl(0, mmio + hpriv->irq_cause_ofs); 2621 2599 2622 2600 /* and unmask interrupt generation for host regs */ 2623 - writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS); 2601 + writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 2624 2602 2625 2603 if (IS_GEN_I(hpriv)) 2626 2604 writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS); ··· 2631 2609 "PCI int cause/mask=0x%08x/0x%08x\n", 2632 2610 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), 2633 2611 readl(mmio + HC_MAIN_IRQ_MASK_OFS), 2634 - readl(mmio + PCI_IRQ_CAUSE_OFS), 2635 - readl(mmio + PCI_IRQ_MASK_OFS)); 2612 + readl(mmio + hpriv->irq_cause_ofs), 2613 + readl(mmio + hpriv->irq_mask_ofs)); 2636 2614 2637 2615 done: 2638 2616 return rc;