tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

watchdog: rzg2l_wdt: Rely on the reset driver for doing proper reset

The reset driver has been adapted in commit da235d2fac21
("clk: renesas: rzg2l: Check reset monitor registers") to check the reset
monitor bits before declaring reset asserts/de-asserts as
successful/failure operations. With that, there is no need to keep the
reset workaround for RZ/V2M in place in the watchdog driver.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20240531065723.1085423-8-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>

authored by

Claudiu Beznea and committed by
Wim Van Sebroeck d8997ed7 900b9383

+4 -35
+4 -35
drivers/watchdog/rzg2l_wdt.c
··· 8 8 #include <linux/clk.h> 9 9 #include <linux/delay.h> 10 10 #include <linux/io.h> 11 - #include <linux/iopoll.h> 12 11 #include <linux/kernel.h> 13 12 #include <linux/module.h> 14 13 #include <linux/of.h> ··· 53 54 struct reset_control *rstc; 54 55 unsigned long osc_clk_rate; 55 56 unsigned long delay; 56 - unsigned long minimum_assertion_period; 57 57 struct clk *pclk; 58 58 struct clk *osc_clk; 59 59 enum rz_wdt_type devtype; 60 60 }; 61 - 62 - static int rzg2l_wdt_reset(struct rzg2l_wdt_priv *priv) 63 - { 64 - int err, status; 65 - 66 - if (priv->devtype == WDT_RZV2M) { 67 - /* WDT needs TYPE-B reset control */ 68 - err = reset_control_assert(priv->rstc); 69 - if (err) 70 - return err; 71 - ndelay(priv->minimum_assertion_period); 72 - err = reset_control_deassert(priv->rstc); 73 - if (err) 74 - return err; 75 - err = read_poll_timeout(reset_control_status, status, 76 - status != 1, 0, 1000, false, 77 - priv->rstc); 78 - } else { 79 - err = reset_control_reset(priv->rstc); 80 - } 81 - 82 - return err; 83 - } 84 61 85 62 static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv) 86 63 { ··· 164 189 unsigned long action, void *data) 165 190 { 166 191 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev); 192 + int ret; 167 193 168 194 clk_prepare_enable(priv->pclk); 169 195 clk_prepare_enable(priv->osc_clk); 170 196 171 197 if (priv->devtype == WDT_RZG2L) { 172 - int ret; 173 - 174 198 ret = reset_control_deassert(priv->rstc); 175 199 if (ret) 176 200 return ret; ··· 181 207 rzg2l_wdt_write(priv, PEEN_FORCE, PEEN); 182 208 } else { 183 209 /* RZ/V2M doesn't have parity error registers */ 184 - rzg2l_wdt_reset(priv); 210 + ret = reset_control_reset(priv->rstc); 211 + if (ret) 212 + return ret; 185 213 186 214 wdev->timeout = 0; 187 215 ··· 274 298 "failed to get cpg reset"); 275 299 276 300 priv->devtype = (uintptr_t)of_device_get_match_data(dev); 277 - 278 - if (priv->devtype == WDT_RZV2M) { 279 - priv->minimum_assertion_period = RZV2M_A_NSEC + 280 - 3 * F2CYCLE_NSEC(pclk_rate) + 5 * 281 - max(F2CYCLE_NSEC(priv->osc_clk_rate), 282 - F2CYCLE_NSEC(pclk_rate)); 283 - } 284 301 285 302 pm_runtime_enable(&pdev->dev); 286 303