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phy: qcom-qmp-pcie: use shorter tables identifiers

The QMP drivers all use 'tbl' to refer to their register initialisation
tables.

For consistency use 'tbls' rather than 'tables' to refer to the new
aggregate table structures.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221105145939.20318-9-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Johan Hovold and committed by
Vinod Koul d8c9a1e9 f8b64114

+45 -45
+45 -45
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 1313 1313 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1314 1314 }; 1315 1315 1316 - struct qmp_phy_cfg_tables { 1316 + struct qmp_phy_cfg_tbls { 1317 1317 const struct qmp_phy_init_tbl *serdes; 1318 1318 int serdes_num; 1319 1319 const struct qmp_phy_init_tbl *tx; ··· 1331 1331 int lanes; 1332 1332 1333 1333 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1334 - const struct qmp_phy_cfg_tables tables; 1334 + const struct qmp_phy_cfg_tbls tbls; 1335 1335 /* 1336 1336 * Additional init sequences for PHY blocks, providing additional 1337 1337 * register programming. They are used for providing separate sequences ··· 1339 1339 * 1340 1340 * If EP mode is not supported, both tables can be left unset. 1341 1341 */ 1342 - const struct qmp_phy_cfg_tables *tables_rc; 1343 - const struct qmp_phy_cfg_tables *tables_ep; 1342 + const struct qmp_phy_cfg_tbls *tbls_rc; 1343 + const struct qmp_phy_cfg_tbls *tbls_ep; 1344 1344 1345 1345 /* clock ids to be requested */ 1346 1346 const char * const *clk_list; ··· 1442 1442 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1443 1443 .lanes = 1, 1444 1444 1445 - .tables = { 1445 + .tbls = { 1446 1446 .serdes = ipq8074_pcie_serdes_tbl, 1447 1447 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1448 1448 .tx = ipq8074_pcie_tx_tbl, ··· 1467 1467 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1468 1468 .lanes = 1, 1469 1469 1470 - .tables = { 1470 + .tbls = { 1471 1471 .serdes = ipq8074_pcie_gen3_serdes_tbl, 1472 1472 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1473 1473 .tx = ipq8074_pcie_gen3_tx_tbl, ··· 1494 1494 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1495 1495 .lanes = 1, 1496 1496 1497 - .tables = { 1497 + .tbls = { 1498 1498 .serdes = ipq6018_pcie_serdes_tbl, 1499 1499 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1500 1500 .tx = ipq6018_pcie_tx_tbl, ··· 1521 1521 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1522 1522 .lanes = 1, 1523 1523 1524 - .tables = { 1524 + .tbls = { 1525 1525 .serdes = sdm845_qmp_pcie_serdes_tbl, 1526 1526 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1527 1527 .tx = sdm845_qmp_pcie_tx_tbl, ··· 1548 1548 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1549 1549 .lanes = 1, 1550 1550 1551 - .tables = { 1551 + .tbls = { 1552 1552 .serdes = sdm845_qhp_pcie_serdes_tbl, 1553 1553 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1554 1554 .tx = sdm845_qhp_pcie_tx_tbl, ··· 1573 1573 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1574 1574 .lanes = 1, 1575 1575 1576 - .tables = { 1576 + .tbls = { 1577 1577 .serdes = sm8250_qmp_pcie_serdes_tbl, 1578 1578 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1579 1579 .tx = sm8250_qmp_pcie_tx_tbl, ··· 1585 1585 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1586 1586 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1587 1587 }, 1588 - .tables_rc = &(const struct qmp_phy_cfg_tables) { 1588 + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1589 1589 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1590 1590 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1591 1591 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, ··· 1610 1610 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1611 1611 .lanes = 2, 1612 1612 1613 - .tables = { 1613 + .tbls = { 1614 1614 .serdes = sm8250_qmp_pcie_serdes_tbl, 1615 1615 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1616 1616 .tx = sm8250_qmp_pcie_tx_tbl, ··· 1622 1622 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1623 1623 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1624 1624 }, 1625 - .tables_rc = &(const struct qmp_phy_cfg_tables) { 1625 + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1626 1626 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 1627 1627 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1628 1628 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, ··· 1647 1647 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1648 1648 .lanes = 1, 1649 1649 1650 - .tables = { 1650 + .tbls = { 1651 1651 .serdes = msm8998_pcie_serdes_tbl, 1652 1652 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1653 1653 .tx = msm8998_pcie_tx_tbl, ··· 1674 1674 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1675 1675 .lanes = 1, 1676 1676 1677 - .tables = { 1677 + .tbls = { 1678 1678 .serdes = sc8180x_qmp_pcie_serdes_tbl, 1679 1679 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1680 1680 .tx = sc8180x_qmp_pcie_tx_tbl, ··· 1701 1701 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1702 1702 .lanes = 2, 1703 1703 1704 - .tables = { 1704 + .tbls = { 1705 1705 .serdes = sdx55_qmp_pcie_serdes_tbl, 1706 1706 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1707 1707 .tx = sdx55_qmp_pcie_tx_tbl, ··· 1728 1728 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 1729 1729 .lanes = 1, 1730 1730 1731 - .tables = { 1731 + .tbls = { 1732 1732 .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, 1733 1733 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 1734 1734 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, ··· 1755 1755 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 1756 1756 .lanes = 2, 1757 1757 1758 - .tables = { 1758 + .tbls = { 1759 1759 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 1760 1760 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 1761 1761 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, ··· 1768 1768 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 1769 1769 }, 1770 1770 1771 - .tables_rc = &(const struct qmp_phy_cfg_tables) { 1771 + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1772 1772 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 1773 1773 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 1774 1774 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 1775 1775 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 1776 1776 }, 1777 1777 1778 - .tables_ep = &(const struct qmp_phy_cfg_tables) { 1778 + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 1779 1779 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 1780 1780 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 1781 1781 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, ··· 1820 1820 qmp_pcie_configure_lane(base, tbl, num, 0xff); 1821 1821 } 1822 1822 1823 - static void qmp_pcie_serdes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) 1823 + static void qmp_pcie_serdes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 1824 1824 { 1825 1825 void __iomem *serdes = qmp->serdes; 1826 1826 1827 - if (!tables) 1827 + if (!tbls) 1828 1828 return; 1829 1829 1830 - qmp_pcie_configure(serdes, tables->serdes, tables->serdes_num); 1830 + qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); 1831 1831 } 1832 1832 1833 - static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) 1833 + static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 1834 1834 { 1835 1835 const struct qmp_phy_cfg *cfg = qmp->cfg; 1836 1836 void __iomem *tx = qmp->tx; ··· 1838 1838 void __iomem *tx2 = qmp->tx2; 1839 1839 void __iomem *rx2 = qmp->rx2; 1840 1840 1841 - if (!tables) 1841 + if (!tbls) 1842 1842 return; 1843 1843 1844 - qmp_pcie_configure_lane(tx, tables->tx, tables->tx_num, 1); 1845 - qmp_pcie_configure_lane(rx, tables->rx, tables->rx_num, 1); 1844 + qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); 1845 + qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); 1846 1846 1847 1847 if (cfg->lanes >= 2) { 1848 - qmp_pcie_configure_lane(tx2, tables->tx, tables->tx_num, 2); 1849 - qmp_pcie_configure_lane(rx2, tables->rx, tables->rx_num, 2); 1848 + qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); 1849 + qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); 1850 1850 } 1851 1851 } 1852 1852 1853 - static void qmp_pcie_pcs_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) 1853 + static void qmp_pcie_pcs_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 1854 1854 { 1855 1855 void __iomem *pcs = qmp->pcs; 1856 1856 void __iomem *pcs_misc = qmp->pcs_misc; 1857 1857 1858 - if (!tables) 1858 + if (!tbls) 1859 1859 return; 1860 1860 1861 - qmp_pcie_configure(pcs, tables->pcs, tables->pcs_num); 1862 - qmp_pcie_configure(pcs_misc, tables->pcs_misc, tables->pcs_misc_num); 1861 + qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); 1862 + qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 1863 1863 } 1864 1864 1865 1865 static int qmp_pcie_init(struct phy *phy) ··· 1918 1918 { 1919 1919 struct qmp_pcie *qmp = phy_get_drvdata(phy); 1920 1920 const struct qmp_phy_cfg *cfg = qmp->cfg; 1921 - const struct qmp_phy_cfg_tables *mode_tables; 1921 + const struct qmp_phy_cfg_tbls *mode_tbls; 1922 1922 void __iomem *pcs = qmp->pcs; 1923 1923 void __iomem *status; 1924 1924 unsigned int mask, val; ··· 1928 1928 cfg->pwrdn_ctrl); 1929 1929 1930 1930 if (qmp->mode == PHY_MODE_PCIE_RC) 1931 - mode_tables = cfg->tables_rc; 1931 + mode_tbls = cfg->tbls_rc; 1932 1932 else 1933 - mode_tables = cfg->tables_ep; 1933 + mode_tbls = cfg->tbls_ep; 1934 1934 1935 - qmp_pcie_serdes_init(qmp, &cfg->tables); 1936 - qmp_pcie_serdes_init(qmp, mode_tables); 1935 + qmp_pcie_serdes_init(qmp, &cfg->tbls); 1936 + qmp_pcie_serdes_init(qmp, mode_tbls); 1937 1937 1938 1938 ret = clk_prepare_enable(qmp->pipe_clk); 1939 1939 if (ret) { ··· 1942 1942 } 1943 1943 1944 1944 /* Tx, Rx, and PCS configurations */ 1945 - qmp_pcie_lanes_init(qmp, &cfg->tables); 1946 - qmp_pcie_lanes_init(qmp, mode_tables); 1945 + qmp_pcie_lanes_init(qmp, &cfg->tbls); 1946 + qmp_pcie_lanes_init(qmp, mode_tbls); 1947 1947 1948 - qmp_pcie_pcs_init(qmp, &cfg->tables); 1949 - qmp_pcie_pcs_init(qmp, mode_tables); 1948 + qmp_pcie_pcs_init(qmp, &cfg->tbls); 1949 + qmp_pcie_pcs_init(qmp, mode_tbls); 1950 1950 1951 1951 /* Pull PHY out of reset state */ 1952 1952 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ··· 2217 2217 qmp->pcs_misc = qmp->pcs + 0x400; 2218 2218 2219 2219 if (IS_ERR(qmp->pcs_misc)) { 2220 - if (cfg->tables.pcs_misc || 2221 - (cfg->tables_rc && cfg->tables_rc->pcs_misc) || 2222 - (cfg->tables_ep && cfg->tables_ep->pcs_misc)) { 2220 + if (cfg->tbls.pcs_misc || 2221 + (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 2222 + (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 2223 2223 return PTR_ERR(qmp->pcs_misc); 2224 2224 } 2225 2225 }