tjh.dev / kernel
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dmaengine: fsl-edma: add i.MX8ULP edma support

Add support for the i.MX8ULP platform to the eDMA driver. Introduce the use
of the correct FSL_EDMA_DRV_HAS_CHCLK flag to handle per-channel clock
configurations.

Signed-off-by: Joy Zou <joy.zou@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240323-8ulp_edma-v3-5-c0e981027c05@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Joy Zou and committed by
Vinod Koul d8d43558 b14f56be

+29
+6
drivers/dma/fsl-edma-common.c
··· 3 3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc 4 4 // Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it> 5 5 6 + #include <linux/clk.h> 6 7 #include <linux/dmapool.h> 7 8 #include <linux/module.h> 8 9 #include <linux/slab.h> ··· 811 810 { 812 811 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 813 812 813 + if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK) 814 + clk_prepare_enable(fsl_chan->clk); 815 + 814 816 fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, 815 817 fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ? 816 818 sizeof(struct fsl_edma_hw_tcd64) : sizeof(struct fsl_edma_hw_tcd), ··· 842 838 fsl_chan->tcd_pool = NULL; 843 839 fsl_chan->is_sw = false; 844 840 fsl_chan->srcid = 0; 841 + if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK) 842 + clk_disable_unprepare(fsl_chan->clk); 845 843 } 846 844 847 845 void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
+1
drivers/dma/fsl-edma-common.h
··· 192 192 #define FSL_EDMA_DRV_WRAP_IO BIT(3) 193 193 #define FSL_EDMA_DRV_EDMA64 BIT(4) 194 194 #define FSL_EDMA_DRV_HAS_PD BIT(5) 195 + #define FSL_EDMA_DRV_HAS_CHCLK BIT(6) 195 196 #define FSL_EDMA_DRV_HAS_CHMUX BIT(7) 196 197 /* imx8 QM audio edma remote local swapped */ 197 198 #define FSL_EDMA_DRV_QUIRK_SWAPPED BIT(8)
+22
drivers/dma/fsl-edma-main.c
··· 356 356 .setup_irq = fsl_edma3_irq_init, 357 357 }; 358 358 359 + static struct fsl_edma_drvdata imx8ulp_data = { 360 + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK | 361 + FSL_EDMA_DRV_EDMA3, 362 + .chreg_space_sz = 0x10000, 363 + .chreg_off = 0x10000, 364 + .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), 365 + .mux_skip = 0x10000, 366 + .setup_irq = fsl_edma3_irq_init, 367 + }; 368 + 359 369 static struct fsl_edma_drvdata imx93_data3 = { 360 370 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, 361 371 .chreg_space_sz = 0x10000, ··· 398 388 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, 399 389 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data}, 400 390 { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data}, 391 + { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data}, 401 392 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, 402 393 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, 403 394 { .compatible = "fsl,imx95-edma5", .data = &imx95_data5}, ··· 452 441 struct fsl_edma_engine *fsl_edma; 453 442 const struct fsl_edma_drvdata *drvdata = NULL; 454 443 u32 chan_mask[2] = {0, 0}; 444 + char clk_name[36]; 455 445 struct edma_regs *regs; 456 446 int chans; 457 447 int ret, i; ··· 562 550 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; 563 551 fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip; 564 552 553 + if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { 554 + snprintf(clk_name, sizeof(clk_name), "ch%02d", i); 555 + fsl_chan->clk = devm_clk_get_enabled(&pdev->dev, 556 + (const char *)clk_name); 557 + 558 + if (IS_ERR(fsl_chan->clk)) 559 + return PTR_ERR(fsl_chan->clk); 560 + } 565 561 fsl_chan->pdev = pdev; 566 562 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); 567 563 568 564 edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr); 569 565 fsl_edma_chan_mux(fsl_chan, 0, false); 566 + if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) 567 + clk_disable_unprepare(fsl_chan->clk); 570 568 } 571 569 572 570 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);