Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: qat - consolidate service enums
The enums `adf_base_services` (used in rate limiting) and `adf_services`
define the same values, resulting in code duplication.
To improve consistency across the QAT driver: (1) rename `adf_services`
to `adf_base_services` in adf_cfg_services.c to better reflect its role
in defining core services (those with dedicated accelerators),
(2) introduce a new `adf_extended_services` enum starting from
`SVC_BASE_COUNT`, and move `SVC_DCC` into it, as it represents an
extended service (DC with chaining), and (3) remove the redundant
`adf_base_services` enum from the rate limiting implementation.
This does not introduce any functional change.
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Suman Kumar Chakraborty
and committed by
Herbert Xu
d8d7e283
fa37d386
+47
-50
+3
-3
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
+3
-3
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
···
296
296
rl_data->pcie_scale_div = ADF_420XX_RL_PCIE_SCALE_FACTOR_DIV;
297
297
rl_data->pcie_scale_mul = ADF_420XX_RL_PCIE_SCALE_FACTOR_MUL;
298
298
rl_data->dcpr_correction = ADF_420XX_RL_DCPR_CORRECTION;
299
-
rl_data->max_tp[ADF_SVC_ASYM] = ADF_420XX_RL_MAX_TP_ASYM;
300
-
rl_data->max_tp[ADF_SVC_SYM] = ADF_420XX_RL_MAX_TP_SYM;
301
-
rl_data->max_tp[ADF_SVC_DC] = ADF_420XX_RL_MAX_TP_DC;
299
+
rl_data->max_tp[SVC_ASYM] = ADF_420XX_RL_MAX_TP_ASYM;
300
+
rl_data->max_tp[SVC_SYM] = ADF_420XX_RL_MAX_TP_SYM;
301
+
rl_data->max_tp[SVC_DC] = ADF_420XX_RL_MAX_TP_DC;
302
302
rl_data->scan_interval = ADF_420XX_RL_SCANS_PER_SEC;
303
303
rl_data->scale_ref = ADF_420XX_RL_SLICE_REF;
304
304
}
+3
-3
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
+3
-3
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
···
222
222
rl_data->pcie_scale_div = ADF_4XXX_RL_PCIE_SCALE_FACTOR_DIV;
223
223
rl_data->pcie_scale_mul = ADF_4XXX_RL_PCIE_SCALE_FACTOR_MUL;
224
224
rl_data->dcpr_correction = ADF_4XXX_RL_DCPR_CORRECTION;
225
-
rl_data->max_tp[ADF_SVC_ASYM] = ADF_4XXX_RL_MAX_TP_ASYM;
226
-
rl_data->max_tp[ADF_SVC_SYM] = ADF_4XXX_RL_MAX_TP_SYM;
227
-
rl_data->max_tp[ADF_SVC_DC] = ADF_4XXX_RL_MAX_TP_DC;
225
+
rl_data->max_tp[SVC_ASYM] = ADF_4XXX_RL_MAX_TP_ASYM;
226
+
rl_data->max_tp[SVC_SYM] = ADF_4XXX_RL_MAX_TP_SYM;
227
+
rl_data->max_tp[SVC_DC] = ADF_4XXX_RL_MAX_TP_DC;
228
228
rl_data->scan_interval = ADF_4XXX_RL_SCANS_PER_SEC;
229
229
rl_data->scale_ref = ADF_4XXX_RL_SLICE_REF;
230
230
}
+3
-3
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
+3
-3
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
···
103
103
{
104
104
int num_svc;
105
105
106
-
if (mask >= BIT(SVC_BASE_COUNT))
106
+
if (mask >= BIT(SVC_COUNT))
107
107
return false;
108
108
109
109
num_svc = hweight_long(mask);
···
138
138
return -EINVAL;
139
139
}
140
140
141
-
static enum adf_cfg_service_type get_ring_type(enum adf_services service)
141
+
static enum adf_cfg_service_type get_ring_type(unsigned int service)
142
142
{
143
143
switch (service) {
144
144
case SVC_SYM:
···
155
155
}
156
156
}
157
157
158
-
static const unsigned long *get_thrd_mask(enum adf_services service)
158
+
static const unsigned long *get_thrd_mask(unsigned int service)
159
159
{
160
160
switch (service) {
161
161
case SVC_SYM:
+4
-4
drivers/crypto/intel/qat/qat_common/adf_cfg_services.c
+4
-4
drivers/crypto/intel/qat/qat_common/adf_cfg_services.c
···
20
20
21
21
/*
22
22
* Ensure that the size of the array matches the number of services,
23
-
* SVC_BASE_COUNT, that is used to size the bitmap.
23
+
* SVC_COUNT, that is used to size the bitmap.
24
24
*/
25
-
static_assert(ARRAY_SIZE(adf_cfg_services) == SVC_BASE_COUNT);
25
+
static_assert(ARRAY_SIZE(adf_cfg_services) == SVC_COUNT);
26
26
27
27
/*
28
28
* Ensure that the maximum number of concurrent services that can be
···
35
35
* Ensure that the number of services fit a single unsigned long, as each
36
36
* service is represented by a bit in the mask.
37
37
*/
38
-
static_assert(BITS_PER_LONG >= SVC_BASE_COUNT);
38
+
static_assert(BITS_PER_LONG >= SVC_COUNT);
39
39
40
40
/*
41
41
* Ensure that size of the concatenation of all service strings is smaller
···
90
90
if (len < ADF_CFG_MAX_VAL_LEN_IN_BYTES)
91
91
return -ENOSPC;
92
92
93
-
for_each_set_bit(bit, &mask, SVC_BASE_COUNT) {
93
+
for_each_set_bit(bit, &mask, SVC_COUNT) {
94
94
if (offset)
95
95
offset += scnprintf(buf + offset, len - offset,
96
96
ADF_SERVICES_DELIMITER);
+7
-3
drivers/crypto/intel/qat/qat_common/adf_cfg_services.h
+7
-3
drivers/crypto/intel/qat/qat_common/adf_cfg_services.h
···
7
7
8
8
struct adf_accel_dev;
9
9
10
-
enum adf_services {
10
+
enum adf_base_services {
11
11
SVC_ASYM = 0,
12
12
SVC_SYM,
13
13
SVC_DC,
14
14
SVC_DECOMP,
15
-
SVC_DCC,
16
15
SVC_BASE_COUNT
17
16
};
18
17
18
+
enum adf_extended_services {
19
+
SVC_DCC = SVC_BASE_COUNT,
20
+
SVC_COUNT
21
+
};
22
+
19
23
enum adf_composed_services {
20
-
SVC_SYM_ASYM = SVC_BASE_COUNT,
24
+
SVC_SYM_ASYM = SVC_COUNT,
21
25
SVC_SYM_DC,
22
26
SVC_ASYM_DC,
23
27
};
+1
-1
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
+1
-1
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
+17
-18
drivers/crypto/intel/qat/qat_common/adf_rl.c
+17
-18
drivers/crypto/intel/qat/qat_common/adf_rl.c
···
13
13
#include <linux/units.h>
14
14
15
15
#include "adf_accel_devices.h"
16
+
#include "adf_cfg_services.h"
16
17
#include "adf_common_drv.h"
17
18
#include "adf_rl_admin.h"
18
19
#include "adf_rl.h"
···
56
55
}
57
56
}
58
57
59
-
if (sla_in->srv >= ADF_SVC_NONE) {
58
+
if (sla_in->srv >= SVC_BASE_COUNT) {
60
59
dev_notice(&GET_DEV(accel_dev),
61
60
"Wrong service type\n");
62
61
return -EINVAL;
···
172
171
static enum adf_cfg_service_type srv_to_cfg_svc_type(enum adf_base_services rl_srv)
173
172
{
174
173
switch (rl_srv) {
175
-
case ADF_SVC_ASYM:
174
+
case SVC_ASYM:
176
175
return ASYM;
177
-
case ADF_SVC_SYM:
176
+
case SVC_SYM:
178
177
return SYM;
179
-
case ADF_SVC_DC:
178
+
case SVC_DC:
180
179
return COMP;
181
-
case ADF_SVC_DECOMP:
180
+
case SVC_DECOMP:
182
181
return DECOMP;
183
182
default:
184
183
return UNUSED;
···
563
562
avail_slice_cycles = hw_data->clock_frequency;
564
563
565
564
switch (svc_type) {
566
-
case ADF_SVC_ASYM:
565
+
case SVC_ASYM:
567
566
avail_slice_cycles *= device_data->slices.pke_cnt;
568
567
break;
569
-
case ADF_SVC_SYM:
568
+
case SVC_SYM:
570
569
avail_slice_cycles *= device_data->slices.cph_cnt;
571
570
break;
572
-
case ADF_SVC_DC:
571
+
case SVC_DC:
573
572
avail_slice_cycles *= device_data->slices.dcpr_cnt;
574
573
break;
575
574
default:
···
619
618
sla_to_bytes *= device_data->max_tp[svc_type];
620
619
do_div(sla_to_bytes, device_data->scale_ref);
621
620
622
-
sla_to_bytes *= (svc_type == ADF_SVC_ASYM) ? RL_TOKEN_ASYM_SIZE :
623
-
BYTES_PER_MBIT;
624
-
if (svc_type == ADF_SVC_DC && is_bw_out)
621
+
sla_to_bytes *= (svc_type == SVC_ASYM) ? RL_TOKEN_ASYM_SIZE : BYTES_PER_MBIT;
622
+
if (svc_type == SVC_DC && is_bw_out)
625
623
sla_to_bytes *= device_data->slices.dcpr_cnt -
626
624
device_data->dcpr_correction;
627
625
···
731
731
sla_in.type = RL_ROOT;
732
732
sla_in.parent_id = RL_PARENT_DEFAULT_ID;
733
733
734
-
for (i = 0; i < ADF_SVC_NONE; i++) {
734
+
for (i = 0; i < SVC_BASE_COUNT; i++) {
735
735
if (!is_service_enabled(accel_dev, i))
736
736
continue;
737
737
···
746
746
747
747
/* Init default cluster for each root */
748
748
sla_in.type = RL_CLUSTER;
749
-
for (i = 0; i < ADF_SVC_NONE; i++) {
749
+
for (i = 0; i < SVC_BASE_COUNT; i++) {
750
750
if (!rl_data->root[i])
751
751
continue;
752
-
753
752
sla_in.cir = rl_data->root[i]->cir;
754
753
sla_in.pir = sla_in.cir;
755
754
sla_in.srv = rl_data->root[i]->srv;
···
987
988
struct rl_sla *sla = NULL;
988
989
int i;
989
990
990
-
if (srv >= ADF_SVC_NONE)
991
+
if (srv >= SVC_BASE_COUNT)
991
992
return -EINVAL;
992
993
993
994
if (sla_id > RL_SLA_EMPTY_ID && !validate_sla_id(accel_dev, sla_id)) {
···
1086
1087
int ret = 0;
1087
1088
1088
1089
/* Validate device parameters */
1089
-
if (RL_VALIDATE_NON_ZERO(rl_hw_data->max_tp[ADF_SVC_ASYM]) ||
1090
-
RL_VALIDATE_NON_ZERO(rl_hw_data->max_tp[ADF_SVC_SYM]) ||
1091
-
RL_VALIDATE_NON_ZERO(rl_hw_data->max_tp[ADF_SVC_DC]) ||
1090
+
if (RL_VALIDATE_NON_ZERO(rl_hw_data->max_tp[SVC_ASYM]) ||
1091
+
RL_VALIDATE_NON_ZERO(rl_hw_data->max_tp[SVC_SYM]) ||
1092
+
RL_VALIDATE_NON_ZERO(rl_hw_data->max_tp[SVC_DC]) ||
1092
1093
RL_VALIDATE_NON_ZERO(rl_hw_data->scan_interval) ||
1093
1094
RL_VALIDATE_NON_ZERO(rl_hw_data->pcie_scale_div) ||
1094
1095
RL_VALIDATE_NON_ZERO(rl_hw_data->pcie_scale_mul) ||
+2
-8
drivers/crypto/intel/qat/qat_common/adf_rl.h
+2
-8
drivers/crypto/intel/qat/qat_common/adf_rl.h
···
7
7
#include <linux/mutex.h>
8
8
#include <linux/types.h>
9
9
10
+
#include "adf_cfg_services.h"
11
+
10
12
struct adf_accel_dev;
11
13
12
14
#define RL_ROOT_MAX 4
···
24
22
RL_ROOT,
25
23
RL_CLUSTER,
26
24
RL_LEAF,
27
-
};
28
-
29
-
enum adf_base_services {
30
-
ADF_SVC_ASYM = 0,
31
-
ADF_SVC_SYM,
32
-
ADF_SVC_DC,
33
-
ADF_SVC_DECOMP,
34
-
ADF_SVC_NONE,
35
25
};
36
26
37
27
/**
+7
-7
drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c
+7
-7
drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c
···
32
32
};
33
33
34
34
static const char *const rl_services[] = {
35
-
[ADF_SVC_ASYM] = "asym",
36
-
[ADF_SVC_SYM] = "sym",
37
-
[ADF_SVC_DC] = "dc",
38
-
[ADF_SVC_DECOMP] = "decomp",
35
+
[SVC_ASYM] = "asym",
36
+
[SVC_SYM] = "sym",
37
+
[SVC_DC] = "dc",
38
+
[SVC_DECOMP] = "decomp",
39
39
};
40
40
41
41
static const char *const rl_operations[] = {
···
283
283
if (ret)
284
284
return ret;
285
285
286
-
if (get == ADF_SVC_NONE)
286
+
if (get == SVC_BASE_COUNT)
287
287
return -EINVAL;
288
288
289
289
return sysfs_emit(buf, "%s\n", rl_services[get]);
···
448
448
dev_err(&GET_DEV(accel_dev),
449
449
"Failed to create qat_rl attribute group\n");
450
450
451
-
data->cap_rem_srv = ADF_SVC_NONE;
452
-
data->input.srv = ADF_SVC_NONE;
451
+
data->cap_rem_srv = SVC_BASE_COUNT;
452
+
data->input.srv = SVC_BASE_COUNT;
453
453
data->sysfs_added = true;
454
454
455
455
return ret;