Merge tag 'riscv-for-linus-6.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Paul Walmsley:
"The notable changes here are the three RISC-V timer compare register
update sequence patches. These only apply to RV32 systems and are
related to the 64-bit timer compare value being split across two
separate 32-bit registers.

We weren't using the appropriate three-write sequence, documented in
the RISC-V ISA specifications, to avoid spurious timer interrupts
during the update sequence; so, these patches now use the recommended
sequence.

This doesn't affect 64-bit RISC-V systems, since the timer compare
value fits inside a single register and can be updated with a single
write.

- Fix the RISC-V timer compare register update sequence on RV32
systems to use the recommended sequence in the RISC-V ISA manual

This avoids spurious interrupts during updates

- Add a dependence on the new CONFIG_CACHEMAINT_FOR_DMA Kconfig
symbol for Renesas and StarFive RISC-V SoCs

- Add a temporary workaround for a Clang compiler bug caused by using
asm_goto_output for get_user()

- Clarify our documentation to specifically state a particular ISA
specification version for a chapter number reference"

* tag 'riscv-for-linus-6.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Add intermediate cast to 'unsigned long' in __get_user_asm
riscv: Use 64-bit variable for output in __get_user_asm
soc: renesas: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA
riscv: ERRATA_STARFIVE_JH7100: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA
riscv: suspend: Fix stimecmp update hazard on RV32
riscv: kvm: Fix vstimecmp update hazard on RV32
riscv: clocksource: Fix stimecmp update hazard on RV32
Documentation: riscv: uabi: Clarify ISA spec version for canonical order

Linus Torvalds 3 months ago d91a46d6 d04ed417

+25 -7

7 changed files

expand all

Documentation

arch

riscv

uabi.rst

arch

riscv

Kconfig.errata

include

asm

uaccess.h

kernel

suspend.c

kvm

vcpu_timer.c

drivers

clocksource

timer-riscv.c

soc

renesas

Kconfig

+3 -1

Documentation/arch/riscv/uabi.rst

··· 7 7 ------------------------------------ 8 8 9 9 The canonical order of ISA extension names in the ISA string is defined in 10 - chapter 27 of the unprivileged specification. 10 + Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA 11 + (Document Version 20191213). 12 + 11 13 The specification uses vague wording, such as should, when it comes to ordering, 12 14 so for our purposes the following rules apply: 13 15

arch/riscv/Kconfig.errata

··· 84 84 select DMA_GLOBAL_POOL 85 85 select RISCV_DMA_NONCOHERENT 86 86 select RISCV_NONSTANDARD_CACHE_OPS 87 + select CACHEMAINT_FOR_DMA 87 88 select SIFIVE_CCACHE 88 89 default n 89 90 help

+12 -2

arch/riscv/include/asm/uaccess.h

··· 97 97 */ 98 98 99 99 #ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT 100 + /* 101 + * Use a temporary variable for the output of the asm goto to avoid a 102 + * triggering an LLVM assertion due to sign extending the output when 103 + * it is used in later function calls: 104 + * https://github.com/llvm/llvm-project/issues/143795 105 + */ 100 106 #define __get_user_asm(insn, x, ptr, label) \ 107 + do { \ 108 + u64 __tmp; \ 101 109 asm_goto_output( \ 102 110 "1:\n" \ 103 111 " " insn " %0, %1\n" \ 104 112 _ASM_EXTABLE_UACCESS_ERR(1b, %l2, %0) \ 105 - : "=&r" (x) \ 106 - : "m" (*(ptr)) : : label) 113 + : "=&r" (__tmp) \ 114 + : "m" (*(ptr)) : : label); \ 115 + (x) = (__typeof__(x))(unsigned long)__tmp; \ 116 + } while (0) 107 117 #else /* !CONFIG_CC_HAS_ASM_GOTO_OUTPUT */ 108 118 #define __get_user_asm(insn, x, ptr, label) \ 109 119 do { \

+2 -1

arch/riscv/kernel/suspend.c

··· 51 51 52 52 #ifdef CONFIG_MMU 53 53 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) { 54 - csr_write(CSR_STIMECMP, context->stimecmp); 55 54 #if __riscv_xlen < 64 55 + csr_write(CSR_STIMECMP, ULONG_MAX); 56 56 csr_write(CSR_STIMECMPH, context->stimecmph); 57 57 #endif 58 + csr_write(CSR_STIMECMP, context->stimecmp); 58 59 } 59 60 60 61 csr_write(CSR_SATP, context->satp);

+4 -2

arch/riscv/kvm/vcpu_timer.c

··· 72 72 static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncycles) 73 73 { 74 74 #if defined(CONFIG_32BIT) 75 - ncsr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF); 75 + ncsr_write(CSR_VSTIMECMP, ULONG_MAX); 76 76 ncsr_write(CSR_VSTIMECMPH, ncycles >> 32); 77 + ncsr_write(CSR_VSTIMECMP, (u32)ncycles); 77 78 #else 78 79 ncsr_write(CSR_VSTIMECMP, ncycles); 79 80 #endif ··· 308 307 return; 309 308 310 309 #if defined(CONFIG_32BIT) 311 - ncsr_write(CSR_VSTIMECMP, (u32)t->next_cycles); 310 + ncsr_write(CSR_VSTIMECMP, ULONG_MAX); 312 311 ncsr_write(CSR_VSTIMECMPH, (u32)(t->next_cycles >> 32)); 312 + ncsr_write(CSR_VSTIMECMP, (u32)(t->next_cycles)); 313 313 #else 314 314 ncsr_write(CSR_VSTIMECMP, t->next_cycles); 315 315 #endif

+2 -1

drivers/clocksource/timer-riscv.c

··· 50 50 51 51 if (static_branch_likely(&riscv_sstc_available)) { 52 52 #if defined(CONFIG_32BIT) 53 - csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF); 53 + csr_write(CSR_STIMECMP, ULONG_MAX); 54 54 csr_write(CSR_STIMECMPH, next_tval >> 32); 55 + csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF); 55 56 #else 56 57 csr_write(CSR_STIMECMP, next_tval); 57 58 #endif

drivers/soc/renesas/Kconfig

··· 445 445 depends on RISCV_SBI 446 446 select ARCH_RZG2L 447 447 select AX45MP_L2_CACHE 448 + select CACHEMAINT_FOR_DMA 448 449 select DMA_GLOBAL_POOL 449 450 select ERRATA_ANDES 450 451 select ERRATA_ANDES_CMO

Configure Feed

Configure Feed