PM6125 regulator support · tjh.dev/kernel@d927029

+15 -11

Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml

··· 24 24 25 25 For mp5496, s2 26 26 27 + For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, 28 + l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22 29 + 30 + For pm6125 s1, s2, s3, s4, s5, s6, s7, s8, l1, l2, l3, l5, l6, l7, l8, l9, 31 + l10, l22, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24 32 + 33 + For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22, 34 + l12, l13, l14, l15, l16, l17, l18, l19 35 + 36 + For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob 37 + 27 38 For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, 28 39 l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, 29 40 l26, l27, l28, lvs1 ··· 63 52 l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, 64 53 l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1, lvs2 65 54 66 - For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22, 67 - l12, l13, l14, l15, l16, l17, l18, l19 68 - 69 - For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob 70 - 71 55 For pma8084, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, 72 56 l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, 73 57 l20, l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1 ··· 74 68 For pms405, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, 75 69 l12, l13 76 70 77 - For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, 78 - l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22 79 - 80 71 maintainers: 81 72 - Andy Gross <agross@kernel.org> 82 73 - Bjorn Andersson <bjorn.andersson@linaro.org> ··· 82 79 compatible: 83 80 enum: 84 81 - qcom,rpm-mp5496-regulators 82 + - qcom,rpm-pm2250-regulators 83 + - qcom,rpm-pm6125-regulators 84 + - qcom,rpm-pm660-regulators 85 + - qcom,rpm-pm660l-regulators 85 86 - qcom,rpm-pm8226-regulators 86 87 - qcom,rpm-pm8841-regulators 87 88 - qcom,rpm-pm8909-regulators ··· 95 88 - qcom,rpm-pm8953-regulators 96 89 - qcom,rpm-pm8994-regulators 97 90 - qcom,rpm-pm8998-regulators 98 - - qcom,rpm-pm660-regulators 99 - - qcom,rpm-pm660l-regulators 100 91 - qcom,rpm-pma8084-regulators 101 92 - qcom,rpm-pmi8994-regulators 102 93 - qcom,rpm-pmi8998-regulators 103 94 - qcom,rpm-pms405-regulators 104 - - qcom,rpm-pm2250-regulators 105 95 106 96 patternProperties: 107 97 ".*-supply$":

+32

Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.yaml

··· 12 12 properties: 13 13 compatible: 14 14 enum: 15 + - qcom,pm6125-regulators 15 16 - qcom,pm660-regulators 16 17 - qcom,pm660l-regulators 17 18 - qcom,pm8004-regulators ··· 113 112 compatible: 114 113 contains: 115 114 enum: 115 + - qcom,pm6125-regulators 116 + then: 117 + properties: 118 + vdd_l1_l7_l17_l18-supply: true 119 + vdd_l2_l3_l4-supply: true 120 + vdd_l5_l15_l19_l20_l21_l22-supply: true 121 + vdd_l6_l8-supply: true 122 + vdd_l9_l11-supply: true 123 + vdd_l10_l13_l14-supply: true 124 + vdd_l12_l16-supply: true 125 + vdd_l23_l24-supply: true 126 + patternProperties: 127 + "^vdd_s[1-8]-supply$": true 128 + 129 + - if: 130 + properties: 131 + compatible: 132 + contains: 133 + enum: 116 134 - qcom,pm660-regulators 117 135 then: 118 136 properties: ··· 142 122 vdd_l8_l9_l10_l11_l12_l13_l14-supply: true 143 123 patternProperties: 144 124 "^vdd_s[1-6]-supply$": true 125 + 145 126 - if: 146 127 properties: 147 128 compatible: ··· 157 136 vdd_l4_l6-supply: true 158 137 patternProperties: 159 138 "^vdd_s[1-5]-supply$": true 139 + 160 140 - if: 161 141 properties: 162 142 compatible: ··· 167 145 then: 168 146 patternProperties: 169 147 "^vdd_s[25]-supply$": true 148 + 170 149 - if: 171 150 properties: 172 151 compatible: ··· 177 154 then: 178 155 patternProperties: 179 156 "^vdd_s[1-4]-supply$": true 157 + 180 158 - if: 181 159 properties: 182 160 compatible: ··· 197 173 vdd_lvs1-supply: true 198 174 patternProperties: 199 175 "^vdd_s[1-5]-supply$": true 176 + 200 177 - if: 201 178 properties: 202 179 compatible: ··· 207 182 then: 208 183 patternProperties: 209 184 "^vdd_s[1-8]-supply$": true 185 + 210 186 - if: 211 187 properties: 212 188 compatible: ··· 223 197 patternProperties: 224 198 "^vdd_l[27]-supply$": true 225 199 "^vdd_s[1-4]-supply$": true 200 + 226 201 - if: 227 202 properties: 228 203 compatible: ··· 252 225 vin_5vs-supply: true 253 226 patternProperties: 254 227 "^vdd_s[1-3]-supply$": true 228 + 255 229 - if: 256 230 properties: 257 231 compatible: ··· 271 243 vdd_l9_l10_l13_l14_l15_l18-supply: true 272 244 patternProperties: 273 245 "^vdd_s[1-6]-supply$": true 246 + 274 247 - if: 275 248 properties: 276 249 compatible: ··· 296 267 vdd_lvs_1_2-supply: true 297 268 patternProperties: 298 269 "^vdd_s[1-9][0-2]?-supply$": true 270 + 299 271 - if: 300 272 properties: 301 273 compatible: ··· 308 278 vdd_l1-supply: true 309 279 patternProperties: 310 280 "^vdd_s[1-3]-supply$": true 281 + 311 282 - if: 312 283 properties: 313 284 compatible: ··· 324 293 patternProperties: 325 294 "^vdd_l[479]-supply$": true 326 295 "^vdd_s[1-5]-supply$": true 296 + 327 297 - if: 328 298 properties: 329 299 compatible:

+223 -177

drivers/regulator/qcom_smd-regulator.c

··· 668 668 .ops = &rpm_bob_ops, 669 669 }; 670 670 671 + static const struct regulator_desc pm6125_ftsmps = { 672 + .linear_ranges = (struct linear_range[]) { 673 + REGULATOR_LINEAR_RANGE(300000, 0, 268, 4000), 674 + }, 675 + .n_linear_ranges = 1, 676 + .n_voltages = 269, 677 + .ops = &rpm_smps_ldo_ops, 678 + }; 679 + 671 680 static const struct regulator_desc pms405_hfsmps3 = { 672 681 .linear_ranges = (struct linear_range[]) { 673 682 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), ··· 781 772 {} 782 773 }; 783 774 775 + static const struct rpm_regulator_data rpm_pm2250_regulators[] = { 776 + { "s1", QCOM_SMD_RPM_SMPA, 1, &pm2250_lvftsmps, "vdd_s1" }, 777 + { "s2", QCOM_SMD_RPM_SMPA, 2, &pm2250_lvftsmps, "vdd_s2" }, 778 + { "s3", QCOM_SMD_RPM_SMPA, 3, &pm2250_lvftsmps, "vdd_s3" }, 779 + { "s4", QCOM_SMD_RPM_SMPA, 4, &pm2250_ftsmps, "vdd_s4" }, 780 + { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 781 + { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 782 + { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 783 + { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 784 + { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 785 + { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 786 + { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 787 + { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 788 + { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 789 + { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 790 + { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 791 + { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 792 + { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" }, 793 + { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" }, 794 + { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" }, 795 + { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" }, 796 + { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 797 + { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 798 + { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 799 + { "l20", QCOM_SMD_RPM_LDOA, 20, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 800 + { "l21", QCOM_SMD_RPM_LDOA, 21, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 801 + { "l22", QCOM_SMD_RPM_LDOA, 22, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 802 + {} 803 + }; 804 + 805 + static const struct rpm_regulator_data rpm_pm6125_regulators[] = { 806 + { "s1", QCOM_SMD_RPM_SMPA, 1, &pm6125_ftsmps, "vdd_s1" }, 807 + { "s2", QCOM_SMD_RPM_SMPA, 2, &pm6125_ftsmps, "vdd_s2" }, 808 + { "s3", QCOM_SMD_RPM_SMPA, 3, &pm6125_ftsmps, "vdd_s3" }, 809 + { "s4", QCOM_SMD_RPM_SMPA, 4, &pm6125_ftsmps, "vdd_s4" }, 810 + { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" }, 811 + { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_hfsmps, "vdd_s6" }, 812 + { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_hfsmps, "vdd_s7" }, 813 + { "s8", QCOM_SMD_RPM_SMPA, 8, &pm6125_ftsmps, "vdd_s8" }, 814 + { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l7_l17_l18" }, 815 + { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_nldo660, "vdd_l2_l3_l4" }, 816 + { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3_l4" }, 817 + { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_nldo660, "vdd_l2_l3_l4" }, 818 + { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" }, 819 + { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l6_l8" }, 820 + { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_nldo660, "vdd_l1_l7_l17_l18" }, 821 + { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l6_l8" }, 822 + { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l9_l11" }, 823 + { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l10_l13_l14" }, 824 + { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l9_l11" }, 825 + { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l12_l16" }, 826 + { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l10_l13_l14" }, 827 + { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l10_l13_l14" }, 828 + { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" }, 829 + { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_ht_lvpldo, "vdd_l12_l16" }, 830 + { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_nldo660, "vdd_l1_l7_l17_l18" }, 831 + { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_nldo660, "vdd_l1_l7_l17_l18" }, 832 + { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" }, 833 + { "l20", QCOM_SMD_RPM_LDOA, 20, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" }, 834 + { "l21", QCOM_SMD_RPM_LDOA, 21, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" }, 835 + { "l22", QCOM_SMD_RPM_LDOA, 22, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" }, 836 + { "l23", QCOM_SMD_RPM_LDOA, 23, &pm660_pldo660, "vdd_l23_l24" }, 837 + { "l24", QCOM_SMD_RPM_LDOA, 24, &pm660_pldo660, "vdd_l23_l24" }, 838 + { } 839 + }; 840 + 841 + static const struct rpm_regulator_data rpm_pm660_regulators[] = { 842 + { "s1", QCOM_SMD_RPM_SMPA, 1, &pm660_ftsmps, "vdd_s1" }, 843 + { "s2", QCOM_SMD_RPM_SMPA, 2, &pm660_ftsmps, "vdd_s2" }, 844 + { "s3", QCOM_SMD_RPM_SMPA, 3, &pm660_ftsmps, "vdd_s3" }, 845 + { "s4", QCOM_SMD_RPM_SMPA, 4, &pm660_hfsmps, "vdd_s4" }, 846 + { "s5", QCOM_SMD_RPM_SMPA, 5, &pm660_hfsmps, "vdd_s5" }, 847 + { "s6", QCOM_SMD_RPM_SMPA, 6, &pm660_hfsmps, "vdd_s6" }, 848 + { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l6_l7" }, 849 + { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_ht_nldo, "vdd_l2_l3" }, 850 + { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3" }, 851 + /* l4 is unaccessible on PM660 */ 852 + { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_ht_nldo, "vdd_l5" }, 853 + { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_ht_nldo, "vdd_l1_l6_l7" }, 854 + { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_ht_nldo, "vdd_l1_l6_l7" }, 855 + { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 856 + { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 857 + { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 858 + { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 859 + { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 860 + { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 861 + { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 862 + { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 863 + { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 864 + { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 865 + { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 866 + { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 867 + { } 868 + }; 869 + 870 + static const struct rpm_regulator_data rpm_pm660l_regulators[] = { 871 + { "s1", QCOM_SMD_RPM_SMPB, 1, &pm660_ftsmps, "vdd_s1" }, 872 + { "s2", QCOM_SMD_RPM_SMPB, 2, &pm660_ftsmps, "vdd_s2" }, 873 + { "s3", QCOM_SMD_RPM_RWCX, 0, &pm660_ftsmps, "vdd_s3_s4" }, 874 + { "s5", QCOM_SMD_RPM_RWMX, 0, &pm660_ftsmps, "vdd_s5" }, 875 + { "l1", QCOM_SMD_RPM_LDOB, 1, &pm660_nldo660, "vdd_l1_l9_l10" }, 876 + { "l2", QCOM_SMD_RPM_LDOB, 2, &pm660_pldo660, "vdd_l2" }, 877 + { "l3", QCOM_SMD_RPM_LDOB, 3, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 878 + { "l4", QCOM_SMD_RPM_LDOB, 4, &pm660_pldo660, "vdd_l4_l6" }, 879 + { "l5", QCOM_SMD_RPM_LDOB, 5, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 880 + { "l6", QCOM_SMD_RPM_LDOB, 6, &pm660_pldo660, "vdd_l4_l6" }, 881 + { "l7", QCOM_SMD_RPM_LDOB, 7, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 882 + { "l8", QCOM_SMD_RPM_LDOB, 8, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 883 + { "l9", QCOM_SMD_RPM_RWLC, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" }, 884 + { "l10", QCOM_SMD_RPM_RWLM, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" }, 885 + { "bob", QCOM_SMD_RPM_BOBB, 1, &pm660l_bob, "vdd_bob", }, 886 + { } 887 + }; 888 + 889 + static const struct rpm_regulator_data rpm_pm8226_regulators[] = { 890 + { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8226_hfsmps, "vdd_s1" }, 891 + { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8226_ftsmps, "vdd_s2" }, 892 + { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8226_hfsmps, "vdd_s3" }, 893 + { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8226_hfsmps, "vdd_s4" }, 894 + { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8226_hfsmps, "vdd_s5" }, 895 + { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8226_nldo, "vdd_l1_l2_l4_l5" }, 896 + { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8226_nldo, "vdd_l1_l2_l4_l5" }, 897 + { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8226_nldo, "vdd_l3_l24_l26" }, 898 + { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8226_nldo, "vdd_l1_l2_l4_l5" }, 899 + { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_nldo, "vdd_l1_l2_l4_l5" }, 900 + { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" }, 901 + { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" }, 902 + { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" }, 903 + { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" }, 904 + { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8226_pldo, "vdd_l10_l11_l13" }, 905 + { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8226_pldo, "vdd_l10_l11_l13" }, 906 + { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8226_pldo, "vdd_l12_l14" }, 907 + { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8226_pldo, "vdd_l10_l11_l13" }, 908 + { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8226_pldo, "vdd_l12_l14" }, 909 + { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8226_pldo, "vdd_l15_l16_l17_l18" }, 910 + { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8226_pldo, "vdd_l15_l16_l17_l18" }, 911 + { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8226_pldo, "vdd_l15_l16_l17_l18" }, 912 + { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8226_pldo, "vdd_l15_l16_l17_l18" }, 913 + { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 914 + { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 915 + { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 916 + { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 917 + { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 918 + { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8226_nldo, "vdd_l3_l24_l26" }, 919 + { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8226_pldo, "vdd_l25" }, 920 + { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8226_nldo, "vdd_l3_l24_l26" }, 921 + { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" }, 922 + { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 923 + { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8226_switch, "vdd_lvs1" }, 924 + {} 925 + }; 926 + 784 927 static const struct rpm_regulator_data rpm_pm8841_regulators[] = { 785 928 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" }, 786 929 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" }, ··· 994 833 {} 995 834 }; 996 835 997 - static const struct rpm_regulator_data rpm_pm8226_regulators[] = { 998 - { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8226_hfsmps, "vdd_s1" }, 999 - { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8226_ftsmps, "vdd_s2" }, 1000 - { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8226_hfsmps, "vdd_s3" }, 1001 - { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8226_hfsmps, "vdd_s4" }, 1002 - { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8226_hfsmps, "vdd_s5" }, 1003 - { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8226_nldo, "vdd_l1_l2_l4_l5" }, 1004 - { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8226_nldo, "vdd_l1_l2_l4_l5" }, 1005 - { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8226_nldo, "vdd_l3_l24_l26" }, 1006 - { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8226_nldo, "vdd_l1_l2_l4_l5" }, 1007 - { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_nldo, "vdd_l1_l2_l4_l5" }, 1008 - { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" }, 1009 - { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" }, 1010 - { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" }, 1011 - { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" }, 1012 - { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8226_pldo, "vdd_l10_l11_l13" }, 1013 - { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8226_pldo, "vdd_l10_l11_l13" }, 1014 - { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8226_pldo, "vdd_l12_l14" }, 1015 - { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8226_pldo, "vdd_l10_l11_l13" }, 1016 - { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8226_pldo, "vdd_l12_l14" }, 1017 - { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8226_pldo, "vdd_l15_l16_l17_l18" }, 1018 - { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8226_pldo, "vdd_l15_l16_l17_l18" }, 1019 - { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8226_pldo, "vdd_l15_l16_l17_l18" }, 1020 - { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8226_pldo, "vdd_l15_l16_l17_l18" }, 1021 - { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 1022 - { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 1023 - { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 1024 - { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 1025 - { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 1026 - { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8226_nldo, "vdd_l3_l24_l26" }, 1027 - { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8226_pldo, "vdd_l25" }, 1028 - { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8226_nldo, "vdd_l3_l24_l26" }, 1029 - { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" }, 1030 - { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" }, 1031 - { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8226_switch, "vdd_lvs1" }, 1032 - {} 1033 - }; 1034 - 1035 836 static const struct rpm_regulator_data rpm_pm8941_regulators[] = { 1036 837 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" }, 1037 838 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" }, ··· 1031 908 1032 909 { "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" }, 1033 910 { "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" }, 1034 - 1035 - {} 1036 - }; 1037 - 1038 - static const struct rpm_regulator_data rpm_pma8084_regulators[] = { 1039 - { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" }, 1040 - { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" }, 1041 - { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" }, 1042 - { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" }, 1043 - { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" }, 1044 - { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" }, 1045 - { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" }, 1046 - { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" }, 1047 - { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" }, 1048 - { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" }, 1049 - { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" }, 1050 - { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" }, 1051 - 1052 - { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" }, 1053 - { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 1054 - { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 1055 - { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 1056 - { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" }, 1057 - { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 1058 - { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" }, 1059 - { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" }, 1060 - { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1061 - { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1062 - { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" }, 1063 - { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 1064 - { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1065 - { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 1066 - { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 1067 - { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" }, 1068 - { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" }, 1069 - { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" }, 1070 - { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" }, 1071 - { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1072 - { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" }, 1073 - { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" }, 1074 - { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1075 - { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1076 - { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" }, 1077 - { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 1078 - { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 1079 - 1080 - { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch }, 1081 - { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch }, 1082 - { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch }, 1083 - { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch }, 1084 - { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch }, 1085 911 1086 912 {} 1087 913 }; ··· 1154 1082 {} 1155 1083 }; 1156 1084 1157 - static const struct rpm_regulator_data rpm_pmi8994_regulators[] = { 1158 - { "s1", QCOM_SMD_RPM_SMPB, 1, &pmi8994_ftsmps, "vdd_s1" }, 1159 - { "s2", QCOM_SMD_RPM_SMPB, 2, &pmi8994_hfsmps, "vdd_s2" }, 1160 - { "s3", QCOM_SMD_RPM_SMPB, 3, &pmi8994_hfsmps, "vdd_s3" }, 1161 - { "boost-bypass", QCOM_SMD_RPM_BBYB, 1, &pmi8994_bby, "vdd_bst_byp" }, 1162 - {} 1163 - }; 1164 - 1165 1085 static const struct rpm_regulator_data rpm_pm8998_regulators[] = { 1166 1086 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" }, 1167 1087 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" }, ··· 1201 1137 {} 1202 1138 }; 1203 1139 1204 - static const struct rpm_regulator_data rpm_pmi8998_regulators[] = { 1205 - { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" }, 1140 + static const struct rpm_regulator_data rpm_pma8084_regulators[] = { 1141 + { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" }, 1142 + { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" }, 1143 + { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" }, 1144 + { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" }, 1145 + { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" }, 1146 + { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" }, 1147 + { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" }, 1148 + { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" }, 1149 + { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" }, 1150 + { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" }, 1151 + { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" }, 1152 + { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" }, 1153 + 1154 + { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" }, 1155 + { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 1156 + { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 1157 + { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 1158 + { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" }, 1159 + { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 1160 + { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" }, 1161 + { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" }, 1162 + { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1163 + { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1164 + { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" }, 1165 + { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 1166 + { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1167 + { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 1168 + { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 1169 + { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" }, 1170 + { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" }, 1171 + { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" }, 1172 + { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" }, 1173 + { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1174 + { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" }, 1175 + { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" }, 1176 + { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1177 + { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 1178 + { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" }, 1179 + { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 1180 + { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 1181 + 1182 + { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch }, 1183 + { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch }, 1184 + { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch }, 1185 + { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch }, 1186 + { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch }, 1187 + 1206 1188 {} 1207 1189 }; 1208 1190 1209 - static const struct rpm_regulator_data rpm_pm660_regulators[] = { 1210 - { "s1", QCOM_SMD_RPM_SMPA, 1, &pm660_ftsmps, "vdd_s1" }, 1211 - { "s2", QCOM_SMD_RPM_SMPA, 2, &pm660_ftsmps, "vdd_s2" }, 1212 - { "s3", QCOM_SMD_RPM_SMPA, 3, &pm660_ftsmps, "vdd_s3" }, 1213 - { "s4", QCOM_SMD_RPM_SMPA, 4, &pm660_hfsmps, "vdd_s4" }, 1214 - { "s5", QCOM_SMD_RPM_SMPA, 5, &pm660_hfsmps, "vdd_s5" }, 1215 - { "s6", QCOM_SMD_RPM_SMPA, 6, &pm660_hfsmps, "vdd_s6" }, 1216 - { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l6_l7" }, 1217 - { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_ht_nldo, "vdd_l2_l3" }, 1218 - { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3" }, 1219 - /* l4 is unaccessible on PM660 */ 1220 - { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_ht_nldo, "vdd_l5" }, 1221 - { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_ht_nldo, "vdd_l1_l6_l7" }, 1222 - { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_ht_nldo, "vdd_l1_l6_l7" }, 1223 - { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1224 - { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1225 - { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1226 - { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1227 - { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1228 - { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1229 - { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1230 - { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 1231 - { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 1232 - { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 1233 - { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 1234 - { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 1235 - { } 1191 + static const struct rpm_regulator_data rpm_pmi8994_regulators[] = { 1192 + { "s1", QCOM_SMD_RPM_SMPB, 1, &pmi8994_ftsmps, "vdd_s1" }, 1193 + { "s2", QCOM_SMD_RPM_SMPB, 2, &pmi8994_hfsmps, "vdd_s2" }, 1194 + { "s3", QCOM_SMD_RPM_SMPB, 3, &pmi8994_hfsmps, "vdd_s3" }, 1195 + { "boost-bypass", QCOM_SMD_RPM_BBYB, 1, &pmi8994_bby, "vdd_bst_byp" }, 1196 + {} 1236 1197 }; 1237 1198 1238 - static const struct rpm_regulator_data rpm_pm660l_regulators[] = { 1239 - { "s1", QCOM_SMD_RPM_SMPB, 1, &pm660_ftsmps, "vdd_s1" }, 1240 - { "s2", QCOM_SMD_RPM_SMPB, 2, &pm660_ftsmps, "vdd_s2" }, 1241 - { "s3", QCOM_SMD_RPM_RWCX, 0, &pm660_ftsmps, "vdd_s3_s4" }, 1242 - { "s5", QCOM_SMD_RPM_RWMX, 0, &pm660_ftsmps, "vdd_s5" }, 1243 - { "l1", QCOM_SMD_RPM_LDOB, 1, &pm660_nldo660, "vdd_l1_l9_l10" }, 1244 - { "l2", QCOM_SMD_RPM_LDOB, 2, &pm660_pldo660, "vdd_l2" }, 1245 - { "l3", QCOM_SMD_RPM_LDOB, 3, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 1246 - { "l4", QCOM_SMD_RPM_LDOB, 4, &pm660_pldo660, "vdd_l4_l6" }, 1247 - { "l5", QCOM_SMD_RPM_LDOB, 5, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 1248 - { "l6", QCOM_SMD_RPM_LDOB, 6, &pm660_pldo660, "vdd_l4_l6" }, 1249 - { "l7", QCOM_SMD_RPM_LDOB, 7, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 1250 - { "l8", QCOM_SMD_RPM_LDOB, 8, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 1251 - { "l9", QCOM_SMD_RPM_RWLC, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" }, 1252 - { "l10", QCOM_SMD_RPM_RWLM, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" }, 1253 - { "bob", QCOM_SMD_RPM_BOBB, 1, &pm660l_bob, "vdd_bob", }, 1254 - { } 1199 + static const struct rpm_regulator_data rpm_pmi8998_regulators[] = { 1200 + { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" }, 1201 + {} 1255 1202 }; 1256 1203 1257 1204 static const struct rpm_regulator_data rpm_pms405_regulators[] = { ··· 1287 1212 {} 1288 1213 }; 1289 1214 1290 - static const struct rpm_regulator_data rpm_pm2250_regulators[] = { 1291 - { "s1", QCOM_SMD_RPM_SMPA, 1, &pm2250_lvftsmps, "vdd_s1" }, 1292 - { "s2", QCOM_SMD_RPM_SMPA, 2, &pm2250_lvftsmps, "vdd_s2" }, 1293 - { "s3", QCOM_SMD_RPM_SMPA, 3, &pm2250_lvftsmps, "vdd_s3" }, 1294 - { "s4", QCOM_SMD_RPM_SMPA, 4, &pm2250_ftsmps, "vdd_s4" }, 1295 - { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 1296 - { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 1297 - { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 1298 - { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 1299 - { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 1300 - { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 1301 - { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 1302 - { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 1303 - { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 1304 - { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 1305 - { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 1306 - { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" }, 1307 - { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" }, 1308 - { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" }, 1309 - { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" }, 1310 - { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" }, 1311 - { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 1312 - { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 1313 - { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 1314 - { "l20", QCOM_SMD_RPM_LDOA, 20, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 1315 - { "l21", QCOM_SMD_RPM_LDOA, 21, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 1316 - { "l22", QCOM_SMD_RPM_LDOA, 22, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" }, 1317 - {} 1318 - }; 1319 - 1320 1215 static const struct of_device_id rpm_of_match[] = { 1321 1216 { .compatible = "qcom,rpm-mp5496-regulators", .data = &rpm_mp5496_regulators }, 1217 + { .compatible = "qcom,rpm-pm2250-regulators", .data = &rpm_pm2250_regulators }, 1218 + { .compatible = "qcom,rpm-pm6125-regulators", .data = &rpm_pm6125_regulators }, 1219 + { .compatible = "qcom,rpm-pm660-regulators", .data = &rpm_pm660_regulators }, 1220 + { .compatible = "qcom,rpm-pm660l-regulators", .data = &rpm_pm660l_regulators }, 1221 + { .compatible = "qcom,rpm-pm8226-regulators", .data = &rpm_pm8226_regulators }, 1322 1222 { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators }, 1323 1223 { .compatible = "qcom,rpm-pm8909-regulators", .data = &rpm_pm8909_regulators }, 1324 1224 { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators }, 1325 - { .compatible = "qcom,rpm-pm8226-regulators", .data = &rpm_pm8226_regulators }, 1326 1225 { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators }, 1327 1226 { .compatible = "qcom,rpm-pm8950-regulators", .data = &rpm_pm8950_regulators }, 1328 1227 { .compatible = "qcom,rpm-pm8953-regulators", .data = &rpm_pm8953_regulators }, 1329 1228 { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators }, 1330 1229 { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators }, 1331 - { .compatible = "qcom,rpm-pm660-regulators", .data = &rpm_pm660_regulators }, 1332 - { .compatible = "qcom,rpm-pm660l-regulators", .data = &rpm_pm660l_regulators }, 1333 1230 { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators }, 1334 1231 { .compatible = "qcom,rpm-pmi8994-regulators", .data = &rpm_pmi8994_regulators }, 1335 1232 { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators }, 1336 1233 { .compatible = "qcom,rpm-pms405-regulators", .data = &rpm_pms405_regulators }, 1337 - { .compatible = "qcom,rpm-pm2250-regulators", .data = &rpm_pm2250_regulators }, 1338 1234 {} 1339 1235 }; 1340 1236 MODULE_DEVICE_TABLE(of, rpm_of_match);

+281 -97

drivers/regulator/qcom_spmi-regulator.c

··· 99 99 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO, 100 100 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426, 101 101 SPMI_REGULATOR_LOGICAL_TYPE_HFS430, 102 + SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3, 103 + SPMI_REGULATOR_LOGICAL_TYPE_LDO_510, 104 + SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS, 102 105 }; 103 106 104 107 enum spmi_regulator_type { ··· 169 166 SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, 170 167 SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35, 171 168 SPMI_REGULATOR_SUBTYPE_HT_P600 = 0x3d, 169 + SPMI_REGULATOR_SUBTYPE_HFSMPS_510 = 0x0a, 170 + SPMI_REGULATOR_SUBTYPE_FTSMPS_510 = 0x0b, 171 + SPMI_REGULATOR_SUBTYPE_LV_P150_510 = 0x71, 172 + SPMI_REGULATOR_SUBTYPE_LV_P300_510 = 0x72, 173 + SPMI_REGULATOR_SUBTYPE_LV_P600_510 = 0x73, 174 + SPMI_REGULATOR_SUBTYPE_N300_510 = 0x6a, 175 + SPMI_REGULATOR_SUBTYPE_N600_510 = 0x6b, 176 + SPMI_REGULATOR_SUBTYPE_N1200_510 = 0x6c, 177 + SPMI_REGULATOR_SUBTYPE_MV_P50_510 = 0x7a, 178 + SPMI_REGULATOR_SUBTYPE_MV_P150_510 = 0x7b, 179 + SPMI_REGULATOR_SUBTYPE_MV_P600_510 = 0x7d, 172 180 }; 173 181 174 182 enum spmi_common_regulator_registers { ··· 205 191 SPMI_FTSMPS426_REG_VOLTAGE_MSB = 0x41, 206 192 SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 0x68, 207 193 SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69, 194 + }; 195 + 196 + /* 197 + * Third common register layout 198 + */ 199 + enum spmi_hfsmps_regulator_registers { 200 + SPMI_HFSMPS_REG_STEP_CTRL = 0x3c, 201 + SPMI_HFSMPS_REG_PULL_DOWN = 0xa0, 208 202 }; 209 203 210 204 enum spmi_vs_registers { ··· 282 260 283 261 #define SPMI_FTSMPS426_MODE_MASK 0x07 284 262 263 + /* Third common regulator mode register values */ 264 + #define SPMI_HFSMPS_MODE_BYPASS_MASK 2 265 + #define SPMI_HFSMPS_MODE_RETENTION_MASK 3 266 + #define SPMI_HFSMPS_MODE_LPM_MASK 4 267 + #define SPMI_HFSMPS_MODE_AUTO_MASK 6 268 + #define SPMI_HFSMPS_MODE_HPM_MASK 7 269 + 270 + #define SPMI_HFSMPS_MODE_MASK 0x07 271 + 285 272 /* Common regulator pull down control register layout */ 286 273 #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80 287 274 ··· 335 304 */ 336 305 #define SPMI_FTSMPS_STEP_MARGIN_NUM 4 337 306 #define SPMI_FTSMPS_STEP_MARGIN_DEN 5 307 + 308 + /* slew_rate has units of uV/us. */ 309 + #define SPMI_HFSMPS_SLEW_RATE_38p4 38400 338 310 339 311 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03 340 312 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0 ··· 588 554 SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000), 589 555 }; 590 556 557 + static struct spmi_voltage_range nldo_510_ranges[] = { 558 + SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000), 559 + }; 560 + 561 + static struct spmi_voltage_range ftsmps510_ranges[] = { 562 + SPMI_VOLTAGE_RANGE(0, 300000, 300000, 1372000, 1372000, 4000), 563 + }; 564 + 591 565 static DEFINE_SPMI_SET_POINTS(pldo); 592 566 static DEFINE_SPMI_SET_POINTS(nldo1); 593 567 static DEFINE_SPMI_SET_POINTS(nldo2); ··· 618 576 static DEFINE_SPMI_SET_POINTS(hfs430); 619 577 static DEFINE_SPMI_SET_POINTS(ht_p150); 620 578 static DEFINE_SPMI_SET_POINTS(ht_p600); 579 + static DEFINE_SPMI_SET_POINTS(nldo_510); 580 + static DEFINE_SPMI_SET_POINTS(ftsmps510); 621 581 622 582 static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, 623 583 int len) ··· 1106 1062 } 1107 1063 } 1108 1064 1065 + static unsigned int spmi_regulator_hfsmps_get_mode(struct regulator_dev *rdev) 1066 + { 1067 + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1068 + u8 reg; 1069 + 1070 + spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &reg, 1); 1071 + 1072 + switch (reg) { 1073 + case SPMI_HFSMPS_MODE_HPM_MASK: 1074 + return REGULATOR_MODE_NORMAL; 1075 + case SPMI_HFSMPS_MODE_AUTO_MASK: 1076 + return REGULATOR_MODE_FAST; 1077 + default: 1078 + return REGULATOR_MODE_IDLE; 1079 + } 1080 + } 1081 + 1109 1082 static int 1110 1083 spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode) 1111 1084 { ··· 1170 1109 } 1171 1110 1172 1111 static int 1112 + spmi_regulator_hfsmps_set_mode(struct regulator_dev *rdev, unsigned int mode) 1113 + { 1114 + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1115 + u8 mask = SPMI_HFSMPS_MODE_MASK; 1116 + u8 val; 1117 + 1118 + switch (mode) { 1119 + case REGULATOR_MODE_NORMAL: 1120 + val = SPMI_HFSMPS_MODE_HPM_MASK; 1121 + break; 1122 + case REGULATOR_MODE_FAST: 1123 + val = SPMI_HFSMPS_MODE_AUTO_MASK; 1124 + break; 1125 + case REGULATOR_MODE_IDLE: 1126 + val = vreg->logical_type == 1127 + SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3 ? 1128 + SPMI_HFSMPS_MODE_RETENTION_MASK : 1129 + SPMI_HFSMPS_MODE_LPM_MASK; 1130 + break; 1131 + default: 1132 + return -EINVAL; 1133 + } 1134 + 1135 + return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); 1136 + } 1137 + 1138 + static int 1173 1139 spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA) 1174 1140 { 1175 1141 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); ··· 1216 1128 unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; 1217 1129 1218 1130 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN, 1131 + mask, mask); 1132 + } 1133 + 1134 + static int spmi_regulator_hfsmps_set_pull_down(struct regulator_dev *rdev) 1135 + { 1136 + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1137 + unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; 1138 + 1139 + return spmi_vreg_update_bits(vreg, SPMI_HFSMPS_REG_PULL_DOWN, 1219 1140 mask, mask); 1220 1141 } 1221 1142 ··· 1562 1465 .get_mode = spmi_regulator_ftsmps426_get_mode, 1563 1466 }; 1564 1467 1468 + static const struct regulator_ops spmi_hfsmps_ops = { 1469 + .enable = regulator_enable_regmap, 1470 + .disable = regulator_disable_regmap, 1471 + .is_enabled = regulator_is_enabled_regmap, 1472 + .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, 1473 + .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1474 + .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, 1475 + .map_voltage = spmi_regulator_single_map_voltage, 1476 + .list_voltage = spmi_regulator_common_list_voltage, 1477 + .set_mode = spmi_regulator_hfsmps_set_mode, 1478 + .get_mode = spmi_regulator_hfsmps_get_mode, 1479 + .set_load = spmi_regulator_common_set_load, 1480 + .set_pull_down = spmi_regulator_hfsmps_set_pull_down, 1481 + }; 1482 + 1565 1483 /* Maximum possible digital major revision value */ 1566 1484 #define INF 0xFF 1567 1485 ··· 1585 1473 SPMI_VREG(LDO, HT_P600, 0, INF, HFS430, hfs430, ht_p600, 10000), 1586 1474 SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000), 1587 1475 SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), 1588 - SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), 1476 + SPMI_VREG(BUCK, HFS430, 0, 3, HFS430, hfs430, hfs430, 10000), 1477 + SPMI_VREG(BUCK, HFSMPS_510, 4, INF, HFSMPS, hfsmps, hfs430, 100000), 1589 1478 SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), 1590 1479 SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000), 1591 1480 SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000), ··· 1662 1549 SPMI_VREG(ULT_LDO, P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1663 1550 SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1664 1551 SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000), 1552 + SPMI_VREG(LDO, LV_P150_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), 1553 + SPMI_VREG(LDO, LV_P300_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), 1554 + SPMI_VREG(LDO, LV_P600_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), 1555 + SPMI_VREG(LDO, MV_P50_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), 1556 + SPMI_VREG(LDO, MV_P150_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), 1557 + SPMI_VREG(LDO, MV_P600_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), 1558 + SPMI_VREG(LDO, N300_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), 1559 + SPMI_VREG(LDO, N600_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), 1560 + SPMI_VREG(LDO, N1200_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), 1561 + SPMI_VREG(FTS, FTSMPS_510, 0, INF, FTSMPS3, hfsmps, ftsmps510, 100000), 1665 1562 }; 1666 1563 1667 1564 static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points) ··· 1815 1692 1816 1693 /* Ensure that the slew rate is greater than 0 */ 1817 1694 vreg->slew_rate = max(slew_rate, 1); 1695 + 1696 + return ret; 1697 + } 1698 + 1699 + static int spmi_regulator_init_slew_rate_hfsmps(struct spmi_regulator *vreg) 1700 + { 1701 + int ret; 1702 + u8 reg = 0; 1703 + int delay; 1704 + 1705 + ret = spmi_vreg_read(vreg, SPMI_HFSMPS_REG_STEP_CTRL, &reg, 1); 1706 + if (ret) { 1707 + dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); 1708 + return ret; 1709 + } 1710 + 1711 + delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK; 1712 + delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT; 1713 + 1714 + vreg->slew_rate = SPMI_HFSMPS_SLEW_RATE_38p4 >> delay; 1818 1715 1819 1716 return ret; 1820 1717 } ··· 1989 1846 if (ret) 1990 1847 return ret; 1991 1848 break; 1849 + case SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS: 1850 + case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3: 1851 + ret = spmi_regulator_init_slew_rate_hfsmps(vreg); 1852 + if (ret) 1853 + return ret; 1854 + break; 1992 1855 default: 1993 1856 break; 1994 1857 } ··· 2021 1872 return 0; 2022 1873 } 2023 1874 2024 - static const struct spmi_regulator_data pm8941_regulators[] = { 1875 + static const struct spmi_regulator_data pm6125_regulators[] = { 1876 + { "s1", 0x1400, "vdd_s1" }, 1877 + { "s2", 0x1700, "vdd_s2" }, 1878 + { "s3", 0x1a00, "vdd_s3" }, 1879 + { "s4", 0x1d00, "vdd_s4" }, 1880 + { "s5", 0x2000, "vdd_s5" }, 1881 + { "s6", 0x2300, "vdd_s6" }, 1882 + { "s7", 0x2600, "vdd_s7" }, 1883 + { "s8", 0x2900, "vdd_s8" }, 1884 + { "l1", 0x4000, "vdd_l1_l7_l17_l18" }, 1885 + { "l2", 0x4100, "vdd_l2_l3_l4" }, 1886 + { "l3", 0x4200, "vdd_l2_l3_l4" }, 1887 + { "l4", 0x4300, "vdd_l2_l3_l4" }, 1888 + { "l5", 0x4400, "vdd_l5_l15_l19_l20_l21_l22" }, 1889 + { "l6", 0x4500, "vdd_l6_l8" }, 1890 + { "l7", 0x4600, "vdd_l1_l7_l17_l18" }, 1891 + { "l8", 0x4700, "vdd_l6_l8" }, 1892 + { "l9", 0x4800, "vdd_l9_l11" }, 1893 + { "l10", 0x4900, "vdd_l10_l13_l14" }, 1894 + { "l11", 0x4a00, "vdd_l9_l11" }, 1895 + { "l12", 0x4b00, "vdd_l12_l16" }, 1896 + { "l13", 0x4c00, "vdd_l10_l13_l14" }, 1897 + { "l14", 0x4d00, "vdd_l10_l13_l14" }, 1898 + { "l15", 0x4e00, "vdd_l5_l15_l19_l20_l21_l22" }, 1899 + { "l16", 0x4f00, "vdd_l12_l16" }, 1900 + { "l17", 0x5000, "vdd_l1_l7_l17_l18" }, 1901 + { "l18", 0x5100, "vdd_l1_l7_l17_l18" }, 1902 + { "l19", 0x5200, "vdd_l5_l15_l19_l20_l21_l22" }, 1903 + { "l20", 0x5300, "vdd_l5_l15_l19_l20_l21_l22" }, 1904 + { "l21", 0x5400, "vdd_l5_l15_l19_l20_l21_l22" }, 1905 + { "l22", 0x5500, "vdd_l5_l15_l19_l20_l21_l22" }, 1906 + { "l23", 0x5600, "vdd_l23_l24" }, 1907 + { "l24", 0x5700, "vdd_l23_l24" }, 1908 + }; 1909 + 1910 + static const struct spmi_regulator_data pm660_regulators[] = { 2025 1911 { "s1", 0x1400, "vdd_s1", }, 2026 1912 { "s2", 0x1700, "vdd_s2", }, 2027 1913 { "s3", 0x1a00, "vdd_s3", }, 2028 - { "s4", 0xa000, }, 2029 - { "l1", 0x4000, "vdd_l1_l3", }, 2030 - { "l2", 0x4100, "vdd_l2_lvs_1_2_3", }, 2031 - { "l3", 0x4200, "vdd_l1_l3", }, 2032 - { "l4", 0x4300, "vdd_l4_l11", }, 2033 - { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 }, 2034 - { "l6", 0x4500, "vdd_l6_l12_l14_l15", }, 2035 - { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 }, 2036 - { "l8", 0x4700, "vdd_l8_l16_l18_19", }, 2037 - { "l9", 0x4800, "vdd_l9_l10_l17_l22", }, 2038 - { "l10", 0x4900, "vdd_l9_l10_l17_l22", }, 2039 - { "l11", 0x4a00, "vdd_l4_l11", }, 2040 - { "l12", 0x4b00, "vdd_l6_l12_l14_l15", }, 2041 - { "l13", 0x4c00, "vdd_l13_l20_l23_l24", }, 2042 - { "l14", 0x4d00, "vdd_l6_l12_l14_l15", }, 2043 - { "l15", 0x4e00, "vdd_l6_l12_l14_l15", }, 2044 - { "l16", 0x4f00, "vdd_l8_l16_l18_19", }, 2045 - { "l17", 0x5000, "vdd_l9_l10_l17_l22", }, 2046 - { "l18", 0x5100, "vdd_l8_l16_l18_19", }, 2047 - { "l19", 0x5200, "vdd_l8_l16_l18_19", }, 2048 - { "l20", 0x5300, "vdd_l13_l20_l23_l24", }, 2049 - { "l21", 0x5400, "vdd_l21", }, 2050 - { "l22", 0x5500, "vdd_l9_l10_l17_l22", }, 2051 - { "l23", 0x5600, "vdd_l13_l20_l23_l24", }, 2052 - { "l24", 0x5700, "vdd_l13_l20_l23_l24", }, 2053 - { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", }, 2054 - { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", }, 2055 - { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", }, 2056 - { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", }, 2057 - { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", }, 1914 + { "s4", 0x1d00, "vdd_s3", }, 1915 + { "s5", 0x2000, "vdd_s5", }, 1916 + { "s6", 0x2300, "vdd_s6", }, 1917 + { "l1", 0x4000, "vdd_l1_l6_l7", }, 1918 + { "l2", 0x4100, "vdd_l2_l3", }, 1919 + { "l3", 0x4200, "vdd_l2_l3", }, 1920 + /* l4 is unaccessible on PM660 */ 1921 + { "l5", 0x4400, "vdd_l5", }, 1922 + { "l6", 0x4500, "vdd_l1_l6_l7", }, 1923 + { "l7", 0x4600, "vdd_l1_l6_l7", }, 1924 + { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 1925 + { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 1926 + { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 1927 + { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 1928 + { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 1929 + { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 1930 + { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 1931 + { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", }, 1932 + { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", }, 1933 + { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", }, 1934 + { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", }, 1935 + { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", }, 1936 + { } 1937 + }; 1938 + 1939 + static const struct spmi_regulator_data pm660l_regulators[] = { 1940 + { "s1", 0x1400, "vdd_s1", }, 1941 + { "s2", 0x1700, "vdd_s2", }, 1942 + { "s3", 0x1a00, "vdd_s3", }, 1943 + { "s4", 0x1d00, "vdd_s4", }, 1944 + { "s5", 0x2000, "vdd_s5", }, 1945 + { "l1", 0x4000, "vdd_l1_l9_l10", }, 1946 + { "l2", 0x4100, "vdd_l2", }, 1947 + { "l3", 0x4200, "vdd_l3_l5_l7_l8", }, 1948 + { "l4", 0x4300, "vdd_l4_l6", }, 1949 + { "l5", 0x4400, "vdd_l3_l5_l7_l8", }, 1950 + { "l6", 0x4500, "vdd_l4_l6", }, 1951 + { "l7", 0x4600, "vdd_l3_l5_l7_l8", }, 1952 + { "l8", 0x4700, "vdd_l3_l5_l7_l8", }, 1953 + { "l9", 0x4800, "vdd_l1_l9_l10", }, 1954 + { "l10", 0x4900, "vdd_l1_l9_l10", }, 1955 + { } 1956 + }; 1957 + 1958 + static const struct spmi_regulator_data pm8004_regulators[] = { 1959 + { "s2", 0x1700, "vdd_s2", }, 1960 + { "s5", 0x2000, "vdd_s5", }, 1961 + { } 1962 + }; 1963 + 1964 + static const struct spmi_regulator_data pm8005_regulators[] = { 1965 + { "s1", 0x1400, "vdd_s1", }, 1966 + { "s2", 0x1700, "vdd_s2", }, 1967 + { "s3", 0x1a00, "vdd_s3", }, 1968 + { "s4", 0x1d00, "vdd_s4", }, 2058 1969 { } 2059 1970 }; 2060 1971 ··· 2191 1982 { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", }, 2192 1983 { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", }, 2193 1984 { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", }, 1985 + { } 1986 + }; 1987 + 1988 + static const struct spmi_regulator_data pm8941_regulators[] = { 1989 + { "s1", 0x1400, "vdd_s1", }, 1990 + { "s2", 0x1700, "vdd_s2", }, 1991 + { "s3", 0x1a00, "vdd_s3", }, 1992 + { "s4", 0xa000, }, 1993 + { "l1", 0x4000, "vdd_l1_l3", }, 1994 + { "l2", 0x4100, "vdd_l2_lvs_1_2_3", }, 1995 + { "l3", 0x4200, "vdd_l1_l3", }, 1996 + { "l4", 0x4300, "vdd_l4_l11", }, 1997 + { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 }, 1998 + { "l6", 0x4500, "vdd_l6_l12_l14_l15", }, 1999 + { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 }, 2000 + { "l8", 0x4700, "vdd_l8_l16_l18_19", }, 2001 + { "l9", 0x4800, "vdd_l9_l10_l17_l22", }, 2002 + { "l10", 0x4900, "vdd_l9_l10_l17_l22", }, 2003 + { "l11", 0x4a00, "vdd_l4_l11", }, 2004 + { "l12", 0x4b00, "vdd_l6_l12_l14_l15", }, 2005 + { "l13", 0x4c00, "vdd_l13_l20_l23_l24", }, 2006 + { "l14", 0x4d00, "vdd_l6_l12_l14_l15", }, 2007 + { "l15", 0x4e00, "vdd_l6_l12_l14_l15", }, 2008 + { "l16", 0x4f00, "vdd_l8_l16_l18_19", }, 2009 + { "l17", 0x5000, "vdd_l9_l10_l17_l22", }, 2010 + { "l18", 0x5100, "vdd_l8_l16_l18_19", }, 2011 + { "l19", 0x5200, "vdd_l8_l16_l18_19", }, 2012 + { "l20", 0x5300, "vdd_l13_l20_l23_l24", }, 2013 + { "l21", 0x5400, "vdd_l21", }, 2014 + { "l22", 0x5500, "vdd_l9_l10_l17_l22", }, 2015 + { "l23", 0x5600, "vdd_l13_l20_l23_l24", }, 2016 + { "l24", 0x5700, "vdd_l13_l20_l23_l24", }, 2017 + { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", }, 2018 + { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", }, 2019 + { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", }, 2020 + { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", }, 2021 + { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", }, 2194 2022 { } 2195 2023 }; 2196 2024 ··· 2322 2076 { } 2323 2077 }; 2324 2078 2325 - static const struct spmi_regulator_data pm660_regulators[] = { 2326 - { "s1", 0x1400, "vdd_s1", }, 2327 - { "s2", 0x1700, "vdd_s2", }, 2328 - { "s3", 0x1a00, "vdd_s3", }, 2329 - { "s4", 0x1d00, "vdd_s3", }, 2330 - { "s5", 0x2000, "vdd_s5", }, 2331 - { "s6", 0x2300, "vdd_s6", }, 2332 - { "l1", 0x4000, "vdd_l1_l6_l7", }, 2333 - { "l2", 0x4100, "vdd_l2_l3", }, 2334 - { "l3", 0x4200, "vdd_l2_l3", }, 2335 - /* l4 is unaccessible on PM660 */ 2336 - { "l5", 0x4400, "vdd_l5", }, 2337 - { "l6", 0x4500, "vdd_l1_l6_l7", }, 2338 - { "l7", 0x4600, "vdd_l1_l6_l7", }, 2339 - { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2340 - { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2341 - { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2342 - { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2343 - { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2344 - { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2345 - { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2346 - { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", }, 2347 - { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", }, 2348 - { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", }, 2349 - { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", }, 2350 - { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", }, 2351 - { } 2352 - }; 2353 - 2354 - static const struct spmi_regulator_data pm660l_regulators[] = { 2355 - { "s1", 0x1400, "vdd_s1", }, 2356 - { "s2", 0x1700, "vdd_s2", }, 2357 - { "s3", 0x1a00, "vdd_s3", }, 2358 - { "s4", 0x1d00, "vdd_s4", }, 2359 - { "s5", 0x2000, "vdd_s5", }, 2360 - { "l1", 0x4000, "vdd_l1_l9_l10", }, 2361 - { "l2", 0x4100, "vdd_l2", }, 2362 - { "l3", 0x4200, "vdd_l3_l5_l7_l8", }, 2363 - { "l4", 0x4300, "vdd_l4_l6", }, 2364 - { "l5", 0x4400, "vdd_l3_l5_l7_l8", }, 2365 - { "l6", 0x4500, "vdd_l4_l6", }, 2366 - { "l7", 0x4600, "vdd_l3_l5_l7_l8", }, 2367 - { "l8", 0x4700, "vdd_l3_l5_l7_l8", }, 2368 - { "l9", 0x4800, "vdd_l1_l9_l10", }, 2369 - { "l10", 0x4900, "vdd_l1_l9_l10", }, 2370 - { } 2371 - }; 2372 - 2373 - 2374 - static const struct spmi_regulator_data pm8004_regulators[] = { 2375 - { "s2", 0x1700, "vdd_s2", }, 2376 - { "s5", 0x2000, "vdd_s5", }, 2377 - { } 2378 - }; 2379 - 2380 - static const struct spmi_regulator_data pm8005_regulators[] = { 2381 - { "s1", 0x1400, "vdd_s1", }, 2382 - { "s2", 0x1700, "vdd_s2", }, 2383 - { "s3", 0x1a00, "vdd_s3", }, 2384 - { "s4", 0x1d00, "vdd_s4", }, 2385 - { } 2386 - }; 2387 - 2388 2079 static const struct spmi_regulator_data pmp8074_regulators[] = { 2389 2080 { "s1", 0x1400, "vdd_s1"}, 2390 2081 { "s2", 0x1700, "vdd_s2"}, ··· 2350 2167 }; 2351 2168 2352 2169 static const struct of_device_id qcom_spmi_regulator_match[] = { 2170 + { .compatible = "qcom,pm6125-regulators", .data = &pm6125_regulators }, 2171 + { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, 2172 + { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, 2353 2173 { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators }, 2354 2174 { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, 2355 2175 { .compatible = "qcom,pm8226-regulators", .data = &pm8226_regulators }, ··· 2362 2176 { .compatible = "qcom,pm8950-regulators", .data = &pm8950_regulators }, 2363 2177 { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators }, 2364 2178 { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, 2365 - { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, 2366 - { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, 2367 2179 { .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators }, 2368 2180 { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, 2369 2181 { }

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