Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch kvm-arm64/gic-v5-nv into kvmarm-master/next
* kvm-arm64/gic-v5-nv:
: .
: Add NV support to GICv5 in GICv3 emulation mode, ensuring that the v3
: guest support is identical to that of a pure v3 platform.
:
: Patches courtesy of Sascha Bischoff (20250828105925.3865158-1-sascha.bischoff@arm.com)
: .
irqchip/gic-v5: Drop has_gcie_v3_compat from gic_kvm_info
KVM: arm64: Use ARM64_HAS_GICV5_LEGACY for GICv5 probing
arm64: cpucaps: Add GICv5 Legacy vCPU interface (GCIE_LEGACY) capability
KVM: arm64: Enable nested for GICv5 host with FEAT_GCIE_LEGACY
KVM: arm64: Don't access ICC_SRE_EL2 if GICv3 doesn't support v2 compatibility
Signed-off-by: Marc Zyngier <maz@kernel.org>
+41
-28
+15
arch/arm64/kernel/cpufeature.c
+15
arch/arm64/kernel/cpufeature.c
···
2539
2539
return idr & MPAMIDR_EL1_HAS_HCR;
2540
2540
}
2541
2541
2542
+
static bool
2543
+
test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope)
2544
+
{
2545
+
if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF))
2546
+
return false;
2547
+
2548
+
return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY);
2549
+
}
2550
+
2542
2551
static const struct arm64_cpu_capabilities arm64_features[] = {
2543
2552
{
2544
2553
.capability = ARM64_ALWAYS_BOOT,
···
3164
3155
.capability = ARM64_HAS_GICV5_CPUIF,
3165
3156
.matches = has_cpuid_feature,
3166
3157
ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP)
3158
+
},
3159
+
{
3160
+
.desc = "GICv5 Legacy vCPU interface",
3161
+
.type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE,
3162
+
.capability = ARM64_HAS_GICV5_LEGACY,
3163
+
.matches = test_has_gicv5_legacy,
3167
3164
},
3168
3165
{},
3169
3166
};
+3
arch/arm64/kernel/image-vars.h
+3
arch/arm64/kernel/image-vars.h
···
105
105
KVM_NVHE_ALIAS(vgic_v2_cpuif_trap);
106
106
KVM_NVHE_ALIAS(vgic_v3_cpuif_trap);
107
107
108
+
/* Static key indicating whether GICv3 has GICv2 compatibility */
109
+
KVM_NVHE_ALIAS(vgic_v3_has_v2_compat);
110
+
108
111
/* Static key which is set if CNTVOFF_EL2 is unusable */
109
112
KVM_NVHE_ALIAS(broken_cntvoff_key);
110
113
+3
-2
arch/arm64/kvm/arm.c
+3
-2
arch/arm64/kvm/arm.c
···
2321
2321
}
2322
2322
2323
2323
if (kvm_mode == KVM_MODE_NV &&
2324
-
!(vgic_present && kvm_vgic_global_state.type == VGIC_V3)) {
2325
-
kvm_err("NV support requires GICv3, giving up\n");
2324
+
!(vgic_present && (kvm_vgic_global_state.type == VGIC_V3 ||
2325
+
kvm_vgic_global_state.has_gcie_v3_compat))) {
2326
+
kvm_err("NV support requires GICv3 or GICv5 with legacy support, giving up\n");
2326
2327
err = -EINVAL;
2327
2328
goto out;
2328
2329
}
+9
-16
arch/arm64/kvm/hyp/vgic-v3-sr.c
+9
-16
arch/arm64/kvm/hyp/vgic-v3-sr.c
···
295
295
}
296
296
}
297
297
298
-
/*
299
-
* GICv5 BET0 FEAT_GCIE_LEGACY doesn't include ICC_SRE_EL2. This is due
300
-
* to be relaxed in a future spec release, at which point this in
301
-
* condition can be dropped.
302
-
*/
303
-
if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) {
298
+
/* Only disable SRE if the host implements the GICv2 interface */
299
+
if (static_branch_unlikely(&vgic_v3_has_v2_compat)) {
304
300
/*
305
301
* Prevent the guest from touching the ICC_SRE_EL1 system
306
302
* register. Note that this may not have any effect, as
···
325
329
cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2);
326
330
}
327
331
328
-
/*
329
-
* Can be dropped in the future when GICv5 spec is relaxed. See comment
330
-
* above.
331
-
*/
332
-
if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) {
332
+
/* Only restore SRE if the host implements the GICv2 interface */
333
+
if (static_branch_unlikely(&vgic_v3_has_v2_compat)) {
333
334
val = read_gicreg(ICC_SRE_EL2);
334
335
write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
335
-
}
336
336
337
-
if (!cpu_if->vgic_sre) {
338
-
/* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
339
-
isb();
340
-
write_gicreg(1, ICC_SRE_EL1);
337
+
if (!cpu_if->vgic_sre) {
338
+
/* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
339
+
isb();
340
+
write_gicreg(1, ICC_SRE_EL1);
341
+
}
341
342
}
342
343
343
344
/*
+8
arch/arm64/kvm/vgic/vgic-v3.c
+8
arch/arm64/kvm/vgic/vgic-v3.c
···
588
588
}
589
589
590
590
DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
591
+
DEFINE_STATIC_KEY_FALSE(vgic_v3_has_v2_compat);
591
592
592
593
static int __init early_group0_trap_cfg(char *buf)
593
594
{
···
697
696
698
697
if (kvm_vgic_global_state.vcpu_base == 0)
699
698
kvm_info("disabling GICv2 emulation\n");
699
+
700
+
/*
701
+
* Flip the static branch if the HW supports v2, even if we're
702
+
* not using it (such as in protected mode).
703
+
*/
704
+
if (has_v2)
705
+
static_branch_enable(&vgic_v3_has_v2_compat);
700
706
701
707
if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
702
708
group0_trap = true;
+1
-1
arch/arm64/kvm/vgic/vgic-v5.c
+1
-1
arch/arm64/kvm/vgic/vgic-v5.c
+1
arch/arm64/tools/cpucaps
+1
arch/arm64/tools/cpucaps
-7
drivers/irqchip/irq-gic-v5.c
-7
drivers/irqchip/irq-gic-v5.c
···
1062
1062
#ifdef CONFIG_KVM
1063
1063
static struct gic_kvm_info gic_v5_kvm_info __initdata;
1064
1064
1065
-
static bool __init gicv5_cpuif_has_gcie_legacy(void)
1066
-
{
1067
-
u64 idr0 = read_sysreg_s(SYS_ICC_IDR0_EL1);
1068
-
return !!FIELD_GET(ICC_IDR0_EL1_GCIE_LEGACY, idr0);
1069
-
}
1070
-
1071
1065
static void __init gic_of_setup_kvm_info(struct device_node *node)
1072
1066
{
1073
1067
gic_v5_kvm_info.type = GIC_V5;
1074
-
gic_v5_kvm_info.has_gcie_v3_compat = gicv5_cpuif_has_gcie_legacy();
1075
1068
1076
1069
/* GIC Virtual CPU interface maintenance interrupt */
1077
1070
gic_v5_kvm_info.no_maint_irq_mask = false;
+1
include/kvm/arm_vgic.h
+1
include/kvm/arm_vgic.h
···
375
375
376
376
extern struct static_key_false vgic_v2_cpuif_trap;
377
377
extern struct static_key_false vgic_v3_cpuif_trap;
378
+
extern struct static_key_false vgic_v3_has_v2_compat;
378
379
379
380
int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr);
380
381
void kvm_vgic_early_init(struct kvm *kvm);