Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: relax ioremap prohibition (309caa9) for -final and -stable
ARM: 6440/1: ep93xx: DMA: fix channel_disable
cpuimx27: fix i2c bus selection
cpuimx27: fix compile when ULPI is selected
ARM: 6435/1: Fix HWCAP_TLS flag for ARM11MPCore/Cortex-A9
ARM: 6436/1: AT91: Fix power-saving in idle-mode on 926T processors
ARM: fix section mismatch warnings in Versatile Express
ARM: 6412/1: kprobes-decode: add support for MOVW instruction
ARM: 6419/1: mmu: Fix MT_MEMORY and MT_MEMORY_NONCACHED pte flags
ARM: 6416/1: errata: faulty hazard checking in the Store Buffer may lead to data corruption
+44
-17
+14
arch/arm/Kconfig
+14
arch/arm/Kconfig
···
1101
1101
invalidated are not, resulting in an incoherency in the system page
1102
1102
tables. The workaround changes the TLB flushing routines to invalidate
1103
1103
entries regardless of the ASID.
1104
+
1105
+
config ARM_ERRATA_743622
1106
+
bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1107
+
depends on CPU_V7
1108
+
help
1109
+
This option enables the workaround for the 743622 Cortex-A9
1110
+
(r2p0..r2p2) erratum. Under very rare conditions, a faulty
1111
+
optimisation in the Cortex-A9 Store Buffer may lead to data
1112
+
corruption. This workaround sets a specific bit in the diagnostic
1113
+
register of the Cortex-A9 which disables the Store Buffer
1114
+
optimisation, preventing the defect from occurring. This has no
1115
+
visible impact on the overall performance or power consumption of the
1116
+
processor.
1117
+
1104
1118
endmenu
1105
1119
1106
1120
source "arch/arm/common/Kconfig"
+4
-3
arch/arm/kernel/kprobes-decode.c
+4
-3
arch/arm/kernel/kprobes-decode.c
···
1162
1162
{
1163
1163
/*
1164
1164
* MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
1165
-
* Undef : cccc 0011 0x00 xxxx xxxx xxxx xxxx xxxx
1165
+
* Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
1166
1166
* ALU op with S bit and Rd == 15 :
1167
1167
* cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
1168
1168
*/
1169
-
if ((insn & 0x0f900000) == 0x03200000 || /* MSR & Undef */
1169
+
if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */
1170
+
(insn & 0x0ff00000) == 0x03400000 || /* Undef */
1170
1171
(insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */
1171
1172
return INSN_REJECTED;
1172
1173
···
1178
1177
* *S (bit 20) updates condition codes
1179
1178
* ADC/SBC/RSC reads the C flag
1180
1179
*/
1181
-
insn &= 0xfff00fff; /* Rn = r0, Rd = r0 */
1180
+
insn &= 0xffff0fff; /* Rd = r0 */
1182
1181
asi->insn[0] = insn;
1183
1182
asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1184
1183
emulate_alu_imm_rwflags : emulate_alu_imm_rflags;
+3
-4
arch/arm/mach-at91/include/mach/system.h
+3
-4
arch/arm/mach-at91/include/mach/system.h
···
28
28
29
29
static inline void arch_idle(void)
30
30
{
31
-
#ifndef CONFIG_DEBUG_KERNEL
32
31
/*
33
32
* Disable the processor clock. The processor will be automatically
34
33
* re-enabled by an interrupt or by a reset.
35
34
*/
36
35
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
37
-
#else
36
+
#ifndef CONFIG_CPU_ARM920T
38
37
/*
39
38
* Set the processor (CP15) into 'Wait for Interrupt' mode.
40
-
* Unlike disabling the processor clock via the PMC (above)
41
-
* this allows the processor to be woken via JTAG.
39
+
* Post-RM9200 processors need this in conjunction with the above
40
+
* to save power when idle.
42
41
*/
43
42
cpu_do_idle();
44
43
#endif
+1
-1
arch/arm/mach-ep93xx/dma-m2p.c
+1
-1
arch/arm/mach-ep93xx/dma-m2p.c
+1
arch/arm/mach-imx/Kconfig
+1
arch/arm/mach-imx/Kconfig
···
122
122
select IMX_HAVE_PLATFORM_IMX_I2C
123
123
select IMX_HAVE_PLATFORM_IMX_UART
124
124
select IMX_HAVE_PLATFORM_MXC_NAND
125
+
select MXC_ULPI if USB_ULPI
125
126
help
126
127
Include support for Eukrea CPUIMX27 platform. This includes
127
128
specific configurations for the module and its peripherals.
+1
-1
arch/arm/mach-imx/mach-cpuimx27.c
+1
-1
arch/arm/mach-imx/mach-cpuimx27.c
···
259
259
i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
260
260
ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
261
261
262
-
imx27_add_i2c_imx1(&cpuimx27_i2c1_data);
262
+
imx27_add_i2c_imx0(&cpuimx27_i2c1_data);
263
263
264
264
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
265
265
+2
-2
arch/arm/mach-vexpress/ct-ca9x4.c
+2
-2
arch/arm/mach-vexpress/ct-ca9x4.c
···
68
68
}
69
69
70
70
#if 0
71
-
static void ct_ca9x4_timer_init(void)
71
+
static void __init ct_ca9x4_timer_init(void)
72
72
{
73
73
writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
74
74
writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
···
222
222
.resource = pmu_resources,
223
223
};
224
224
225
-
static void ct_ca9x4_init(void)
225
+
static void __init ct_ca9x4_init(void)
226
226
{
227
227
int i;
228
228
+1
-1
arch/arm/mach-vexpress/v2m.c
+1
-1
arch/arm/mach-vexpress/v2m.c
+6
-2
arch/arm/mm/ioremap.c
+6
-2
arch/arm/mm/ioremap.c
···
204
204
/*
205
205
* Don't allow RAM to be mapped - this causes problems with ARMv6+
206
206
*/
207
-
if (WARN_ON(pfn_valid(pfn)))
208
-
return NULL;
207
+
if (pfn_valid(pfn)) {
208
+
printk(KERN_WARNING "BUG: Your driver calls ioremap() on system memory. This leads\n"
209
+
KERN_WARNING "to architecturally unpredictable behaviour on ARMv6+, and ioremap()\n"
210
+
KERN_WARNING "will fail in the next kernel release. Please fix your driver.\n");
211
+
WARN_ON(1);
212
+
}
209
213
210
214
type = get_mem_type(mtype);
211
215
if (!type)
+2
-2
arch/arm/mm/mmu.c
+2
-2
arch/arm/mm/mmu.c
···
248
248
},
249
249
[MT_MEMORY] = {
250
250
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
251
-
L_PTE_USER | L_PTE_EXEC,
251
+
L_PTE_WRITE | L_PTE_EXEC,
252
252
.prot_l1 = PMD_TYPE_TABLE,
253
253
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
254
254
.domain = DOMAIN_KERNEL,
···
259
259
},
260
260
[MT_MEMORY_NONCACHED] = {
261
261
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
262
-
L_PTE_USER | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
262
+
L_PTE_WRITE | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
263
263
.prot_l1 = PMD_TYPE_TABLE,
264
264
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
265
265
.domain = DOMAIN_KERNEL,
+9
-1
arch/arm/mm/proc-v7.S
+9
-1
arch/arm/mm/proc-v7.S
···
253
253
orreq r10, r10, #1 << 22 @ set bit #22
254
254
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
255
255
#endif
256
+
#ifdef CONFIG_ARM_ERRATA_743622
257
+
teq r6, #0x20 @ present in r2p0
258
+
teqne r6, #0x21 @ present in r2p1
259
+
teqne r6, #0x22 @ present in r2p2
260
+
mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
261
+
orreq r10, r10, #1 << 6 @ set bit #6
262
+
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
263
+
#endif
256
264
257
265
3: mov r10, #0
258
266
#ifdef HARVARD_CACHE
···
373
365
b __v7_ca9mp_setup
374
366
.long cpu_arch_name
375
367
.long cpu_elf_name
376
-
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
368
+
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
377
369
.long cpu_v7_name
378
370
.long v7_processor_functions
379
371
.long v7wbi_tlb_fns