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crypto: qat - disable ZUC-256 capability for QAT GEN5

The ZUC-256 EEA (encryption) and EIA (integrity) algorithms are not
supported on QAT GEN5 devices, as their current implementation does not
align with the NIST specification. Earlier versions of the ZUC-256
specification used a different initialization scheme, which has since
been revised to comply with the 5G specification.

Due to this misalignment with the updated specification, remove support
for ZUC-256 EEA and EIA for QAT GEN5 by masking out the ZUC-256
capability.

Fixes: fcf60f4bcf549 ("crypto: qat - add support for 420xx devices")
Signed-off-by: Bairavi Alagappan <bairavix.alagappan@intel.com>
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Bairavi Alagappan and committed by
Herbert Xu d956692c 34b28363

+1 -8
+1 -8
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
··· 191 191 ICP_ACCEL_CAPABILITIES_SM4 | 192 192 ICP_ACCEL_CAPABILITIES_AES_V2 | 193 193 ICP_ACCEL_CAPABILITIES_ZUC | 194 - ICP_ACCEL_CAPABILITIES_ZUC_256 | 195 194 ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT | 196 195 ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN; 197 196 ··· 222 223 223 224 if (fusectl1 & ICP_ACCEL_GEN4_MASK_WCP_WAT_SLICE) { 224 225 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC; 225 - capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC_256; 226 226 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT; 227 227 } 228 228 229 - if (fusectl1 & ICP_ACCEL_GEN4_MASK_EIA3_SLICE) { 229 + if (fusectl1 & ICP_ACCEL_GEN4_MASK_EIA3_SLICE) 230 230 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC; 231 - capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC_256; 232 - } 233 - 234 - if (fusectl1 & ICP_ACCEL_GEN4_MASK_ZUC_256_SLICE) 235 - capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC_256; 236 231 237 232 capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC | 238 233 ICP_ACCEL_CAPABILITIES_SM2 |