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spi: sophgo: Fix incorrect use of bus width value macros

The previous code initialized the 'reg' value with specific bus-width
values (BUS_WIDTH_2_BIT and BUS_WIDTH_4_BIT), which introduces ambiguity.
Replace them with BUS_WIDTH_MASK to express the intention clearly.

Fixes: de16c322eefb ("spi: sophgo: add SG2044 SPI NOR controller driver")
Signed-off-by: Longbin Li <looong.bin@gmail.com>
Link: https://patch.msgid.link/20251117090559.78288-1-looong.bin@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Longbin Li and committed by
Mark Brown d9813cd2 bd79452b

+2 -2
+2 -2
drivers/spi/spi-sg2044-nor.c
··· 42 42 #define SPIFMC_TRAN_CSR_TRAN_MODE_RX BIT(0) 43 43 #define SPIFMC_TRAN_CSR_TRAN_MODE_TX BIT(1) 44 44 #define SPIFMC_TRAN_CSR_FAST_MODE BIT(3) 45 + #define SPIFMC_TRAN_CSR_BUS_WIDTH_MASK GENMASK(5, 4) 45 46 #define SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT (0x00 << 4) 46 47 #define SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT (0x01 << 4) 47 48 #define SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT (0x02 << 4) ··· 123 122 reg = readl(spifmc->io_base + SPIFMC_TRAN_CSR); 124 123 reg &= ~(SPIFMC_TRAN_CSR_TRAN_MODE_MASK | 125 124 SPIFMC_TRAN_CSR_FAST_MODE | 126 - SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT | 127 - SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT | 125 + SPIFMC_TRAN_CSR_BUS_WIDTH_MASK | 128 126 SPIFMC_TRAN_CSR_DMA_EN | 129 127 SPIFMC_TRAN_CSR_ADDR_BYTES_MASK | 130 128 SPIFMC_TRAN_CSR_WITH_CMD |