clk: qcom: gcc-sdm660: Add missing LPASS/CDSP vote clocks

For the proper functioning of SMMUs related to the audio/compute DSPs,
it makes sense that the clocks and power domains they rely on for
communication should be online.

Add the vote clocks & GDSCs that, when enabled, ensure all such
requirements are met, through various internal mechanisms.

Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Nickolay Goppen <setotau@yandex.ru>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250815-gcc-sdm660-vote-clocks-and-gdscs-v1-2-c5a8af040093@yandex.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Nickolay Goppen and committed by

Bjorn Andersson 9 months ago d9f1c08c 9a834bfe

+72

1 changed file

expand all

drivers

clk

qcom

gcc-sdm660.c

+72

drivers/clk/qcom/gcc-sdm660.c

··· 2247 2247 }, 2248 2248 }; 2249 2249 2250 + static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = { 2251 + .halt_reg = 0x7d014, 2252 + .halt_check = BRANCH_VOTED, 2253 + .clkr = { 2254 + .enable_reg = 0x7d014, 2255 + .enable_mask = BIT(0), 2256 + .hw.init = &(const struct clk_init_data) { 2257 + .name = "hlos1_vote_lpass_adsp_smmu_clk", 2258 + .ops = &clk_branch2_ops, 2259 + }, 2260 + }, 2261 + }; 2262 + 2263 + static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = { 2264 + .halt_reg = 0x7d048, 2265 + .halt_check = BRANCH_VOTED, 2266 + .clkr = { 2267 + .enable_reg = 0x7d048, 2268 + .enable_mask = BIT(0), 2269 + .hw.init = &(const struct clk_init_data) { 2270 + .name = "hlos1_vote_turing_adsp_smmu_clk", 2271 + .ops = &clk_branch2_ops, 2272 + }, 2273 + }, 2274 + }; 2275 + 2276 + static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = { 2277 + .halt_reg = 0x7e048, 2278 + .halt_check = BRANCH_VOTED, 2279 + .clkr = { 2280 + .enable_reg = 0x7e048, 2281 + .enable_mask = BIT(0), 2282 + .hw.init = &(const struct clk_init_data) { 2283 + .name = "hlos2_vote_turing_adsp_smmu_clk", 2284 + .ops = &clk_branch2_ops, 2285 + }, 2286 + }, 2287 + }; 2288 + 2250 2289 static struct gdsc ufs_gdsc = { 2251 2290 .gdscr = 0x75004, 2252 2291 .gds_hw_ctrl = 0x0, ··· 2311 2272 .gds_hw_ctrl = 0x0, 2312 2273 .pd = { 2313 2274 .name = "pcie_0_gdsc", 2275 + }, 2276 + .pwrsts = PWRSTS_OFF_ON, 2277 + .flags = VOTABLE, 2278 + }; 2279 + 2280 + static struct gdsc hlos1_vote_turing_adsp_gdsc = { 2281 + .gdscr = 0x7d04c, 2282 + .pd = { 2283 + .name = "hlos1_vote_turing_adsp_gdsc", 2284 + }, 2285 + .pwrsts = PWRSTS_OFF_ON, 2286 + .flags = VOTABLE, 2287 + }; 2288 + 2289 + static struct gdsc hlos2_vote_turing_adsp_gdsc = { 2290 + .gdscr = 0x7e04c, 2291 + .pd = { 2292 + .name = "hlos2_vote_turing_adsp_gdsc", 2293 + }, 2294 + .pwrsts = PWRSTS_OFF_ON, 2295 + .flags = VOTABLE, 2296 + }; 2297 + 2298 + static struct gdsc hlos1_vote_lpass_adsp_gdsc = { 2299 + .gdscr = 0x7d034, 2300 + .pd = { 2301 + .name = "hlos1_vote_lpass_adsp_gdsc", 2314 2302 }, 2315 2303 .pwrsts = PWRSTS_OFF_ON, 2316 2304 .flags = VOTABLE, ··· 2475 2409 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2476 2410 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2477 2411 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2412 + [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr, 2413 + [GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK] = &hlos1_vote_turing_adsp_smmu_clk.clkr, 2414 + [GCC_HLOS2_VOTE_TURING_ADSP_SMMU_CLK] = &hlos2_vote_turing_adsp_smmu_clk.clkr, 2478 2415 }; 2479 2416 2480 2417 static struct gdsc *gcc_sdm660_gdscs[] = { 2481 2418 [UFS_GDSC] = &ufs_gdsc, 2482 2419 [USB_30_GDSC] = &usb_30_gdsc, 2483 2420 [PCIE_0_GDSC] = &pcie_0_gdsc, 2421 + [HLOS1_VOTE_TURING_ADSP_GDSC] = &hlos1_vote_turing_adsp_gdsc, 2422 + [HLOS2_VOTE_TURING_ADSP_GDSC] = &hlos2_vote_turing_adsp_gdsc, 2423 + [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc, 2484 2424 }; 2485 2425 2486 2426 static const struct qcom_reset_map gcc_sdm660_resets[] = {

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