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clk: qcom: gcc-sdm660: Replace usage of parent_names

Using parent_data and parent_hws, instead of parent_names, does protect
against some cases of incompletely defined clock trees. While it turns
out that the bug being chased this time was totally unrelated, this
patch converts the SDM660 GCC driver to avoid such issues.

The "xo" fixed_factor clock is unused within the gcc driver, but
referenced from the DSI PHY. So it's left in place until the DSI driver
is updated.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210825204517.1278130-1-bjorn.andersson@linaro.org
[sboyd@kernel.org: Reduce diff by moving enum and tables back to
original position in previous patch]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Bjorn Andersson and committed by
Stephen Boyd da09577a a61ca021

+194 -176
+194 -176
drivers/clk/qcom/gcc-sdm660.c
··· 42 42 .div = 1, 43 43 .hw.init = &(struct clk_init_data){ 44 44 .name = "xo", 45 - .parent_names = (const char *[]){ "xo_board" }, 45 + .parent_data = &(const struct clk_parent_data) { 46 + .fw_name = "xo" 47 + }, 46 48 .num_parents = 1, 47 49 .ops = &clk_fixed_factor_ops, 48 50 }, ··· 58 56 .enable_mask = BIT(0), 59 57 .hw.init = &(struct clk_init_data){ 60 58 .name = "gpll0_early", 61 - .parent_names = (const char *[]){ "xo" }, 59 + .parent_data = &(const struct clk_parent_data){ 60 + .fw_name = "xo", 61 + }, 62 62 .num_parents = 1, 63 63 .ops = &clk_alpha_pll_ops, 64 64 }, ··· 72 68 .div = 2, 73 69 .hw.init = &(struct clk_init_data){ 74 70 .name = "gpll0_early_div", 75 - .parent_names = (const char *[]){ "gpll0_early" }, 71 + .parent_hws = (const struct clk_hw*[]){ 72 + &gpll0_early.clkr.hw, 73 + }, 76 74 .num_parents = 1, 77 75 .ops = &clk_fixed_factor_ops, 78 76 }, ··· 85 79 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 86 80 .clkr.hw.init = &(struct clk_init_data){ 87 81 .name = "gpll0", 88 - .parent_names = (const char *[]){ "gpll0_early" }, 82 + .parent_hws = (const struct clk_hw*[]){ 83 + &gpll0_early.clkr.hw, 84 + }, 89 85 .num_parents = 1, 90 86 .ops = &clk_alpha_pll_postdiv_ops, 91 87 }, ··· 101 93 .enable_mask = BIT(1), 102 94 .hw.init = &(struct clk_init_data){ 103 95 .name = "gpll1_early", 104 - .parent_names = (const char *[]){ "xo" }, 96 + .parent_data = &(const struct clk_parent_data){ 97 + .fw_name = "xo", 98 + }, 105 99 .num_parents = 1, 106 100 .ops = &clk_alpha_pll_ops, 107 101 }, ··· 115 105 .div = 2, 116 106 .hw.init = &(struct clk_init_data){ 117 107 .name = "gpll1_early_div", 118 - .parent_names = (const char *[]){ "gpll1_early" }, 108 + .parent_hws = (const struct clk_hw*[]){ 109 + &gpll1_early.clkr.hw, 110 + }, 119 111 .num_parents = 1, 120 112 .ops = &clk_fixed_factor_ops, 121 113 }, ··· 128 116 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 129 117 .clkr.hw.init = &(struct clk_init_data){ 130 118 .name = "gpll1", 131 - .parent_names = (const char *[]){ "gpll1_early" }, 119 + .parent_hws = (const struct clk_hw*[]){ 120 + &gpll1_early.clkr.hw, 121 + }, 132 122 .num_parents = 1, 133 123 .ops = &clk_alpha_pll_postdiv_ops, 134 124 }, ··· 144 130 .enable_mask = BIT(4), 145 131 .hw.init = &(struct clk_init_data){ 146 132 .name = "gpll4_early", 147 - .parent_names = (const char *[]){ "xo" }, 133 + .parent_data = &(const struct clk_parent_data){ 134 + .fw_name = "xo", 135 + }, 148 136 .num_parents = 1, 149 137 .ops = &clk_alpha_pll_ops, 150 138 }, ··· 159 143 .clkr.hw.init = &(struct clk_init_data) 160 144 { 161 145 .name = "gpll4", 162 - .parent_names = (const char *[]) { "gpll4_early" }, 146 + .parent_hws = (const struct clk_hw*[]){ 147 + &gpll4_early.clkr.hw, 148 + }, 163 149 .num_parents = 1, 164 150 .ops = &clk_alpha_pll_postdiv_ops, 165 151 }, ··· 173 155 { P_GPLL0_EARLY_DIV, 6 }, 174 156 }; 175 157 176 - static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = { 177 - "xo", 178 - "gpll0", 179 - "gpll0_early_div", 158 + static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div[] = { 159 + { .fw_name = "xo" }, 160 + { .hw = &gpll0.clkr.hw }, 161 + { .hw = &gpll0_early_div.hw }, 180 162 }; 181 163 182 164 static const struct parent_map gcc_parent_map_xo_gpll0[] = { ··· 184 166 { P_GPLL0, 1 }, 185 167 }; 186 168 187 - static const char * const gcc_parent_names_xo_gpll0[] = { 188 - "xo", 189 - "gpll0", 169 + static const struct clk_parent_data gcc_parent_data_xo_gpll0[] = { 170 + { .fw_name = "xo" }, 171 + { .hw = &gpll0.clkr.hw }, 190 172 }; 191 173 192 174 static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = { ··· 196 178 { P_GPLL0_EARLY_DIV, 6 }, 197 179 }; 198 180 199 - static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = { 200 - "xo", 201 - "gpll0", 202 - "sleep_clk", 203 - "gpll0_early_div", 181 + static const struct clk_parent_data gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div[] = { 182 + { .fw_name = "xo" }, 183 + { .hw = &gpll0.clkr.hw }, 184 + { .fw_name = "sleep_clk" }, 185 + { .hw = &gpll0_early_div.hw }, 204 186 }; 205 187 206 188 static const struct parent_map gcc_parent_map_xo_sleep_clk[] = { ··· 208 190 { P_SLEEP_CLK, 5 }, 209 191 }; 210 192 211 - static const char * const gcc_parent_names_xo_sleep_clk[] = { 212 - "xo", 213 - "sleep_clk", 193 + static const struct clk_parent_data gcc_parent_data_xo_sleep_clk[] = { 194 + { .fw_name = "xo" }, 195 + { .fw_name = "sleep_clk" }, 214 196 }; 215 197 216 198 static const struct parent_map gcc_parent_map_xo_gpll4[] = { ··· 218 200 { P_GPLL4, 5 }, 219 201 }; 220 202 221 - static const char * const gcc_parent_names_xo_gpll4[] = { 222 - "xo", 223 - "gpll4", 203 + static const struct clk_parent_data gcc_parent_data_xo_gpll4[] = { 204 + { .fw_name = "xo" }, 205 + { .hw = &gpll4.clkr.hw }, 224 206 }; 225 207 226 208 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { ··· 232 214 { P_GPLL1_EARLY_DIV, 6 }, 233 215 }; 234 216 235 - static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { 236 - "xo", 237 - "gpll0", 238 - "gpll0_early_div", 239 - "gpll1", 240 - "gpll4", 241 - "gpll1_early_div", 217 + static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { 218 + { .fw_name = "xo" }, 219 + { .hw = &gpll0.clkr.hw }, 220 + { .hw = &gpll0_early_div.hw }, 221 + { .hw = &gpll1.clkr.hw }, 222 + { .hw = &gpll4.clkr.hw }, 223 + { .hw = &gpll1_early_div.hw }, 242 224 }; 243 225 244 226 static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = { ··· 248 230 { P_GPLL0_EARLY_DIV, 6 }, 249 231 }; 250 232 251 - static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = { 252 - "xo", 253 - "gpll0", 254 - "gpll4", 255 - "gpll0_early_div", 233 + static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div[] = { 234 + { .fw_name = "xo" }, 235 + { .hw = &gpll0.clkr.hw }, 236 + { .hw = &gpll4.clkr.hw }, 237 + { .hw = &gpll0_early_div.hw }, 256 238 }; 257 239 258 240 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = { ··· 262 244 { P_GPLL4, 5 }, 263 245 }; 264 246 265 - static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = { 266 - "xo", 267 - "gpll0", 268 - "gpll0_early_div", 269 - "gpll4", 247 + static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4[] = { 248 + { .fw_name = "xo" }, 249 + { .hw = &gpll0.clkr.hw }, 250 + { .hw = &gpll0_early_div.hw }, 251 + { .hw = &gpll4.clkr.hw }, 270 252 }; 271 253 272 254 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { ··· 283 265 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 284 266 .clkr.hw.init = &(struct clk_init_data){ 285 267 .name = "blsp1_qup1_i2c_apps_clk_src", 286 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 268 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 287 269 .num_parents = 3, 288 270 .ops = &clk_rcg2_ops, 289 271 }, ··· 308 290 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 309 291 .clkr.hw.init = &(struct clk_init_data){ 310 292 .name = "blsp1_qup1_spi_apps_clk_src", 311 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 293 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 312 294 .num_parents = 3, 313 295 .ops = &clk_rcg2_ops, 314 296 }, ··· 322 304 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 323 305 .clkr.hw.init = &(struct clk_init_data){ 324 306 .name = "blsp1_qup2_i2c_apps_clk_src", 325 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 307 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 326 308 .num_parents = 3, 327 309 .ops = &clk_rcg2_ops, 328 310 }, ··· 336 318 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 337 319 .clkr.hw.init = &(struct clk_init_data){ 338 320 .name = "blsp1_qup2_spi_apps_clk_src", 339 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 321 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 340 322 .num_parents = 3, 341 323 .ops = &clk_rcg2_ops, 342 324 }, ··· 350 332 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 351 333 .clkr.hw.init = &(struct clk_init_data){ 352 334 .name = "blsp1_qup3_i2c_apps_clk_src", 353 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 335 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 354 336 .num_parents = 3, 355 337 .ops = &clk_rcg2_ops, 356 338 }, ··· 364 346 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 365 347 .clkr.hw.init = &(struct clk_init_data){ 366 348 .name = "blsp1_qup3_spi_apps_clk_src", 367 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 349 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 368 350 .num_parents = 3, 369 351 .ops = &clk_rcg2_ops, 370 352 }, ··· 378 360 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 379 361 .clkr.hw.init = &(struct clk_init_data){ 380 362 .name = "blsp1_qup4_i2c_apps_clk_src", 381 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 363 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 382 364 .num_parents = 3, 383 365 .ops = &clk_rcg2_ops, 384 366 }, ··· 392 374 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 393 375 .clkr.hw.init = &(struct clk_init_data){ 394 376 .name = "blsp1_qup4_spi_apps_clk_src", 395 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 377 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 396 378 .num_parents = 3, 397 379 .ops = &clk_rcg2_ops, 398 380 }, ··· 425 407 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 426 408 .clkr.hw.init = &(struct clk_init_data){ 427 409 .name = "blsp1_uart1_apps_clk_src", 428 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 410 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 429 411 .num_parents = 3, 430 412 .ops = &clk_rcg2_ops, 431 413 }, ··· 439 421 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 440 422 .clkr.hw.init = &(struct clk_init_data){ 441 423 .name = "blsp1_uart2_apps_clk_src", 442 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 424 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 443 425 .num_parents = 3, 444 426 .ops = &clk_rcg2_ops, 445 427 }, ··· 453 435 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 454 436 .clkr.hw.init = &(struct clk_init_data){ 455 437 .name = "blsp2_qup1_i2c_apps_clk_src", 456 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 438 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 457 439 .num_parents = 3, 458 440 .ops = &clk_rcg2_ops, 459 441 }, ··· 467 449 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 468 450 .clkr.hw.init = &(struct clk_init_data){ 469 451 .name = "blsp2_qup1_spi_apps_clk_src", 470 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 452 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 471 453 .num_parents = 3, 472 454 .ops = &clk_rcg2_ops, 473 455 }, ··· 481 463 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 482 464 .clkr.hw.init = &(struct clk_init_data){ 483 465 .name = "blsp2_qup2_i2c_apps_clk_src", 484 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 466 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 485 467 .num_parents = 3, 486 468 .ops = &clk_rcg2_ops, 487 469 }, ··· 495 477 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 496 478 .clkr.hw.init = &(struct clk_init_data){ 497 479 .name = "blsp2_qup2_spi_apps_clk_src", 498 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 480 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 499 481 .num_parents = 3, 500 482 .ops = &clk_rcg2_ops, 501 483 }, ··· 509 491 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 510 492 .clkr.hw.init = &(struct clk_init_data){ 511 493 .name = "blsp2_qup3_i2c_apps_clk_src", 512 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 494 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 513 495 .num_parents = 3, 514 496 .ops = &clk_rcg2_ops, 515 497 }, ··· 523 505 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 524 506 .clkr.hw.init = &(struct clk_init_data){ 525 507 .name = "blsp2_qup3_spi_apps_clk_src", 526 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 508 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 527 509 .num_parents = 3, 528 510 .ops = &clk_rcg2_ops, 529 511 }, ··· 537 519 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 538 520 .clkr.hw.init = &(struct clk_init_data){ 539 521 .name = "blsp2_qup4_i2c_apps_clk_src", 540 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 522 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 541 523 .num_parents = 3, 542 524 .ops = &clk_rcg2_ops, 543 525 }, ··· 551 533 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 552 534 .clkr.hw.init = &(struct clk_init_data){ 553 535 .name = "blsp2_qup4_spi_apps_clk_src", 554 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 536 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 555 537 .num_parents = 3, 556 538 .ops = &clk_rcg2_ops, 557 539 }, ··· 565 547 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 566 548 .clkr.hw.init = &(struct clk_init_data){ 567 549 .name = "blsp2_uart1_apps_clk_src", 568 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 550 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 569 551 .num_parents = 3, 570 552 .ops = &clk_rcg2_ops, 571 553 }, ··· 579 561 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 580 562 .clkr.hw.init = &(struct clk_init_data){ 581 563 .name = "blsp2_uart2_apps_clk_src", 582 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 564 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 583 565 .num_parents = 3, 584 566 .ops = &clk_rcg2_ops, 585 567 }, ··· 600 582 .freq_tbl = ftbl_gp1_clk_src, 601 583 .clkr.hw.init = &(struct clk_init_data){ 602 584 .name = "gp1_clk_src", 603 - .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, 585 + .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, 604 586 .num_parents = 4, 605 587 .ops = &clk_rcg2_ops, 606 588 }, ··· 614 596 .freq_tbl = ftbl_gp1_clk_src, 615 597 .clkr.hw.init = &(struct clk_init_data){ 616 598 .name = "gp2_clk_src", 617 - .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, 599 + .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, 618 600 .num_parents = 4, 619 601 .ops = &clk_rcg2_ops, 620 602 }, ··· 628 610 .freq_tbl = ftbl_gp1_clk_src, 629 611 .clkr.hw.init = &(struct clk_init_data){ 630 612 .name = "gp3_clk_src", 631 - .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, 613 + .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, 632 614 .num_parents = 4, 633 615 .ops = &clk_rcg2_ops, 634 616 }, ··· 648 630 .freq_tbl = ftbl_hmss_gpll0_clk_src, 649 631 .clkr.hw.init = &(struct clk_init_data){ 650 632 .name = "hmss_gpll0_clk_src", 651 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 633 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 652 634 .num_parents = 3, 653 635 .ops = &clk_rcg2_ops, 654 636 }, ··· 669 651 .freq_tbl = ftbl_hmss_gpll4_clk_src, 670 652 .clkr.hw.init = &(struct clk_init_data){ 671 653 .name = "hmss_gpll4_clk_src", 672 - .parent_names = gcc_parent_names_xo_gpll4, 654 + .parent_data = gcc_parent_data_xo_gpll4, 673 655 .num_parents = 2, 674 656 .ops = &clk_rcg2_ops, 675 657 }, ··· 688 670 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 689 671 .clkr.hw.init = &(struct clk_init_data){ 690 672 .name = "hmss_rbcpr_clk_src", 691 - .parent_names = gcc_parent_names_xo_gpll0, 673 + .parent_data = gcc_parent_data_xo_gpll0, 692 674 .num_parents = 2, 693 675 .ops = &clk_rcg2_ops, 694 676 }, ··· 707 689 .freq_tbl = ftbl_pdm2_clk_src, 708 690 .clkr.hw.init = &(struct clk_init_data){ 709 691 .name = "pdm2_clk_src", 710 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 692 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 711 693 .num_parents = 3, 712 694 .ops = &clk_rcg2_ops, 713 695 }, ··· 729 711 .freq_tbl = ftbl_qspi_ser_clk_src, 730 712 .clkr.hw.init = &(struct clk_init_data){ 731 713 .name = "qspi_ser_clk_src", 732 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, 714 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, 733 715 .num_parents = 6, 734 716 .ops = &clk_rcg2_ops, 735 717 }, ··· 755 737 .freq_tbl = ftbl_sdcc1_apps_clk_src, 756 738 .clkr.hw.init = &(struct clk_init_data){ 757 739 .name = "sdcc1_apps_clk_src", 758 - .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div, 740 + .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div, 759 741 .num_parents = 4, 760 742 .ops = &clk_rcg2_ops, 761 743 }, ··· 777 759 .freq_tbl = ftbl_sdcc1_ice_core_clk_src, 778 760 .clkr.hw.init = &(struct clk_init_data){ 779 761 .name = "sdcc1_ice_core_clk_src", 780 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 762 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 781 763 .num_parents = 3, 782 764 .ops = &clk_rcg2_ops, 783 765 }, ··· 803 785 .freq_tbl = ftbl_sdcc2_apps_clk_src, 804 786 .clkr.hw.init = &(struct clk_init_data){ 805 787 .name = "sdcc2_apps_clk_src", 806 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4, 788 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4, 807 789 .num_parents = 4, 808 790 .ops = &clk_rcg2_floor_ops, 809 791 }, ··· 826 808 .freq_tbl = ftbl_ufs_axi_clk_src, 827 809 .clkr.hw.init = &(struct clk_init_data){ 828 810 .name = "ufs_axi_clk_src", 829 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 811 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 830 812 .num_parents = 3, 831 813 .ops = &clk_rcg2_ops, 832 814 }, ··· 847 829 .freq_tbl = ftbl_ufs_ice_core_clk_src, 848 830 .clkr.hw.init = &(struct clk_init_data){ 849 831 .name = "ufs_ice_core_clk_src", 850 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 832 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 851 833 .num_parents = 3, 852 834 .ops = &clk_rcg2_ops, 853 835 }, ··· 861 843 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 862 844 .clkr.hw.init = &(struct clk_init_data){ 863 845 .name = "ufs_phy_aux_clk_src", 864 - .parent_names = gcc_parent_names_xo_sleep_clk, 846 + .parent_data = gcc_parent_data_xo_sleep_clk, 865 847 .num_parents = 2, 866 848 .ops = &clk_rcg2_ops, 867 849 }, ··· 882 864 .freq_tbl = ftbl_ufs_unipro_core_clk_src, 883 865 .clkr.hw.init = &(struct clk_init_data){ 884 866 .name = "ufs_unipro_core_clk_src", 885 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 867 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 886 868 .num_parents = 3, 887 869 .ops = &clk_rcg2_ops, 888 870 }, ··· 903 885 .freq_tbl = ftbl_usb20_master_clk_src, 904 886 .clkr.hw.init = &(struct clk_init_data){ 905 887 .name = "usb20_master_clk_src", 906 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 888 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 907 889 .num_parents = 3, 908 890 .ops = &clk_rcg2_ops, 909 891 }, ··· 923 905 .freq_tbl = ftbl_usb20_mock_utmi_clk_src, 924 906 .clkr.hw.init = &(struct clk_init_data){ 925 907 .name = "usb20_mock_utmi_clk_src", 926 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 908 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 927 909 .num_parents = 3, 928 910 .ops = &clk_rcg2_ops, 929 911 }, ··· 948 930 .freq_tbl = ftbl_usb30_master_clk_src, 949 931 .clkr.hw.init = &(struct clk_init_data){ 950 932 .name = "usb30_master_clk_src", 951 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 933 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 952 934 .num_parents = 3, 953 935 .ops = &clk_rcg2_ops, 954 936 }, ··· 969 951 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 970 952 .clkr.hw.init = &(struct clk_init_data){ 971 953 .name = "usb30_mock_utmi_clk_src", 972 - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, 954 + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 973 955 .num_parents = 3, 974 956 .ops = &clk_rcg2_ops, 975 957 }, ··· 989 971 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 990 972 .clkr.hw.init = &(struct clk_init_data){ 991 973 .name = "usb3_phy_aux_clk_src", 992 - .parent_names = gcc_parent_names_xo_sleep_clk, 974 + .parent_data = gcc_parent_data_xo_sleep_clk, 993 975 .num_parents = 2, 994 976 .ops = &clk_rcg2_ops, 995 977 }, ··· 1003 985 .enable_mask = BIT(0), 1004 986 .hw.init = &(struct clk_init_data){ 1005 987 .name = "gcc_aggre2_ufs_axi_clk", 1006 - .parent_names = (const char *[]){ 1007 - "ufs_axi_clk_src", 988 + .parent_hws = (const struct clk_hw*[]) { 989 + &ufs_axi_clk_src.clkr.hw, 1008 990 }, 1009 991 .num_parents = 1, 1010 992 .ops = &clk_branch2_ops, ··· 1020 1002 .enable_mask = BIT(0), 1021 1003 .hw.init = &(struct clk_init_data){ 1022 1004 .name = "gcc_aggre2_usb3_axi_clk", 1023 - .parent_names = (const char *[]){ 1024 - "usb30_master_clk_src", 1005 + .parent_hws = (const struct clk_hw*[]) { 1006 + &usb30_master_clk_src.clkr.hw, 1025 1007 }, 1026 1008 .num_parents = 1, 1027 1009 .ops = &clk_branch2_ops, ··· 1089 1071 .enable_mask = BIT(0), 1090 1072 .hw.init = &(struct clk_init_data){ 1091 1073 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1092 - .parent_names = (const char *[]){ 1093 - "blsp1_qup1_i2c_apps_clk_src", 1074 + .parent_hws = (const struct clk_hw*[]) { 1075 + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1094 1076 }, 1095 1077 .num_parents = 1, 1096 1078 .flags = CLK_SET_RATE_PARENT, ··· 1107 1089 .enable_mask = BIT(0), 1108 1090 .hw.init = &(struct clk_init_data){ 1109 1091 .name = "gcc_blsp1_qup1_spi_apps_clk", 1110 - .parent_names = (const char *[]){ 1111 - "blsp1_qup1_spi_apps_clk_src", 1092 + .parent_hws = (const struct clk_hw*[]) { 1093 + &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1112 1094 }, 1113 1095 .num_parents = 1, 1114 1096 .flags = CLK_SET_RATE_PARENT, ··· 1125 1107 .enable_mask = BIT(0), 1126 1108 .hw.init = &(struct clk_init_data){ 1127 1109 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1128 - .parent_names = (const char *[]){ 1129 - "blsp1_qup2_i2c_apps_clk_src", 1110 + .parent_hws = (const struct clk_hw*[]) { 1111 + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1130 1112 }, 1131 1113 .num_parents = 1, 1132 1114 .flags = CLK_SET_RATE_PARENT, ··· 1143 1125 .enable_mask = BIT(0), 1144 1126 .hw.init = &(struct clk_init_data){ 1145 1127 .name = "gcc_blsp1_qup2_spi_apps_clk", 1146 - .parent_names = (const char *[]){ 1147 - "blsp1_qup2_spi_apps_clk_src", 1128 + .parent_hws = (const struct clk_hw*[]) { 1129 + &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1148 1130 }, 1149 1131 .num_parents = 1, 1150 1132 .flags = CLK_SET_RATE_PARENT, ··· 1161 1143 .enable_mask = BIT(0), 1162 1144 .hw.init = &(struct clk_init_data){ 1163 1145 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1164 - .parent_names = (const char *[]){ 1165 - "blsp1_qup3_i2c_apps_clk_src", 1146 + .parent_hws = (const struct clk_hw*[]) { 1147 + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1166 1148 }, 1167 1149 .num_parents = 1, 1168 1150 .flags = CLK_SET_RATE_PARENT, ··· 1179 1161 .enable_mask = BIT(0), 1180 1162 .hw.init = &(struct clk_init_data){ 1181 1163 .name = "gcc_blsp1_qup3_spi_apps_clk", 1182 - .parent_names = (const char *[]){ 1183 - "blsp1_qup3_spi_apps_clk_src", 1164 + .parent_hws = (const struct clk_hw*[]) { 1165 + &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1184 1166 }, 1185 1167 .num_parents = 1, 1186 1168 .flags = CLK_SET_RATE_PARENT, ··· 1197 1179 .enable_mask = BIT(0), 1198 1180 .hw.init = &(struct clk_init_data){ 1199 1181 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1200 - .parent_names = (const char *[]){ 1201 - "blsp1_qup4_i2c_apps_clk_src", 1182 + .parent_hws = (const struct clk_hw*[]) { 1183 + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1202 1184 }, 1203 1185 .num_parents = 1, 1204 1186 .flags = CLK_SET_RATE_PARENT, ··· 1215 1197 .enable_mask = BIT(0), 1216 1198 .hw.init = &(struct clk_init_data){ 1217 1199 .name = "gcc_blsp1_qup4_spi_apps_clk", 1218 - .parent_names = (const char *[]){ 1219 - "blsp1_qup4_spi_apps_clk_src", 1200 + .parent_hws = (const struct clk_hw*[]) { 1201 + &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1220 1202 }, 1221 1203 .num_parents = 1, 1222 1204 .flags = CLK_SET_RATE_PARENT, ··· 1233 1215 .enable_mask = BIT(0), 1234 1216 .hw.init = &(struct clk_init_data){ 1235 1217 .name = "gcc_blsp1_uart1_apps_clk", 1236 - .parent_names = (const char *[]){ 1237 - "blsp1_uart1_apps_clk_src", 1218 + .parent_hws = (const struct clk_hw*[]) { 1219 + &blsp1_uart1_apps_clk_src.clkr.hw, 1238 1220 }, 1239 1221 .num_parents = 1, 1240 1222 .flags = CLK_SET_RATE_PARENT, ··· 1251 1233 .enable_mask = BIT(0), 1252 1234 .hw.init = &(struct clk_init_data){ 1253 1235 .name = "gcc_blsp1_uart2_apps_clk", 1254 - .parent_names = (const char *[]){ 1255 - "blsp1_uart2_apps_clk_src", 1236 + .parent_hws = (const struct clk_hw*[]) { 1237 + &blsp1_uart2_apps_clk_src.clkr.hw, 1256 1238 }, 1257 1239 .num_parents = 1, 1258 1240 .flags = CLK_SET_RATE_PARENT, ··· 1282 1264 .enable_mask = BIT(0), 1283 1265 .hw.init = &(struct clk_init_data){ 1284 1266 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1285 - .parent_names = (const char *[]){ 1286 - "blsp2_qup1_i2c_apps_clk_src", 1267 + .parent_hws = (const struct clk_hw*[]) { 1268 + &blsp2_qup1_i2c_apps_clk_src.clkr.hw, 1287 1269 }, 1288 1270 .num_parents = 1, 1289 1271 .flags = CLK_SET_RATE_PARENT, ··· 1300 1282 .enable_mask = BIT(0), 1301 1283 .hw.init = &(struct clk_init_data){ 1302 1284 .name = "gcc_blsp2_qup1_spi_apps_clk", 1303 - .parent_names = (const char *[]){ 1304 - "blsp2_qup1_spi_apps_clk_src", 1285 + .parent_hws = (const struct clk_hw*[]) { 1286 + &blsp2_qup1_spi_apps_clk_src.clkr.hw, 1305 1287 }, 1306 1288 .num_parents = 1, 1307 1289 .flags = CLK_SET_RATE_PARENT, ··· 1318 1300 .enable_mask = BIT(0), 1319 1301 .hw.init = &(struct clk_init_data){ 1320 1302 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1321 - .parent_names = (const char *[]){ 1322 - "blsp2_qup2_i2c_apps_clk_src", 1303 + .parent_hws = (const struct clk_hw*[]) { 1304 + &blsp2_qup2_i2c_apps_clk_src.clkr.hw, 1323 1305 }, 1324 1306 .num_parents = 1, 1325 1307 .flags = CLK_SET_RATE_PARENT, ··· 1336 1318 .enable_mask = BIT(0), 1337 1319 .hw.init = &(struct clk_init_data){ 1338 1320 .name = "gcc_blsp2_qup2_spi_apps_clk", 1339 - .parent_names = (const char *[]){ 1340 - "blsp2_qup2_spi_apps_clk_src", 1321 + .parent_hws = (const struct clk_hw*[]) { 1322 + &blsp2_qup2_spi_apps_clk_src.clkr.hw, 1341 1323 }, 1342 1324 .num_parents = 1, 1343 1325 .flags = CLK_SET_RATE_PARENT, ··· 1354 1336 .enable_mask = BIT(0), 1355 1337 .hw.init = &(struct clk_init_data){ 1356 1338 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1357 - .parent_names = (const char *[]){ 1358 - "blsp2_qup3_i2c_apps_clk_src", 1339 + .parent_hws = (const struct clk_hw*[]) { 1340 + &blsp2_qup3_i2c_apps_clk_src.clkr.hw, 1359 1341 }, 1360 1342 .num_parents = 1, 1361 1343 .flags = CLK_SET_RATE_PARENT, ··· 1372 1354 .enable_mask = BIT(0), 1373 1355 .hw.init = &(struct clk_init_data){ 1374 1356 .name = "gcc_blsp2_qup3_spi_apps_clk", 1375 - .parent_names = (const char *[]){ 1376 - "blsp2_qup3_spi_apps_clk_src", 1357 + .parent_hws = (const struct clk_hw*[]) { 1358 + &blsp2_qup3_spi_apps_clk_src.clkr.hw, 1377 1359 }, 1378 1360 .num_parents = 1, 1379 1361 .flags = CLK_SET_RATE_PARENT, ··· 1390 1372 .enable_mask = BIT(0), 1391 1373 .hw.init = &(struct clk_init_data){ 1392 1374 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1393 - .parent_names = (const char *[]){ 1394 - "blsp2_qup4_i2c_apps_clk_src", 1375 + .parent_hws = (const struct clk_hw*[]) { 1376 + &blsp2_qup4_i2c_apps_clk_src.clkr.hw, 1395 1377 }, 1396 1378 .num_parents = 1, 1397 1379 .flags = CLK_SET_RATE_PARENT, ··· 1408 1390 .enable_mask = BIT(0), 1409 1391 .hw.init = &(struct clk_init_data){ 1410 1392 .name = "gcc_blsp2_qup4_spi_apps_clk", 1411 - .parent_names = (const char *[]){ 1412 - "blsp2_qup4_spi_apps_clk_src", 1393 + .parent_hws = (const struct clk_hw*[]) { 1394 + &blsp2_qup4_spi_apps_clk_src.clkr.hw, 1413 1395 }, 1414 1396 .num_parents = 1, 1415 1397 .flags = CLK_SET_RATE_PARENT, ··· 1426 1408 .enable_mask = BIT(0), 1427 1409 .hw.init = &(struct clk_init_data){ 1428 1410 .name = "gcc_blsp2_uart1_apps_clk", 1429 - .parent_names = (const char *[]){ 1430 - "blsp2_uart1_apps_clk_src", 1411 + .parent_hws = (const struct clk_hw*[]) { 1412 + &blsp2_uart1_apps_clk_src.clkr.hw, 1431 1413 }, 1432 1414 .num_parents = 1, 1433 1415 .flags = CLK_SET_RATE_PARENT, ··· 1444 1426 .enable_mask = BIT(0), 1445 1427 .hw.init = &(struct clk_init_data){ 1446 1428 .name = "gcc_blsp2_uart2_apps_clk", 1447 - .parent_names = (const char *[]){ 1448 - "blsp2_uart2_apps_clk_src", 1429 + .parent_hws = (const struct clk_hw*[]) { 1430 + &blsp2_uart2_apps_clk_src.clkr.hw, 1449 1431 }, 1450 1432 .num_parents = 1, 1451 1433 .flags = CLK_SET_RATE_PARENT, ··· 1475 1457 .enable_mask = BIT(0), 1476 1458 .hw.init = &(struct clk_init_data){ 1477 1459 .name = "gcc_cfg_noc_usb2_axi_clk", 1478 - .parent_names = (const char *[]){ 1479 - "usb20_master_clk_src", 1460 + .parent_hws = (const struct clk_hw*[]) { 1461 + &usb20_master_clk_src.clkr.hw, 1480 1462 }, 1481 1463 .num_parents = 1, 1482 1464 .ops = &clk_branch2_ops, ··· 1492 1474 .enable_mask = BIT(0), 1493 1475 .hw.init = &(struct clk_init_data){ 1494 1476 .name = "gcc_cfg_noc_usb3_axi_clk", 1495 - .parent_names = (const char *[]){ 1496 - "usb30_master_clk_src", 1477 + .parent_hws = (const struct clk_hw*[]) { 1478 + &usb30_master_clk_src.clkr.hw, 1497 1479 }, 1498 1480 .num_parents = 1, 1499 1481 .ops = &clk_branch2_ops, ··· 1521 1503 .enable_mask = BIT(0), 1522 1504 .hw.init = &(struct clk_init_data){ 1523 1505 .name = "gcc_gp1_clk", 1524 - .parent_names = (const char *[]){ 1525 - "gp1_clk_src", 1506 + .parent_hws = (const struct clk_hw*[]) { 1507 + &gp1_clk_src.clkr.hw, 1526 1508 }, 1527 1509 .num_parents = 1, 1528 1510 .flags = CLK_SET_RATE_PARENT, ··· 1539 1521 .enable_mask = BIT(0), 1540 1522 .hw.init = &(struct clk_init_data){ 1541 1523 .name = "gcc_gp2_clk", 1542 - .parent_names = (const char *[]){ 1543 - "gp2_clk_src", 1524 + .parent_hws = (const struct clk_hw*[]) { 1525 + &gp2_clk_src.clkr.hw, 1544 1526 }, 1545 1527 .num_parents = 1, 1546 1528 .flags = CLK_SET_RATE_PARENT, ··· 1557 1539 .enable_mask = BIT(0), 1558 1540 .hw.init = &(struct clk_init_data){ 1559 1541 .name = "gcc_gp3_clk", 1560 - .parent_names = (const char *[]){ 1561 - "gp3_clk_src", 1542 + .parent_hws = (const struct clk_hw*[]) { 1543 + &gp3_clk_src.clkr.hw, 1562 1544 }, 1563 1545 .num_parents = 1, 1564 1546 .flags = CLK_SET_RATE_PARENT, ··· 1602 1584 .enable_mask = BIT(4), 1603 1585 .hw.init = &(struct clk_init_data){ 1604 1586 .name = "gcc_gpu_gpll0_clk", 1605 - .parent_names = (const char *[]){ 1606 - "gpll0", 1587 + .parent_hws = (const struct clk_hw*[]) { 1588 + &gpll0.clkr.hw, 1607 1589 }, 1608 1590 .num_parents = 1, 1609 1591 .ops = &clk_branch2_ops, ··· 1619 1601 .enable_mask = BIT(3), 1620 1602 .hw.init = &(struct clk_init_data){ 1621 1603 .name = "gcc_gpu_gpll0_div_clk", 1622 - .parent_names = (const char *[]){ 1623 - "gpll0_early_div", 1604 + .parent_hws = (const struct clk_hw*[]) { 1605 + &gpll0_early_div.hw, 1624 1606 }, 1625 1607 .num_parents = 1, 1626 1608 .ops = &clk_branch2_ops, ··· 1650 1632 .enable_mask = BIT(0), 1651 1633 .hw.init = &(struct clk_init_data){ 1652 1634 .name = "gcc_hmss_rbcpr_clk", 1653 - .parent_names = (const char *[]){ 1654 - "hmss_rbcpr_clk_src", 1635 + .parent_hws = (const struct clk_hw*[]) { 1636 + &hmss_rbcpr_clk_src.clkr.hw, 1655 1637 }, 1656 1638 .num_parents = 1, 1657 1639 .flags = CLK_SET_RATE_PARENT, ··· 1668 1650 .enable_mask = BIT(1), 1669 1651 .hw.init = &(struct clk_init_data){ 1670 1652 .name = "gcc_mmss_gpll0_clk", 1671 - .parent_names = (const char *[]){ 1672 - "gpll0", 1653 + .parent_hws = (const struct clk_hw*[]) { 1654 + &gpll0.clkr.hw, 1673 1655 }, 1674 1656 .num_parents = 1, 1675 1657 .ops = &clk_branch2_ops, ··· 1685 1667 .enable_mask = BIT(0), 1686 1668 .hw.init = &(struct clk_init_data){ 1687 1669 .name = "gcc_mmss_gpll0_div_clk", 1688 - .parent_names = (const char *[]){ 1689 - "gpll0_early_div", 1670 + .parent_hws = (const struct clk_hw*[]) { 1671 + &gpll0_early_div.hw, 1690 1672 }, 1691 1673 .num_parents = 1, 1692 1674 .ops = &clk_branch2_ops, ··· 1785 1767 .enable_mask = BIT(0), 1786 1768 .hw.init = &(struct clk_init_data){ 1787 1769 .name = "gcc_pdm2_clk", 1788 - .parent_names = (const char *[]){ 1789 - "pdm2_clk_src", 1770 + .parent_hws = (const struct clk_hw*[]) { 1771 + &pdm2_clk_src.clkr.hw, 1790 1772 }, 1791 1773 .num_parents = 1, 1792 1774 .flags = CLK_SET_RATE_PARENT, ··· 1842 1824 .enable_mask = BIT(0), 1843 1825 .hw.init = &(struct clk_init_data){ 1844 1826 .name = "gcc_qspi_ser_clk", 1845 - .parent_names = (const char *[]){ 1846 - "qspi_ser_clk_src", 1827 + .parent_hws = (const struct clk_hw*[]) { 1828 + &qspi_ser_clk_src.clkr.hw, 1847 1829 }, 1848 1830 .num_parents = 1, 1849 1831 .flags = CLK_SET_RATE_PARENT, ··· 1899 1881 .enable_mask = BIT(0), 1900 1882 .hw.init = &(struct clk_init_data){ 1901 1883 .name = "gcc_sdcc1_apps_clk", 1902 - .parent_names = (const char *[]){ 1903 - "sdcc1_apps_clk_src", 1884 + .parent_hws = (const struct clk_hw*[]) { 1885 + &sdcc1_apps_clk_src.clkr.hw, 1904 1886 }, 1905 1887 .num_parents = 1, 1906 1888 .flags = CLK_SET_RATE_PARENT, ··· 1917 1899 .enable_mask = BIT(0), 1918 1900 .hw.init = &(struct clk_init_data){ 1919 1901 .name = "gcc_sdcc1_ice_core_clk", 1920 - .parent_names = (const char *[]){ 1921 - "sdcc1_ice_core_clk_src", 1902 + .parent_hws = (const struct clk_hw*[]) { 1903 + &sdcc1_ice_core_clk_src.clkr.hw, 1922 1904 }, 1923 1905 .num_parents = 1, 1924 1906 .flags = CLK_SET_RATE_PARENT, ··· 1948 1930 .enable_mask = BIT(0), 1949 1931 .hw.init = &(struct clk_init_data){ 1950 1932 .name = "gcc_sdcc2_apps_clk", 1951 - .parent_names = (const char *[]){ 1952 - "sdcc2_apps_clk_src", 1933 + .parent_hws = (const struct clk_hw*[]) { 1934 + &sdcc2_apps_clk_src.clkr.hw, 1953 1935 }, 1954 1936 .num_parents = 1, 1955 1937 .flags = CLK_SET_RATE_PARENT, ··· 1979 1961 .enable_mask = BIT(0), 1980 1962 .hw.init = &(struct clk_init_data){ 1981 1963 .name = "gcc_ufs_axi_clk", 1982 - .parent_names = (const char *[]){ 1983 - "ufs_axi_clk_src", 1964 + .parent_hws = (const struct clk_hw*[]) { 1965 + &ufs_axi_clk_src.clkr.hw, 1984 1966 }, 1985 1967 .num_parents = 1, 1986 1968 .flags = CLK_SET_RATE_PARENT, ··· 2010 1992 .enable_mask = BIT(0), 2011 1993 .hw.init = &(struct clk_init_data){ 2012 1994 .name = "gcc_ufs_ice_core_clk", 2013 - .parent_names = (const char *[]){ 2014 - "ufs_ice_core_clk_src", 1995 + .parent_hws = (const struct clk_hw*[]) { 1996 + &ufs_ice_core_clk_src.clkr.hw, 2015 1997 }, 2016 1998 .num_parents = 1, 2017 1999 .flags = CLK_SET_RATE_PARENT, ··· 2028 2010 .enable_mask = BIT(0), 2029 2011 .hw.init = &(struct clk_init_data){ 2030 2012 .name = "gcc_ufs_phy_aux_clk", 2031 - .parent_names = (const char *[]){ 2032 - "ufs_phy_aux_clk_src", 2013 + .parent_hws = (const struct clk_hw*[]) { 2014 + &ufs_phy_aux_clk_src.clkr.hw, 2033 2015 }, 2034 2016 .num_parents = 1, 2035 2017 .flags = CLK_SET_RATE_PARENT, ··· 2085 2067 .enable_mask = BIT(0), 2086 2068 .hw.init = &(struct clk_init_data){ 2087 2069 .name = "gcc_ufs_unipro_core_clk", 2088 - .parent_names = (const char *[]){ 2089 - "ufs_unipro_core_clk_src", 2070 + .parent_hws = (const struct clk_hw*[]) { 2071 + &ufs_unipro_core_clk_src.clkr.hw, 2090 2072 }, 2091 2073 .flags = CLK_SET_RATE_PARENT, 2092 2074 .num_parents = 1, ··· 2103 2085 .enable_mask = BIT(0), 2104 2086 .hw.init = &(struct clk_init_data){ 2105 2087 .name = "gcc_usb20_master_clk", 2106 - .parent_names = (const char *[]){ 2107 - "usb20_master_clk_src" 2088 + .parent_hws = (const struct clk_hw*[]) { 2089 + &usb20_master_clk_src.clkr.hw, 2108 2090 }, 2109 2091 .flags = CLK_SET_RATE_PARENT, 2110 2092 .num_parents = 1, ··· 2121 2103 .enable_mask = BIT(0), 2122 2104 .hw.init = &(struct clk_init_data){ 2123 2105 .name = "gcc_usb20_mock_utmi_clk", 2124 - .parent_names = (const char *[]){ 2125 - "usb20_mock_utmi_clk_src", 2106 + .parent_hws = (const struct clk_hw*[]) { 2107 + &usb20_mock_utmi_clk_src.clkr.hw, 2126 2108 }, 2127 2109 .num_parents = 1, 2128 2110 .flags = CLK_SET_RATE_PARENT, ··· 2152 2134 .enable_mask = BIT(0), 2153 2135 .hw.init = &(struct clk_init_data){ 2154 2136 .name = "gcc_usb30_master_clk", 2155 - .parent_names = (const char *[]){ 2156 - "usb30_master_clk_src", 2137 + .parent_hws = (const struct clk_hw*[]) { 2138 + &usb30_master_clk_src.clkr.hw, 2157 2139 }, 2158 2140 .num_parents = 1, 2159 2141 .flags = CLK_SET_RATE_PARENT, ··· 2170 2152 .enable_mask = BIT(0), 2171 2153 .hw.init = &(struct clk_init_data){ 2172 2154 .name = "gcc_usb30_mock_utmi_clk", 2173 - .parent_names = (const char *[]){ 2174 - "usb30_mock_utmi_clk_src", 2155 + .parent_hws = (const struct clk_hw*[]) { 2156 + &usb30_mock_utmi_clk_src.clkr.hw, 2175 2157 }, 2176 2158 .num_parents = 1, 2177 2159 .flags = CLK_SET_RATE_PARENT, ··· 2214 2196 .enable_mask = BIT(0), 2215 2197 .hw.init = &(struct clk_init_data){ 2216 2198 .name = "gcc_usb3_phy_aux_clk", 2217 - .parent_names = (const char *[]){ 2218 - "usb3_phy_aux_clk_src", 2199 + .parent_hws = (const struct clk_hw*[]) { 2200 + &usb3_phy_aux_clk_src.clkr.hw, 2219 2201 }, 2220 2202 .num_parents = 1, 2221 2203 .flags = CLK_SET_RATE_PARENT,