tjh.dev / kernel
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Merge branch 'net-mdio-continue-separating-c22-and-c45'

Michael Walle says:

====================
net: mdio: Continue separating C22 and C45

I've picked this older series from Andrew up and rebased it onto
the latest net-next.

This is the second patch set in the series which separates the C22
and C45 MDIO bus transactions at the API level to the MDIO bus drivers.
====================

Link: https://lore.kernel.org/r/20230112-net-next-c45-seperation-part-2-v1-0-5eeaae931526@walle.cc
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski da1b0b5c 9b7fe804

+778 -444
+4 -2
drivers/net/dsa/ocelot/felix_vsc9959.c
··· 954 954 return -ENOMEM; 955 955 956 956 bus->name = "VSC9959 internal MDIO bus"; 957 - bus->read = enetc_mdio_read; 958 - bus->write = enetc_mdio_write; 957 + bus->read = enetc_mdio_read_c22; 958 + bus->write = enetc_mdio_write_c22; 959 + bus->read_c45 = enetc_mdio_read_c45; 960 + bus->write_c45 = enetc_mdio_write_c45; 959 961 bus->parent = dev; 960 962 mdio_priv = bus->priv; 961 963 mdio_priv->hw = hw;
+93 -34
drivers/net/ethernet/freescale/enetc/enetc_mdio.c
··· 55 55 is_busy, !is_busy, 10, 10 * 1000); 56 56 } 57 57 58 - int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value) 58 + int enetc_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, 59 + u16 value) 59 60 { 60 61 struct enetc_mdio_priv *mdio_priv = bus->priv; 61 62 u32 mdio_ctl, mdio_cfg; ··· 64 63 int ret; 65 64 66 65 mdio_cfg = ENETC_EMDIO_CFG; 67 - if (regnum & MII_ADDR_C45) { 68 - dev_addr = (regnum >> 16) & 0x1f; 69 - mdio_cfg |= MDIO_CFG_ENC45; 70 - } else { 71 - /* clause 22 (ie 1G) */ 72 - dev_addr = regnum & 0x1f; 73 - mdio_cfg &= ~MDIO_CFG_ENC45; 74 - } 66 + dev_addr = regnum & 0x1f; 67 + mdio_cfg &= ~MDIO_CFG_ENC45; 68 + 69 + enetc_mdio_wr(mdio_priv, ENETC_MDIO_CFG, mdio_cfg); 70 + 71 + ret = enetc_mdio_wait_complete(mdio_priv); 72 + if (ret) 73 + return ret; 74 + 75 + /* set port and dev addr */ 76 + mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); 77 + enetc_mdio_wr(mdio_priv, ENETC_MDIO_CTL, mdio_ctl); 78 + 79 + /* write the value */ 80 + enetc_mdio_wr(mdio_priv, ENETC_MDIO_DATA, value); 81 + 82 + ret = enetc_mdio_wait_complete(mdio_priv); 83 + if (ret) 84 + return ret; 85 + 86 + return 0; 87 + } 88 + EXPORT_SYMBOL_GPL(enetc_mdio_write_c22); 89 + 90 + int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev_addr, 91 + int regnum, u16 value) 92 + { 93 + struct enetc_mdio_priv *mdio_priv = bus->priv; 94 + u32 mdio_ctl, mdio_cfg; 95 + int ret; 96 + 97 + mdio_cfg = ENETC_EMDIO_CFG; 98 + mdio_cfg |= MDIO_CFG_ENC45; 75 99 76 100 enetc_mdio_wr(mdio_priv, ENETC_MDIO_CFG, mdio_cfg); 77 101 ··· 109 83 enetc_mdio_wr(mdio_priv, ENETC_MDIO_CTL, mdio_ctl); 110 84 111 85 /* set the register address */ 112 - if (regnum & MII_ADDR_C45) { 113 - enetc_mdio_wr(mdio_priv, ENETC_MDIO_ADDR, regnum & 0xffff); 86 + enetc_mdio_wr(mdio_priv, ENETC_MDIO_ADDR, regnum & 0xffff); 114 87 115 - ret = enetc_mdio_wait_complete(mdio_priv); 116 - if (ret) 117 - return ret; 118 - } 88 + ret = enetc_mdio_wait_complete(mdio_priv); 89 + if (ret) 90 + return ret; 119 91 120 92 /* write the value */ 121 93 enetc_mdio_wr(mdio_priv, ENETC_MDIO_DATA, value); ··· 124 100 125 101 return 0; 126 102 } 127 - EXPORT_SYMBOL_GPL(enetc_mdio_write); 103 + EXPORT_SYMBOL_GPL(enetc_mdio_write_c45); 128 104 129 - int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum) 105 + int enetc_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum) 130 106 { 131 107 struct enetc_mdio_priv *mdio_priv = bus->priv; 132 108 u32 mdio_ctl, mdio_cfg; ··· 134 110 int ret; 135 111 136 112 mdio_cfg = ENETC_EMDIO_CFG; 137 - if (regnum & MII_ADDR_C45) { 138 - dev_addr = (regnum >> 16) & 0x1f; 139 - mdio_cfg |= MDIO_CFG_ENC45; 140 - } else { 141 - dev_addr = regnum & 0x1f; 142 - mdio_cfg &= ~MDIO_CFG_ENC45; 143 - } 113 + dev_addr = regnum & 0x1f; 114 + mdio_cfg &= ~MDIO_CFG_ENC45; 144 115 145 116 enetc_mdio_wr(mdio_priv, ENETC_MDIO_CFG, mdio_cfg); 146 117 ··· 146 127 /* set port and device addr */ 147 128 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); 148 129 enetc_mdio_wr(mdio_priv, ENETC_MDIO_CTL, mdio_ctl); 149 - 150 - /* set the register address */ 151 - if (regnum & MII_ADDR_C45) { 152 - enetc_mdio_wr(mdio_priv, ENETC_MDIO_ADDR, regnum & 0xffff); 153 - 154 - ret = enetc_mdio_wait_complete(mdio_priv); 155 - if (ret) 156 - return ret; 157 - } 158 130 159 131 /* initiate the read */ 160 132 enetc_mdio_wr(mdio_priv, ENETC_MDIO_CTL, mdio_ctl | MDIO_CTL_READ); ··· 166 156 167 157 return value; 168 158 } 169 - EXPORT_SYMBOL_GPL(enetc_mdio_read); 159 + EXPORT_SYMBOL_GPL(enetc_mdio_read_c22); 160 + 161 + int enetc_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr, 162 + int regnum) 163 + { 164 + struct enetc_mdio_priv *mdio_priv = bus->priv; 165 + u32 mdio_ctl, mdio_cfg; 166 + u16 value; 167 + int ret; 168 + 169 + mdio_cfg = ENETC_EMDIO_CFG; 170 + mdio_cfg |= MDIO_CFG_ENC45; 171 + 172 + enetc_mdio_wr(mdio_priv, ENETC_MDIO_CFG, mdio_cfg); 173 + 174 + ret = enetc_mdio_wait_complete(mdio_priv); 175 + if (ret) 176 + return ret; 177 + 178 + /* set port and device addr */ 179 + mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); 180 + enetc_mdio_wr(mdio_priv, ENETC_MDIO_CTL, mdio_ctl); 181 + 182 + /* set the register address */ 183 + enetc_mdio_wr(mdio_priv, ENETC_MDIO_ADDR, regnum & 0xffff); 184 + 185 + ret = enetc_mdio_wait_complete(mdio_priv); 186 + if (ret) 187 + return ret; 188 + 189 + /* initiate the read */ 190 + enetc_mdio_wr(mdio_priv, ENETC_MDIO_CTL, mdio_ctl | MDIO_CTL_READ); 191 + 192 + ret = enetc_mdio_wait_complete(mdio_priv); 193 + if (ret) 194 + return ret; 195 + 196 + /* return all Fs if nothing was there */ 197 + if (enetc_mdio_rd(mdio_priv, ENETC_MDIO_CFG) & MDIO_CFG_RD_ER) { 198 + dev_dbg(&bus->dev, 199 + "Error while reading PHY%d reg at %d.%d\n", 200 + phy_id, dev_addr, regnum); 201 + return 0xffff; 202 + } 203 + 204 + value = enetc_mdio_rd(mdio_priv, ENETC_MDIO_DATA) & 0xffff; 205 + 206 + return value; 207 + } 208 + EXPORT_SYMBOL_GPL(enetc_mdio_read_c45); 170 209 171 210 struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs) 172 211 {
+4 -2
drivers/net/ethernet/freescale/enetc/enetc_pci_mdio.c
··· 39 39 } 40 40 41 41 bus->name = ENETC_MDIO_BUS_NAME; 42 - bus->read = enetc_mdio_read; 43 - bus->write = enetc_mdio_write; 42 + bus->read = enetc_mdio_read_c22; 43 + bus->write = enetc_mdio_write_c22; 44 + bus->read_c45 = enetc_mdio_read_c45; 45 + bus->write_c45 = enetc_mdio_write_c45; 44 46 bus->parent = dev; 45 47 mdio_priv = bus->priv; 46 48 mdio_priv->hw = hw;
+8 -4
drivers/net/ethernet/freescale/enetc/enetc_pf.c
··· 848 848 return -ENOMEM; 849 849 850 850 bus->name = "Freescale ENETC MDIO Bus"; 851 - bus->read = enetc_mdio_read; 852 - bus->write = enetc_mdio_write; 851 + bus->read = enetc_mdio_read_c22; 852 + bus->write = enetc_mdio_write_c22; 853 + bus->read_c45 = enetc_mdio_read_c45; 854 + bus->write_c45 = enetc_mdio_write_c45; 853 855 bus->parent = dev; 854 856 mdio_priv = bus->priv; 855 857 mdio_priv->hw = &pf->si->hw; ··· 887 885 return -ENOMEM; 888 886 889 887 bus->name = "Freescale ENETC internal MDIO Bus"; 890 - bus->read = enetc_mdio_read; 891 - bus->write = enetc_mdio_write; 888 + bus->read = enetc_mdio_read_c22; 889 + bus->write = enetc_mdio_write_c22; 890 + bus->read_c45 = enetc_mdio_read_c45; 891 + bus->write_c45 = enetc_mdio_write_c45; 892 892 bus->parent = dev; 893 893 bus->phy_mask = ~0; 894 894 mdio_priv = bus->priv;
+111 -65
drivers/net/ethernet/mediatek/mtk_eth_soc.c
··· 215 215 return -ETIMEDOUT; 216 216 } 217 217 218 - static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 219 - u32 write_data) 218 + static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 219 + u32 write_data) 220 220 { 221 221 int ret; 222 222 ··· 224 224 if (ret < 0) 225 225 return ret; 226 226 227 - if (phy_reg & MII_ADDR_C45) { 228 - mtk_w32(eth, PHY_IAC_ACCESS | 229 - PHY_IAC_START_C45 | 230 - PHY_IAC_CMD_C45_ADDR | 231 - PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 232 - PHY_IAC_ADDR(phy_addr) | 233 - PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 234 - MTK_PHY_IAC); 235 - 236 - ret = mtk_mdio_busy_wait(eth); 237 - if (ret < 0) 238 - return ret; 239 - 240 - mtk_w32(eth, PHY_IAC_ACCESS | 241 - PHY_IAC_START_C45 | 242 - PHY_IAC_CMD_WRITE | 243 - PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 244 - PHY_IAC_ADDR(phy_addr) | 245 - PHY_IAC_DATA(write_data), 246 - MTK_PHY_IAC); 247 - } else { 248 - mtk_w32(eth, PHY_IAC_ACCESS | 249 - PHY_IAC_START_C22 | 250 - PHY_IAC_CMD_WRITE | 251 - PHY_IAC_REG(phy_reg) | 252 - PHY_IAC_ADDR(phy_addr) | 253 - PHY_IAC_DATA(write_data), 254 - MTK_PHY_IAC); 255 - } 227 + mtk_w32(eth, PHY_IAC_ACCESS | 228 + PHY_IAC_START_C22 | 229 + PHY_IAC_CMD_WRITE | 230 + PHY_IAC_REG(phy_reg) | 231 + PHY_IAC_ADDR(phy_addr) | 232 + PHY_IAC_DATA(write_data), 233 + MTK_PHY_IAC); 256 234 257 235 ret = mtk_mdio_busy_wait(eth); 258 236 if (ret < 0) ··· 239 261 return 0; 240 262 } 241 263 242 - static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 264 + static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 265 + u32 devad, u32 phy_reg, u32 write_data) 243 266 { 244 267 int ret; 245 268 ··· 248 269 if (ret < 0) 249 270 return ret; 250 271 251 - if (phy_reg & MII_ADDR_C45) { 252 - mtk_w32(eth, PHY_IAC_ACCESS | 253 - PHY_IAC_START_C45 | 254 - PHY_IAC_CMD_C45_ADDR | 255 - PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 256 - PHY_IAC_ADDR(phy_addr) | 257 - PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 258 - MTK_PHY_IAC); 272 + mtk_w32(eth, PHY_IAC_ACCESS | 273 + PHY_IAC_START_C45 | 274 + PHY_IAC_CMD_C45_ADDR | 275 + PHY_IAC_REG(devad) | 276 + PHY_IAC_ADDR(phy_addr) | 277 + PHY_IAC_DATA(phy_reg), 278 + MTK_PHY_IAC); 259 279 260 - ret = mtk_mdio_busy_wait(eth); 261 - if (ret < 0) 262 - return ret; 280 + ret = mtk_mdio_busy_wait(eth); 281 + if (ret < 0) 282 + return ret; 263 283 264 - mtk_w32(eth, PHY_IAC_ACCESS | 265 - PHY_IAC_START_C45 | 266 - PHY_IAC_CMD_C45_READ | 267 - PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 268 - PHY_IAC_ADDR(phy_addr), 269 - MTK_PHY_IAC); 270 - } else { 271 - mtk_w32(eth, PHY_IAC_ACCESS | 272 - PHY_IAC_START_C22 | 273 - PHY_IAC_CMD_C22_READ | 274 - PHY_IAC_REG(phy_reg) | 275 - PHY_IAC_ADDR(phy_addr), 276 - MTK_PHY_IAC); 277 - } 284 + mtk_w32(eth, PHY_IAC_ACCESS | 285 + PHY_IAC_START_C45 | 286 + PHY_IAC_CMD_WRITE | 287 + PHY_IAC_REG(devad) | 288 + PHY_IAC_ADDR(phy_addr) | 289 + PHY_IAC_DATA(write_data), 290 + MTK_PHY_IAC); 291 + 292 + ret = mtk_mdio_busy_wait(eth); 293 + if (ret < 0) 294 + return ret; 295 + 296 + return 0; 297 + } 298 + 299 + static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 300 + { 301 + int ret; 302 + 303 + ret = mtk_mdio_busy_wait(eth); 304 + if (ret < 0) 305 + return ret; 306 + 307 + mtk_w32(eth, PHY_IAC_ACCESS | 308 + PHY_IAC_START_C22 | 309 + PHY_IAC_CMD_C22_READ | 310 + PHY_IAC_REG(phy_reg) | 311 + PHY_IAC_ADDR(phy_addr), 312 + MTK_PHY_IAC); 278 313 279 314 ret = mtk_mdio_busy_wait(eth); 280 315 if (ret < 0) ··· 297 304 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 298 305 } 299 306 300 - static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 301 - int phy_reg, u16 val) 307 + static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 308 + u32 devad, u32 phy_reg) 302 309 { 303 - struct mtk_eth *eth = bus->priv; 310 + int ret; 304 311 305 - return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 312 + ret = mtk_mdio_busy_wait(eth); 313 + if (ret < 0) 314 + return ret; 315 + 316 + mtk_w32(eth, PHY_IAC_ACCESS | 317 + PHY_IAC_START_C45 | 318 + PHY_IAC_CMD_C45_ADDR | 319 + PHY_IAC_REG(devad) | 320 + PHY_IAC_ADDR(phy_addr) | 321 + PHY_IAC_DATA(phy_reg), 322 + MTK_PHY_IAC); 323 + 324 + ret = mtk_mdio_busy_wait(eth); 325 + if (ret < 0) 326 + return ret; 327 + 328 + mtk_w32(eth, PHY_IAC_ACCESS | 329 + PHY_IAC_START_C45 | 330 + PHY_IAC_CMD_C45_READ | 331 + PHY_IAC_REG(devad) | 332 + PHY_IAC_ADDR(phy_addr), 333 + MTK_PHY_IAC); 334 + 335 + ret = mtk_mdio_busy_wait(eth); 336 + if (ret < 0) 337 + return ret; 338 + 339 + return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 306 340 } 307 341 308 - static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 342 + static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 343 + int phy_reg, u16 val) 309 344 { 310 345 struct mtk_eth *eth = bus->priv; 311 346 312 - return _mtk_mdio_read(eth, phy_addr, phy_reg); 347 + return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 348 + } 349 + 350 + static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 351 + int devad, int phy_reg, u16 val) 352 + { 353 + struct mtk_eth *eth = bus->priv; 354 + 355 + return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 356 + } 357 + 358 + static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 359 + { 360 + struct mtk_eth *eth = bus->priv; 361 + 362 + return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 363 + } 364 + 365 + static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 366 + int phy_reg) 367 + { 368 + struct mtk_eth *eth = bus->priv; 369 + 370 + return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 313 371 } 314 372 315 373 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, ··· 804 760 } 805 761 806 762 eth->mii_bus->name = "mdio"; 807 - eth->mii_bus->read = mtk_mdio_read; 808 - eth->mii_bus->write = mtk_mdio_write; 763 + eth->mii_bus->read = mtk_mdio_read_c22; 764 + eth->mii_bus->write = mtk_mdio_write_c22; 765 + eth->mii_bus->read_c45 = mtk_mdio_read_c45; 766 + eth->mii_bus->write_c45 = mtk_mdio_write_c45; 809 767 eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; 810 768 eth->mii_bus->priv = eth; 811 769 eth->mii_bus->parent = eth->dev;
+51 -55
drivers/net/ethernet/microchip/lan743x_main.c
··· 792 792 !(data & MAC_MII_ACC_MII_BUSY_), 0, 1000000); 793 793 } 794 794 795 - static int lan743x_mdiobus_read(struct mii_bus *bus, int phy_id, int index) 795 + static int lan743x_mdiobus_read_c22(struct mii_bus *bus, int phy_id, int index) 796 796 { 797 797 struct lan743x_adapter *adapter = bus->priv; 798 798 u32 val, mii_access; ··· 814 814 return (int)(val & 0xFFFF); 815 815 } 816 816 817 - static int lan743x_mdiobus_write(struct mii_bus *bus, 818 - int phy_id, int index, u16 regval) 817 + static int lan743x_mdiobus_write_c22(struct mii_bus *bus, 818 + int phy_id, int index, u16 regval) 819 819 { 820 820 struct lan743x_adapter *adapter = bus->priv; 821 821 u32 val, mii_access; ··· 835 835 return ret; 836 836 } 837 837 838 - static u32 lan743x_mac_mmd_access(int id, int index, int op) 838 + static u32 lan743x_mac_mmd_access(int id, int dev_addr, int op) 839 839 { 840 - u16 dev_addr; 841 840 u32 ret; 842 841 843 - dev_addr = (index >> 16) & 0x1f; 844 842 ret = (id << MAC_MII_ACC_PHY_ADDR_SHIFT_) & 845 843 MAC_MII_ACC_PHY_ADDR_MASK_; 846 844 ret |= (dev_addr << MAC_MII_ACC_MIIMMD_SHIFT_) & ··· 856 858 return ret; 857 859 } 858 860 859 - static int lan743x_mdiobus_c45_read(struct mii_bus *bus, int phy_id, int index) 861 + static int lan743x_mdiobus_read_c45(struct mii_bus *bus, int phy_id, 862 + int dev_addr, int index) 860 863 { 861 864 struct lan743x_adapter *adapter = bus->priv; 862 865 u32 mmd_access; ··· 867 868 ret = lan743x_mac_mii_wait_till_not_busy(adapter); 868 869 if (ret < 0) 869 870 return ret; 870 - if (index & MII_ADDR_C45) { 871 - /* Load Register Address */ 872 - lan743x_csr_write(adapter, MAC_MII_DATA, (u32)(index & 0xffff)); 873 - mmd_access = lan743x_mac_mmd_access(phy_id, index, 874 - MMD_ACCESS_ADDRESS); 875 - lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access); 876 - ret = lan743x_mac_mii_wait_till_not_busy(adapter); 877 - if (ret < 0) 878 - return ret; 879 - /* Read Data */ 880 - mmd_access = lan743x_mac_mmd_access(phy_id, index, 881 - MMD_ACCESS_READ); 882 - lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access); 883 - ret = lan743x_mac_mii_wait_till_not_busy(adapter); 884 - if (ret < 0) 885 - return ret; 886 - ret = lan743x_csr_read(adapter, MAC_MII_DATA); 887 - return (int)(ret & 0xFFFF); 888 - } 889 871 890 - ret = lan743x_mdiobus_read(bus, phy_id, index); 891 - return ret; 872 + /* Load Register Address */ 873 + lan743x_csr_write(adapter, MAC_MII_DATA, index); 874 + mmd_access = lan743x_mac_mmd_access(phy_id, dev_addr, 875 + MMD_ACCESS_ADDRESS); 876 + lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access); 877 + ret = lan743x_mac_mii_wait_till_not_busy(adapter); 878 + if (ret < 0) 879 + return ret; 880 + 881 + /* Read Data */ 882 + mmd_access = lan743x_mac_mmd_access(phy_id, dev_addr, 883 + MMD_ACCESS_READ); 884 + lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access); 885 + ret = lan743x_mac_mii_wait_till_not_busy(adapter); 886 + if (ret < 0) 887 + return ret; 888 + 889 + ret = lan743x_csr_read(adapter, MAC_MII_DATA); 890 + return (int)(ret & 0xFFFF); 892 891 } 893 892 894 - static int lan743x_mdiobus_c45_write(struct mii_bus *bus, 895 - int phy_id, int index, u16 regval) 893 + static int lan743x_mdiobus_write_c45(struct mii_bus *bus, int phy_id, 894 + int dev_addr, int index, u16 regval) 896 895 { 897 896 struct lan743x_adapter *adapter = bus->priv; 898 897 u32 mmd_access; ··· 900 903 ret = lan743x_mac_mii_wait_till_not_busy(adapter); 901 904 if (ret < 0) 902 905 return ret; 903 - if (index & MII_ADDR_C45) { 904 - /* Load Register Address */ 905 - lan743x_csr_write(adapter, MAC_MII_DATA, (u32)(index & 0xffff)); 906 - mmd_access = lan743x_mac_mmd_access(phy_id, index, 907 - MMD_ACCESS_ADDRESS); 908 - lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access); 909 - ret = lan743x_mac_mii_wait_till_not_busy(adapter); 910 - if (ret < 0) 911 - return ret; 912 - /* Write Data */ 913 - lan743x_csr_write(adapter, MAC_MII_DATA, (u32)regval); 914 - mmd_access = lan743x_mac_mmd_access(phy_id, index, 915 - MMD_ACCESS_WRITE); 916 - lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access); 917 - ret = lan743x_mac_mii_wait_till_not_busy(adapter); 918 - } else { 919 - ret = lan743x_mdiobus_write(bus, phy_id, index, regval); 920 - } 921 906 922 - return ret; 907 + /* Load Register Address */ 908 + lan743x_csr_write(adapter, MAC_MII_DATA, (u32)index); 909 + mmd_access = lan743x_mac_mmd_access(phy_id, dev_addr, 910 + MMD_ACCESS_ADDRESS); 911 + lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access); 912 + ret = lan743x_mac_mii_wait_till_not_busy(adapter); 913 + if (ret < 0) 914 + return ret; 915 + 916 + /* Write Data */ 917 + lan743x_csr_write(adapter, MAC_MII_DATA, (u32)regval); 918 + mmd_access = lan743x_mac_mmd_access(phy_id, dev_addr, 919 + MMD_ACCESS_WRITE); 920 + lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access); 921 + 922 + return lan743x_mac_mii_wait_till_not_busy(adapter); 923 923 } 924 924 925 925 static int lan743x_sgmii_wait_till_not_busy(struct lan743x_adapter *adapter) ··· 3280 3286 netif_dbg(adapter, drv, adapter->netdev, 3281 3287 "SGMII operation\n"); 3282 3288 adapter->mdiobus->probe_capabilities = MDIOBUS_C22_C45; 3283 - adapter->mdiobus->read = lan743x_mdiobus_c45_read; 3284 - adapter->mdiobus->write = lan743x_mdiobus_c45_write; 3289 + adapter->mdiobus->read = lan743x_mdiobus_read_c22; 3290 + adapter->mdiobus->write = lan743x_mdiobus_write_c22; 3291 + adapter->mdiobus->read_c45 = lan743x_mdiobus_read_c45; 3292 + adapter->mdiobus->write_c45 = lan743x_mdiobus_write_c45; 3285 3293 adapter->mdiobus->name = "lan743x-mdiobus-c45"; 3286 3294 netif_dbg(adapter, drv, adapter->netdev, 3287 3295 "lan743x-mdiobus-c45\n"); ··· 3296 3300 "RGMII operation\n"); 3297 3301 // Only C22 support when RGMII I/F 3298 3302 adapter->mdiobus->probe_capabilities = MDIOBUS_C22; 3299 - adapter->mdiobus->read = lan743x_mdiobus_read; 3300 - adapter->mdiobus->write = lan743x_mdiobus_write; 3303 + adapter->mdiobus->read = lan743x_mdiobus_read_c22; 3304 + adapter->mdiobus->write = lan743x_mdiobus_write_c22; 3301 3305 adapter->mdiobus->name = "lan743x-mdiobus"; 3302 3306 netif_dbg(adapter, drv, adapter->netdev, 3303 3307 "lan743x-mdiobus\n"); 3304 3308 } 3305 3309 } else { 3306 - adapter->mdiobus->read = lan743x_mdiobus_read; 3307 - adapter->mdiobus->write = lan743x_mdiobus_write; 3310 + adapter->mdiobus->read = lan743x_mdiobus_read_c22; 3311 + adapter->mdiobus->write = lan743x_mdiobus_write_c22; 3308 3312 adapter->mdiobus->name = "lan743x-mdiobus"; 3309 3313 netif_dbg(adapter, drv, adapter->netdev, "lan743x-mdiobus\n"); 3310 3314 }
+223 -116
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
··· 45 45 #define MII_XGMAC_PA_SHIFT 16 46 46 #define MII_XGMAC_DA_SHIFT 21 47 47 48 - static int stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr, 49 - int phyreg, u32 *hw_addr) 48 + static void stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr, 49 + int devad, int phyreg, u32 *hw_addr) 50 50 { 51 51 u32 tmp; 52 52 ··· 56 56 writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); 57 57 58 58 *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff); 59 - *hw_addr |= (phyreg >> MII_DEVADDR_C45_SHIFT) << MII_XGMAC_DA_SHIFT; 60 - return 0; 59 + *hw_addr |= devad << MII_XGMAC_DA_SHIFT; 61 60 } 62 61 63 - static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr, 64 - int phyreg, u32 *hw_addr) 62 + static void stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr, 63 + int phyreg, u32 *hw_addr) 65 64 { 66 65 u32 tmp; 67 - 68 - /* HW does not support C22 addr >= 4 */ 69 - if (phyaddr > MII_XGMAC_MAX_C22ADDR) 70 - return -ENODEV; 71 66 72 67 /* Set port as Clause 22 */ 73 68 tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P); ··· 71 76 writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); 72 77 73 78 *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f); 74 - return 0; 75 79 } 76 80 77 - static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) 81 + static int stmmac_xgmac2_mdio_read(struct stmmac_priv *priv, u32 addr, 82 + u32 value) 78 83 { 79 - struct net_device *ndev = bus->priv; 80 - struct stmmac_priv *priv = netdev_priv(ndev); 81 84 unsigned int mii_address = priv->hw->mii.addr; 82 85 unsigned int mii_data = priv->hw->mii.data; 83 - u32 tmp, addr, value = MII_XGMAC_BUSY; 86 + u32 tmp; 84 87 int ret; 85 88 86 89 ret = pm_runtime_resume_and_get(priv->device); ··· 90 97 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 91 98 ret = -EBUSY; 92 99 goto err_disable_clks; 93 - } 94 - 95 - if (phyreg & MII_ADDR_C45) { 96 - phyreg &= ~MII_ADDR_C45; 97 - 98 - ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr); 99 - if (ret) 100 - goto err_disable_clks; 101 - } else { 102 - ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); 103 - if (ret) 104 - goto err_disable_clks; 105 - 106 - value |= MII_XGMAC_SADDR; 107 100 } 108 101 109 102 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) ··· 123 144 return ret; 124 145 } 125 146 126 - static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr, 127 - int phyreg, u16 phydata) 147 + static int stmmac_xgmac2_mdio_read_c22(struct mii_bus *bus, int phyaddr, 148 + int phyreg) 128 149 { 129 150 struct net_device *ndev = bus->priv; 130 - struct stmmac_priv *priv = netdev_priv(ndev); 151 + struct stmmac_priv *priv; 152 + u32 addr; 153 + 154 + priv = netdev_priv(ndev); 155 + 156 + /* HW does not support C22 addr >= 4 */ 157 + if (phyaddr > MII_XGMAC_MAX_C22ADDR) 158 + return -ENODEV; 159 + 160 + stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); 161 + 162 + return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY); 163 + } 164 + 165 + static int stmmac_xgmac2_mdio_read_c45(struct mii_bus *bus, int phyaddr, 166 + int devad, int phyreg) 167 + { 168 + struct net_device *ndev = bus->priv; 169 + struct stmmac_priv *priv; 170 + u32 addr; 171 + 172 + priv = netdev_priv(ndev); 173 + 174 + stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr); 175 + 176 + return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY); 177 + } 178 + 179 + static int stmmac_xgmac2_mdio_write(struct stmmac_priv *priv, u32 addr, 180 + u32 value, u16 phydata) 181 + { 131 182 unsigned int mii_address = priv->hw->mii.addr; 132 183 unsigned int mii_data = priv->hw->mii.data; 133 - u32 addr, tmp, value = MII_XGMAC_BUSY; 184 + u32 tmp; 134 185 int ret; 135 186 136 187 ret = pm_runtime_resume_and_get(priv->device); ··· 172 163 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 173 164 ret = -EBUSY; 174 165 goto err_disable_clks; 175 - } 176 - 177 - if (phyreg & MII_ADDR_C45) { 178 - phyreg &= ~MII_ADDR_C45; 179 - 180 - ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr); 181 - if (ret) 182 - goto err_disable_clks; 183 - } else { 184 - ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); 185 - if (ret) 186 - goto err_disable_clks; 187 - 188 - value |= MII_XGMAC_SADDR; 189 166 } 190 167 191 168 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) ··· 200 205 return ret; 201 206 } 202 207 208 + static int stmmac_xgmac2_mdio_write_c22(struct mii_bus *bus, int phyaddr, 209 + int phyreg, u16 phydata) 210 + { 211 + struct net_device *ndev = bus->priv; 212 + struct stmmac_priv *priv; 213 + u32 addr; 214 + 215 + priv = netdev_priv(ndev); 216 + 217 + /* HW does not support C22 addr >= 4 */ 218 + if (phyaddr > MII_XGMAC_MAX_C22ADDR) 219 + return -ENODEV; 220 + 221 + stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); 222 + 223 + return stmmac_xgmac2_mdio_write(priv, addr, 224 + MII_XGMAC_BUSY | MII_XGMAC_SADDR, phydata); 225 + } 226 + 227 + static int stmmac_xgmac2_mdio_write_c45(struct mii_bus *bus, int phyaddr, 228 + int devad, int phyreg, u16 phydata) 229 + { 230 + struct net_device *ndev = bus->priv; 231 + struct stmmac_priv *priv; 232 + u32 addr; 233 + 234 + priv = netdev_priv(ndev); 235 + 236 + stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr); 237 + 238 + return stmmac_xgmac2_mdio_write(priv, addr, MII_XGMAC_BUSY, 239 + phydata); 240 + } 241 + 242 + static int stmmac_mdio_read(struct stmmac_priv *priv, int data, u32 value) 243 + { 244 + unsigned int mii_address = priv->hw->mii.addr; 245 + unsigned int mii_data = priv->hw->mii.data; 246 + u32 v; 247 + 248 + if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 249 + 100, 10000)) 250 + return -EBUSY; 251 + 252 + writel(data, priv->ioaddr + mii_data); 253 + writel(value, priv->ioaddr + mii_address); 254 + 255 + if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 256 + 100, 10000)) 257 + return -EBUSY; 258 + 259 + /* Read the data from the MII data register */ 260 + return readl(priv->ioaddr + mii_data) & MII_DATA_MASK; 261 + } 262 + 203 263 /** 204 - * stmmac_mdio_read 264 + * stmmac_mdio_read_c22 205 265 * @bus: points to the mii_bus structure 206 266 * @phyaddr: MII addr 207 267 * @phyreg: MII reg ··· 265 215 * accessing the PHY registers. 266 216 * Fortunately, it seems this has no drawback for the 7109 MAC. 267 217 */ 268 - static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) 218 + static int stmmac_mdio_read_c22(struct mii_bus *bus, int phyaddr, int phyreg) 269 219 { 270 220 struct net_device *ndev = bus->priv; 271 221 struct stmmac_priv *priv = netdev_priv(ndev); 272 - unsigned int mii_address = priv->hw->mii.addr; 273 - unsigned int mii_data = priv->hw->mii.data; 274 222 u32 value = MII_BUSY; 275 223 int data = 0; 276 - u32 v; 277 224 278 225 data = pm_runtime_resume_and_get(priv->device); 279 226 if (data < 0) ··· 283 236 & priv->hw->mii.clk_csr_mask; 284 237 if (priv->plat->has_gmac4) { 285 238 value |= MII_GMAC4_READ; 286 - if (phyreg & MII_ADDR_C45) { 287 - value |= MII_GMAC4_C45E; 288 - value &= ~priv->hw->mii.reg_mask; 289 - value |= ((phyreg >> MII_DEVADDR_C45_SHIFT) << 290 - priv->hw->mii.reg_shift) & 291 - priv->hw->mii.reg_mask; 292 - 293 - data |= (phyreg & MII_REGADDR_C45_MASK) << 294 - MII_GMAC4_REG_ADDR_SHIFT; 295 - } 296 239 } 297 240 298 - if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 299 - 100, 10000)) { 300 - data = -EBUSY; 301 - goto err_disable_clks; 302 - } 241 + data = stmmac_mdio_read(priv, data, value); 303 242 304 - writel(data, priv->ioaddr + mii_data); 305 - writel(value, priv->ioaddr + mii_address); 306 - 307 - if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 308 - 100, 10000)) { 309 - data = -EBUSY; 310 - goto err_disable_clks; 311 - } 312 - 313 - /* Read the data from the MII data register */ 314 - data = (int)readl(priv->ioaddr + mii_data) & MII_DATA_MASK; 315 - 316 - err_disable_clks: 317 243 pm_runtime_put(priv->device); 318 244 319 245 return data; 320 246 } 321 247 322 248 /** 323 - * stmmac_mdio_write 249 + * stmmac_mdio_read_c45 250 + * @bus: points to the mii_bus structure 251 + * @phyaddr: MII addr 252 + * @devad: device address to read 253 + * @phyreg: MII reg 254 + * Description: it reads data from the MII register from within the phy device. 255 + * For the 7111 GMAC, we must set the bit 0 in the MII address register while 256 + * accessing the PHY registers. 257 + * Fortunately, it seems this has no drawback for the 7109 MAC. 258 + */ 259 + static int stmmac_mdio_read_c45(struct mii_bus *bus, int phyaddr, int devad, 260 + int phyreg) 261 + { 262 + struct net_device *ndev = bus->priv; 263 + struct stmmac_priv *priv = netdev_priv(ndev); 264 + u32 value = MII_BUSY; 265 + int data = 0; 266 + 267 + data = pm_runtime_get_sync(priv->device); 268 + if (data < 0) { 269 + pm_runtime_put_noidle(priv->device); 270 + return data; 271 + } 272 + 273 + value |= (phyaddr << priv->hw->mii.addr_shift) 274 + & priv->hw->mii.addr_mask; 275 + value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 276 + value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 277 + & priv->hw->mii.clk_csr_mask; 278 + value |= MII_GMAC4_READ; 279 + value |= MII_GMAC4_C45E; 280 + value &= ~priv->hw->mii.reg_mask; 281 + value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 282 + 283 + data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT; 284 + 285 + data = stmmac_mdio_read(priv, data, value); 286 + 287 + pm_runtime_put(priv->device); 288 + 289 + return data; 290 + } 291 + 292 + static int stmmac_mdio_write(struct stmmac_priv *priv, int data, u32 value) 293 + { 294 + unsigned int mii_address = priv->hw->mii.addr; 295 + unsigned int mii_data = priv->hw->mii.data; 296 + u32 v; 297 + 298 + /* Wait until any existing MII operation is complete */ 299 + if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 300 + 100, 10000)) 301 + return -EBUSY; 302 + 303 + /* Set the MII address register to write */ 304 + writel(data, priv->ioaddr + mii_data); 305 + writel(value, priv->ioaddr + mii_address); 306 + 307 + /* Wait until any existing MII operation is complete */ 308 + return readl_poll_timeout(priv->ioaddr + mii_address, v, 309 + !(v & MII_BUSY), 100, 10000); 310 + } 311 + 312 + /** 313 + * stmmac_mdio_write_c22 324 314 * @bus: points to the mii_bus structure 325 315 * @phyaddr: MII addr 326 316 * @phyreg: MII reg 327 317 * @phydata: phy data 328 318 * Description: it writes the data into the MII register from within the device. 329 319 */ 330 - static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, 331 - u16 phydata) 320 + static int stmmac_mdio_write_c22(struct mii_bus *bus, int phyaddr, int phyreg, 321 + u16 phydata) 332 322 { 333 323 struct net_device *ndev = bus->priv; 334 324 struct stmmac_priv *priv = netdev_priv(ndev); 335 - unsigned int mii_address = priv->hw->mii.addr; 336 - unsigned int mii_data = priv->hw->mii.data; 337 325 int ret, data = phydata; 338 326 u32 value = MII_BUSY; 339 - u32 v; 340 327 341 328 ret = pm_runtime_resume_and_get(priv->device); 342 329 if (ret < 0) ··· 382 301 383 302 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 384 303 & priv->hw->mii.clk_csr_mask; 385 - if (priv->plat->has_gmac4) { 304 + if (priv->plat->has_gmac4) 386 305 value |= MII_GMAC4_WRITE; 387 - if (phyreg & MII_ADDR_C45) { 388 - value |= MII_GMAC4_C45E; 389 - value &= ~priv->hw->mii.reg_mask; 390 - value |= ((phyreg >> MII_DEVADDR_C45_SHIFT) << 391 - priv->hw->mii.reg_shift) & 392 - priv->hw->mii.reg_mask; 393 - 394 - data |= (phyreg & MII_REGADDR_C45_MASK) << 395 - MII_GMAC4_REG_ADDR_SHIFT; 396 - } 397 - } else { 306 + else 398 307 value |= MII_WRITE; 308 + 309 + ret = stmmac_mdio_write(priv, data, value); 310 + 311 + pm_runtime_put(priv->device); 312 + 313 + return ret; 314 + } 315 + 316 + /** 317 + * stmmac_mdio_write_c45 318 + * @bus: points to the mii_bus structure 319 + * @phyaddr: MII addr 320 + * @phyreg: MII reg 321 + * @devad: device address to read 322 + * @phydata: phy data 323 + * Description: it writes the data into the MII register from within the device. 324 + */ 325 + static int stmmac_mdio_write_c45(struct mii_bus *bus, int phyaddr, 326 + int devad, int phyreg, u16 phydata) 327 + { 328 + struct net_device *ndev = bus->priv; 329 + struct stmmac_priv *priv = netdev_priv(ndev); 330 + int ret, data = phydata; 331 + u32 value = MII_BUSY; 332 + 333 + ret = pm_runtime_get_sync(priv->device); 334 + if (ret < 0) { 335 + pm_runtime_put_noidle(priv->device); 336 + return ret; 399 337 } 400 338 401 - /* Wait until any existing MII operation is complete */ 402 - if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 403 - 100, 10000)) { 404 - ret = -EBUSY; 405 - goto err_disable_clks; 406 - } 339 + value |= (phyaddr << priv->hw->mii.addr_shift) 340 + & priv->hw->mii.addr_mask; 341 + value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 407 342 408 - /* Set the MII address register to write */ 409 - writel(data, priv->ioaddr + mii_data); 410 - writel(value, priv->ioaddr + mii_address); 343 + value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 344 + & priv->hw->mii.clk_csr_mask; 411 345 412 - /* Wait until any existing MII operation is complete */ 413 - ret = readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 414 - 100, 10000); 346 + value |= MII_GMAC4_WRITE; 347 + value |= MII_GMAC4_C45E; 348 + value &= ~priv->hw->mii.reg_mask; 349 + value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 415 350 416 - err_disable_clks: 351 + data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT; 352 + 353 + ret = stmmac_mdio_write(priv, data, value); 354 + 417 355 pm_runtime_put(priv->device); 418 356 419 357 return ret; ··· 557 457 new_bus->probe_capabilities = MDIOBUS_C22_C45; 558 458 559 459 if (priv->plat->has_xgmac) { 560 - new_bus->read = &stmmac_xgmac2_mdio_read; 561 - new_bus->write = &stmmac_xgmac2_mdio_write; 460 + new_bus->read = &stmmac_xgmac2_mdio_read_c22; 461 + new_bus->write = &stmmac_xgmac2_mdio_write_c22; 462 + new_bus->read_c45 = &stmmac_xgmac2_mdio_read_c45; 463 + new_bus->write_c45 = &stmmac_xgmac2_mdio_write_c45; 562 464 563 465 /* Right now only C22 phys are supported */ 564 466 max_addr = MII_XGMAC_MAX_C22ADDR + 1; ··· 570 468 dev_err(dev, "Unsupported phy_addr (max=%d)\n", 571 469 MII_XGMAC_MAX_C22ADDR); 572 470 } else { 573 - new_bus->read = &stmmac_mdio_read; 574 - new_bus->write = &stmmac_mdio_write; 471 + new_bus->read = &stmmac_mdio_read_c22; 472 + new_bus->write = &stmmac_mdio_write_c22; 473 + if (priv->plat->has_gmac4) { 474 + new_bus->read_c45 = &stmmac_mdio_read_c45; 475 + new_bus->write_c45 = &stmmac_mdio_write_c45; 476 + } 477 + 575 478 max_addr = PHY_MAX_ADDR; 576 479 } 577 480 ··· 597 490 598 491 /* Looks like we need a dummy read for XGMAC only and C45 PHYs */ 599 492 if (priv->plat->has_xgmac) 600 - stmmac_xgmac2_mdio_read(new_bus, 0, MII_ADDR_C45); 493 + stmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0); 601 494 602 495 /* If fixed-link is set, skip PHY scanning */ 603 496 if (!fwnode)
+12 -35
drivers/net/mdio/mdio-aspeed.c
··· 104 104 addr, regnum, val); 105 105 } 106 106 107 - static int aspeed_mdio_read_c45(struct mii_bus *bus, int addr, int regnum) 107 + static int aspeed_mdio_read_c45(struct mii_bus *bus, int addr, int devad, 108 + int regnum) 108 109 { 109 - u8 c45_dev = (regnum >> 16) & 0x1F; 110 - u16 c45_addr = regnum & 0xFFFF; 111 110 int rc; 112 111 113 112 rc = aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_ADDR, 114 - addr, c45_dev, c45_addr); 113 + addr, devad, regnum); 115 114 if (rc < 0) 116 115 return rc; 117 116 118 117 rc = aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_READ, 119 - addr, c45_dev, 0); 118 + addr, devad, 0); 120 119 if (rc < 0) 121 120 return rc; 122 121 123 122 return aspeed_mdio_get_data(bus); 124 123 } 125 124 126 - static int aspeed_mdio_write_c45(struct mii_bus *bus, int addr, int regnum, 127 - u16 val) 125 + static int aspeed_mdio_write_c45(struct mii_bus *bus, int addr, int devad, 126 + int regnum, u16 val) 128 127 { 129 - u8 c45_dev = (regnum >> 16) & 0x1F; 130 - u16 c45_addr = regnum & 0xFFFF; 131 128 int rc; 132 129 133 130 rc = aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_ADDR, 134 - addr, c45_dev, c45_addr); 131 + addr, devad, regnum); 135 132 if (rc < 0) 136 133 return rc; 137 134 138 135 return aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_WRITE, 139 - addr, c45_dev, val); 140 - } 141 - 142 - static int aspeed_mdio_read(struct mii_bus *bus, int addr, int regnum) 143 - { 144 - dev_dbg(&bus->dev, "%s: addr: %d, regnum: %d\n", __func__, addr, 145 - regnum); 146 - 147 - if (regnum & MII_ADDR_C45) 148 - return aspeed_mdio_read_c45(bus, addr, regnum); 149 - 150 - return aspeed_mdio_read_c22(bus, addr, regnum); 151 - } 152 - 153 - static int aspeed_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) 154 - { 155 - dev_dbg(&bus->dev, "%s: addr: %d, regnum: %d, val: 0x%x\n", 156 - __func__, addr, regnum, val); 157 - 158 - if (regnum & MII_ADDR_C45) 159 - return aspeed_mdio_write_c45(bus, addr, regnum, val); 160 - 161 - return aspeed_mdio_write_c22(bus, addr, regnum, val); 136 + addr, devad, val); 162 137 } 163 138 164 139 static int aspeed_mdio_probe(struct platform_device *pdev) ··· 160 185 bus->name = DRV_NAME; 161 186 snprintf(bus->id, MII_BUS_ID_SIZE, "%s%d", pdev->name, pdev->id); 162 187 bus->parent = &pdev->dev; 163 - bus->read = aspeed_mdio_read; 164 - bus->write = aspeed_mdio_write; 188 + bus->read = aspeed_mdio_read_c22; 189 + bus->write = aspeed_mdio_write_c22; 190 + bus->read_c45 = aspeed_mdio_read_c45; 191 + bus->write_c45 = aspeed_mdio_write_c45; 165 192 bus->probe_capabilities = MDIOBUS_C22_C45; 166 193 167 194 rc = of_mdiobus_register(bus, pdev->dev.of_node);
+83 -34
drivers/net/mdio/mdio-cavium.c
··· 26 26 } 27 27 28 28 static int cavium_mdiobus_c45_addr(struct cavium_mdiobus *p, 29 - int phy_id, int regnum) 29 + int phy_id, int devad, int regnum) 30 30 { 31 31 union cvmx_smix_cmd smi_cmd; 32 32 union cvmx_smix_wr_dat smi_wr; ··· 38 38 smi_wr.s.dat = regnum & 0xffff; 39 39 oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); 40 40 41 - regnum = (regnum >> 16) & 0x1f; 42 - 43 41 smi_cmd.u64 = 0; 44 42 smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */ 45 43 smi_cmd.s.phy_adr = phy_id; 46 - smi_cmd.s.reg_adr = regnum; 44 + smi_cmd.s.reg_adr = devad; 47 45 oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); 48 46 49 47 do { ··· 57 59 return 0; 58 60 } 59 61 60 - int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum) 62 + int cavium_mdiobus_read_c22(struct mii_bus *bus, int phy_id, int regnum) 61 63 { 62 64 struct cavium_mdiobus *p = bus->priv; 63 65 union cvmx_smix_cmd smi_cmd; 64 66 union cvmx_smix_rd_dat smi_rd; 65 - unsigned int op = 1; /* MDIO_CLAUSE_22_READ */ 66 67 int timeout = 1000; 67 68 68 - if (regnum & MII_ADDR_C45) { 69 - int r = cavium_mdiobus_c45_addr(p, phy_id, regnum); 70 - 71 - if (r < 0) 72 - return r; 73 - 74 - regnum = (regnum >> 16) & 0x1f; 75 - op = 3; /* MDIO_CLAUSE_45_READ */ 76 - } else { 77 - cavium_mdiobus_set_mode(p, C22); 78 - } 69 + cavium_mdiobus_set_mode(p, C22); 79 70 80 71 smi_cmd.u64 = 0; 81 - smi_cmd.s.phy_op = op; 72 + smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */; 82 73 smi_cmd.s.phy_adr = phy_id; 83 74 smi_cmd.s.reg_adr = regnum; 84 75 oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); ··· 85 98 else 86 99 return -EIO; 87 100 } 88 - EXPORT_SYMBOL(cavium_mdiobus_read); 101 + EXPORT_SYMBOL(cavium_mdiobus_read_c22); 89 102 90 - int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val) 103 + int cavium_mdiobus_read_c45(struct mii_bus *bus, int phy_id, int devad, 104 + int regnum) 105 + { 106 + struct cavium_mdiobus *p = bus->priv; 107 + union cvmx_smix_cmd smi_cmd; 108 + union cvmx_smix_rd_dat smi_rd; 109 + int timeout = 1000; 110 + int r; 111 + 112 + r = cavium_mdiobus_c45_addr(p, phy_id, devad, regnum); 113 + if (r < 0) 114 + return r; 115 + 116 + smi_cmd.u64 = 0; 117 + smi_cmd.s.phy_op = 3; /* MDIO_CLAUSE_45_READ */ 118 + smi_cmd.s.phy_adr = phy_id; 119 + smi_cmd.s.reg_adr = regnum; 120 + oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); 121 + 122 + do { 123 + /* Wait 1000 clocks so we don't saturate the RSL bus 124 + * doing reads. 125 + */ 126 + __delay(1000); 127 + smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT); 128 + } while (smi_rd.s.pending && --timeout); 129 + 130 + if (smi_rd.s.val) 131 + return smi_rd.s.dat; 132 + else 133 + return -EIO; 134 + } 135 + EXPORT_SYMBOL(cavium_mdiobus_read_c45); 136 + 137 + int cavium_mdiobus_write_c22(struct mii_bus *bus, int phy_id, int regnum, 138 + u16 val) 91 139 { 92 140 struct cavium_mdiobus *p = bus->priv; 93 141 union cvmx_smix_cmd smi_cmd; 94 142 union cvmx_smix_wr_dat smi_wr; 95 - unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */ 96 143 int timeout = 1000; 97 144 98 - if (regnum & MII_ADDR_C45) { 99 - int r = cavium_mdiobus_c45_addr(p, phy_id, regnum); 100 - 101 - if (r < 0) 102 - return r; 103 - 104 - regnum = (regnum >> 16) & 0x1f; 105 - op = 1; /* MDIO_CLAUSE_45_WRITE */ 106 - } else { 107 - cavium_mdiobus_set_mode(p, C22); 108 - } 145 + cavium_mdiobus_set_mode(p, C22); 109 146 110 147 smi_wr.u64 = 0; 111 148 smi_wr.s.dat = val; 112 149 oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); 113 150 114 151 smi_cmd.u64 = 0; 115 - smi_cmd.s.phy_op = op; 152 + smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */; 116 153 smi_cmd.s.phy_adr = phy_id; 117 154 smi_cmd.s.reg_adr = regnum; 118 155 oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); ··· 154 143 155 144 return 0; 156 145 } 157 - EXPORT_SYMBOL(cavium_mdiobus_write); 146 + EXPORT_SYMBOL(cavium_mdiobus_write_c22); 147 + 148 + int cavium_mdiobus_write_c45(struct mii_bus *bus, int phy_id, int devad, 149 + int regnum, u16 val) 150 + { 151 + struct cavium_mdiobus *p = bus->priv; 152 + union cvmx_smix_cmd smi_cmd; 153 + union cvmx_smix_wr_dat smi_wr; 154 + int timeout = 1000; 155 + int r; 156 + 157 + r = cavium_mdiobus_c45_addr(p, phy_id, devad, regnum); 158 + if (r < 0) 159 + return r; 160 + 161 + smi_wr.u64 = 0; 162 + smi_wr.s.dat = val; 163 + oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); 164 + 165 + smi_cmd.u64 = 0; 166 + smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_45_WRITE */ 167 + smi_cmd.s.phy_adr = phy_id; 168 + smi_cmd.s.reg_adr = devad; 169 + oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); 170 + 171 + do { 172 + /* Wait 1000 clocks so we don't saturate the RSL bus 173 + * doing reads. 174 + */ 175 + __delay(1000); 176 + smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT); 177 + } while (smi_wr.s.pending && --timeout); 178 + 179 + if (timeout <= 0) 180 + return -EIO; 181 + 182 + return 0; 183 + } 184 + EXPORT_SYMBOL(cavium_mdiobus_write_c45); 158 185 159 186 MODULE_DESCRIPTION("Common code for OCTEON and Thunder MDIO bus drivers"); 160 187 MODULE_AUTHOR("David Daney");
+7 -2
drivers/net/mdio/mdio-cavium.h
··· 114 114 #define oct_mdio_readq(addr) readq(addr) 115 115 #endif 116 116 117 - int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum); 118 - int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val); 117 + int cavium_mdiobus_read_c22(struct mii_bus *bus, int phy_id, int regnum); 118 + int cavium_mdiobus_write_c22(struct mii_bus *bus, int phy_id, int regnum, 119 + u16 val); 120 + int cavium_mdiobus_read_c45(struct mii_bus *bus, int phy_id, int devad, 121 + int regnum); 122 + int cavium_mdiobus_write_c45(struct mii_bus *bus, int phy_id, int devad, 123 + int regnum, u16 val);
+23 -9
drivers/net/mdio/mdio-i2c.c
··· 30 30 return phy_id + 0x40; 31 31 } 32 32 33 - static int i2c_mii_read_default(struct mii_bus *bus, int phy_id, int reg) 33 + static int i2c_mii_read_default_c45(struct mii_bus *bus, int phy_id, int devad, 34 + int reg) 34 35 { 35 36 struct i2c_adapter *i2c = bus->priv; 36 37 struct i2c_msg msgs[2]; ··· 42 41 return 0xffff; 43 42 44 43 p = addr; 45 - if (reg & MII_ADDR_C45) { 46 - *p++ = 0x20 | ((reg >> 16) & 31); 44 + if (devad >= 0) { 45 + *p++ = 0x20 | devad; 47 46 *p++ = reg >> 8; 48 47 } 49 48 *p++ = reg; ··· 65 64 return data[0] << 8 | data[1]; 66 65 } 67 66 68 - static int i2c_mii_write_default(struct mii_bus *bus, int phy_id, int reg, 69 - u16 val) 67 + static int i2c_mii_write_default_c45(struct mii_bus *bus, int phy_id, 68 + int devad, int reg, u16 val) 70 69 { 71 70 struct i2c_adapter *i2c = bus->priv; 72 71 struct i2c_msg msg; ··· 77 76 return 0; 78 77 79 78 p = data; 80 - if (reg & MII_ADDR_C45) { 81 - *p++ = (reg >> 16) & 31; 79 + if (devad >= 0) { 80 + *p++ = devad; 82 81 *p++ = reg >> 8; 83 82 } 84 83 *p++ = reg; ··· 93 92 ret = i2c_transfer(i2c, &msg, 1); 94 93 95 94 return ret < 0 ? ret : 0; 95 + } 96 + 97 + static int i2c_mii_read_default_c22(struct mii_bus *bus, int phy_id, int reg) 98 + { 99 + return i2c_mii_read_default_c45(bus, phy_id, -1, reg); 100 + } 101 + 102 + static int i2c_mii_write_default_c22(struct mii_bus *bus, int phy_id, int reg, 103 + u16 val) 104 + { 105 + return i2c_mii_write_default_c45(bus, phy_id, -1, reg, val); 96 106 } 97 107 98 108 /* RollBall SFPs do not access internal PHY via I2C address 0x56, but ··· 415 403 mii->write = i2c_mii_write_rollball; 416 404 break; 417 405 default: 418 - mii->read = i2c_mii_read_default; 419 - mii->write = i2c_mii_write_default; 406 + mii->read = i2c_mii_read_default_c22; 407 + mii->write = i2c_mii_write_default_c22; 408 + mii->read_c45 = i2c_mii_read_default_c45; 409 + mii->write_c45 = i2c_mii_write_default_c45; 420 410 break; 421 411 } 422 412
+92 -66
drivers/net/mdio/mdio-ipq4019.c
··· 53 53 IPQ4019_MDIO_SLEEP, IPQ4019_MDIO_TIMEOUT); 54 54 } 55 55 56 - static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 56 + static int ipq4019_mdio_read_c45(struct mii_bus *bus, int mii_id, int mmd, 57 + int reg) 57 58 { 58 59 struct ipq4019_mdio_data *priv = bus->priv; 59 60 unsigned int data; ··· 63 62 if (ipq4019_mdio_wait_busy(bus)) 64 63 return -ETIMEDOUT; 65 64 66 - /* Clause 45 support */ 67 - if (regnum & MII_ADDR_C45) { 68 - unsigned int mmd = (regnum >> 16) & 0x1F; 69 - unsigned int reg = regnum & 0xFFFF; 65 + data = readl(priv->membase + MDIO_MODE_REG); 70 66 71 - /* Enter Clause 45 mode */ 72 - data = readl(priv->membase + MDIO_MODE_REG); 67 + data |= MDIO_MODE_C45; 73 68 74 - data |= MDIO_MODE_C45; 69 + writel(data, priv->membase + MDIO_MODE_REG); 75 70 76 - writel(data, priv->membase + MDIO_MODE_REG); 71 + /* issue the phy address and mmd */ 72 + writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); 77 73 78 - /* issue the phy address and mmd */ 79 - writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); 74 + /* issue reg */ 75 + writel(reg, priv->membase + MDIO_DATA_WRITE_REG); 80 76 81 - /* issue reg */ 82 - writel(reg, priv->membase + MDIO_DATA_WRITE_REG); 83 - 84 - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; 85 - } else { 86 - /* Enter Clause 22 mode */ 87 - data = readl(priv->membase + MDIO_MODE_REG); 88 - 89 - data &= ~MDIO_MODE_C45; 90 - 91 - writel(data, priv->membase + MDIO_MODE_REG); 92 - 93 - /* issue the phy address and reg */ 94 - writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); 95 - 96 - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ; 97 - } 77 + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; 98 78 99 79 /* issue read command */ 100 80 writel(cmd, priv->membase + MDIO_CMD_REG); ··· 84 102 if (ipq4019_mdio_wait_busy(bus)) 85 103 return -ETIMEDOUT; 86 104 87 - if (regnum & MII_ADDR_C45) { 88 - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_READ; 105 + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_READ; 89 106 90 - writel(cmd, priv->membase + MDIO_CMD_REG); 107 + writel(cmd, priv->membase + MDIO_CMD_REG); 91 108 92 - if (ipq4019_mdio_wait_busy(bus)) 93 - return -ETIMEDOUT; 94 - } 109 + if (ipq4019_mdio_wait_busy(bus)) 110 + return -ETIMEDOUT; 95 111 96 112 /* Read and return data */ 97 113 return readl(priv->membase + MDIO_DATA_READ_REG); 98 114 } 99 115 100 - static int ipq4019_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 101 - u16 value) 116 + static int ipq4019_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 102 117 { 103 118 struct ipq4019_mdio_data *priv = bus->priv; 104 119 unsigned int data; ··· 104 125 if (ipq4019_mdio_wait_busy(bus)) 105 126 return -ETIMEDOUT; 106 127 107 - /* Clause 45 support */ 108 - if (regnum & MII_ADDR_C45) { 109 - unsigned int mmd = (regnum >> 16) & 0x1F; 110 - unsigned int reg = regnum & 0xFFFF; 128 + data = readl(priv->membase + MDIO_MODE_REG); 111 129 112 - /* Enter Clause 45 mode */ 113 - data = readl(priv->membase + MDIO_MODE_REG); 130 + data &= ~MDIO_MODE_C45; 114 131 115 - data |= MDIO_MODE_C45; 132 + writel(data, priv->membase + MDIO_MODE_REG); 116 133 117 - writel(data, priv->membase + MDIO_MODE_REG); 134 + /* issue the phy address and reg */ 135 + writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); 118 136 119 - /* issue the phy address and mmd */ 120 - writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); 137 + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ; 121 138 122 - /* issue reg */ 123 - writel(reg, priv->membase + MDIO_DATA_WRITE_REG); 139 + /* issue read command */ 140 + writel(cmd, priv->membase + MDIO_CMD_REG); 124 141 125 - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; 142 + /* Wait read complete */ 143 + if (ipq4019_mdio_wait_busy(bus)) 144 + return -ETIMEDOUT; 126 145 127 - writel(cmd, priv->membase + MDIO_CMD_REG); 146 + /* Read and return data */ 147 + return readl(priv->membase + MDIO_DATA_READ_REG); 148 + } 128 149 129 - if (ipq4019_mdio_wait_busy(bus)) 130 - return -ETIMEDOUT; 131 - } else { 132 - /* Enter Clause 22 mode */ 133 - data = readl(priv->membase + MDIO_MODE_REG); 150 + static int ipq4019_mdio_write_c45(struct mii_bus *bus, int mii_id, int mmd, 151 + int reg, u16 value) 152 + { 153 + struct ipq4019_mdio_data *priv = bus->priv; 154 + unsigned int data; 155 + unsigned int cmd; 134 156 135 - data &= ~MDIO_MODE_C45; 157 + if (ipq4019_mdio_wait_busy(bus)) 158 + return -ETIMEDOUT; 136 159 137 - writel(data, priv->membase + MDIO_MODE_REG); 160 + data = readl(priv->membase + MDIO_MODE_REG); 138 161 139 - /* issue the phy address and reg */ 140 - writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); 141 - } 162 + data |= MDIO_MODE_C45; 163 + 164 + writel(data, priv->membase + MDIO_MODE_REG); 165 + 166 + /* issue the phy address and mmd */ 167 + writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); 168 + 169 + /* issue reg */ 170 + writel(reg, priv->membase + MDIO_DATA_WRITE_REG); 171 + 172 + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; 173 + 174 + writel(cmd, priv->membase + MDIO_CMD_REG); 175 + 176 + if (ipq4019_mdio_wait_busy(bus)) 177 + return -ETIMEDOUT; 178 + 179 + /* issue write data */ 180 + writel(value, priv->membase + MDIO_DATA_WRITE_REG); 181 + 182 + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_WRITE; 183 + writel(cmd, priv->membase + MDIO_CMD_REG); 184 + 185 + /* Wait write complete */ 186 + if (ipq4019_mdio_wait_busy(bus)) 187 + return -ETIMEDOUT; 188 + 189 + return 0; 190 + } 191 + 192 + static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 193 + u16 value) 194 + { 195 + struct ipq4019_mdio_data *priv = bus->priv; 196 + unsigned int data; 197 + unsigned int cmd; 198 + 199 + if (ipq4019_mdio_wait_busy(bus)) 200 + return -ETIMEDOUT; 201 + 202 + /* Enter Clause 22 mode */ 203 + data = readl(priv->membase + MDIO_MODE_REG); 204 + 205 + data &= ~MDIO_MODE_C45; 206 + 207 + writel(data, priv->membase + MDIO_MODE_REG); 208 + 209 + /* issue the phy address and reg */ 210 + writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); 142 211 143 212 /* issue write data */ 144 213 writel(value, priv->membase + MDIO_DATA_WRITE_REG); 145 214 146 215 /* issue write command */ 147 - if (regnum & MII_ADDR_C45) 148 - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_WRITE; 149 - else 150 - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE; 216 + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE; 151 217 152 218 writel(cmd, priv->membase + MDIO_CMD_REG); 153 219 ··· 259 235 priv->eth_ldo_rdy = devm_ioremap_resource(&pdev->dev, res); 260 236 261 237 bus->name = "ipq4019_mdio"; 262 - bus->read = ipq4019_mdio_read; 263 - bus->write = ipq4019_mdio_write; 238 + bus->read = ipq4019_mdio_read_c22; 239 + bus->write = ipq4019_mdio_write_c22; 240 + bus->read_c45 = ipq4019_mdio_read_c45; 241 + bus->write_c45 = ipq4019_mdio_write_c45; 264 242 bus->reset = ipq_mdio_reset; 265 243 bus->parent = &pdev->dev; 266 244 snprintf(bus->id, MII_BUS_ID_SIZE, "%s%d", pdev->name, pdev->id);
+43 -11
drivers/net/mdio/mdio-mux-bcm-iproc.c
··· 98 98 * Return value: Successful Read operation returns read reg values and write 99 99 * operation returns 0. Failure operation returns negative error code. 100 100 */ 101 - static int start_miim_ops(void __iomem *base, 101 + static int start_miim_ops(void __iomem *base, bool c45, 102 102 u16 phyid, u32 reg, u16 val, u32 op) 103 103 { 104 104 u32 param; ··· 112 112 param = readl(base + MDIO_PARAM_OFFSET); 113 113 param |= phyid << MDIO_PARAM_PHY_ID; 114 114 param |= val << MDIO_PARAM_PHY_DATA; 115 - if (reg & MII_ADDR_C45) 115 + if (c45) 116 116 param |= BIT(MDIO_PARAM_C45_SEL); 117 117 118 118 writel(param, base + MDIO_PARAM_OFFSET); ··· 131 131 return ret; 132 132 } 133 133 134 - static int iproc_mdiomux_read(struct mii_bus *bus, int phyid, int reg) 134 + static int iproc_mdiomux_read_c22(struct mii_bus *bus, int phyid, int reg) 135 135 { 136 136 struct iproc_mdiomux_desc *md = bus->priv; 137 137 int ret; 138 138 139 - ret = start_miim_ops(md->base, phyid, reg, 0, MDIO_CTRL_READ_OP); 139 + ret = start_miim_ops(md->base, false, phyid, reg, 0, MDIO_CTRL_READ_OP); 140 140 if (ret < 0) 141 - dev_err(&bus->dev, "mdiomux read operation failed!!!"); 141 + dev_err(&bus->dev, "mdiomux c22 read operation failed!!!"); 142 142 143 143 return ret; 144 144 } 145 145 146 - static int iproc_mdiomux_write(struct mii_bus *bus, 147 - int phyid, int reg, u16 val) 146 + static int iproc_mdiomux_read_c45(struct mii_bus *bus, int phyid, int devad, 147 + int reg) 148 + { 149 + struct iproc_mdiomux_desc *md = bus->priv; 150 + int ret; 151 + 152 + ret = start_miim_ops(md->base, true, phyid, reg | devad << 16, 0, 153 + MDIO_CTRL_READ_OP); 154 + if (ret < 0) 155 + dev_err(&bus->dev, "mdiomux read c45 operation failed!!!"); 156 + 157 + return ret; 158 + } 159 + 160 + static int iproc_mdiomux_write_c22(struct mii_bus *bus, 161 + int phyid, int reg, u16 val) 148 162 { 149 163 struct iproc_mdiomux_desc *md = bus->priv; 150 164 int ret; 151 165 152 166 /* Write val at reg offset */ 153 - ret = start_miim_ops(md->base, phyid, reg, val, MDIO_CTRL_WRITE_OP); 167 + ret = start_miim_ops(md->base, false, phyid, reg, val, 168 + MDIO_CTRL_WRITE_OP); 154 169 if (ret < 0) 155 - dev_err(&bus->dev, "mdiomux write operation failed!!!"); 170 + dev_err(&bus->dev, "mdiomux write c22 operation failed!!!"); 171 + 172 + return ret; 173 + } 174 + 175 + static int iproc_mdiomux_write_c45(struct mii_bus *bus, 176 + int phyid, int devad, int reg, u16 val) 177 + { 178 + struct iproc_mdiomux_desc *md = bus->priv; 179 + int ret; 180 + 181 + /* Write val at reg offset */ 182 + ret = start_miim_ops(md->base, true, phyid, reg | devad << 16, val, 183 + MDIO_CTRL_WRITE_OP); 184 + if (ret < 0) 185 + dev_err(&bus->dev, "mdiomux write c45 operation failed!!!"); 156 186 157 187 return ret; 158 188 } ··· 253 223 bus->name = "iProc MDIO mux bus"; 254 224 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id); 255 225 bus->parent = &pdev->dev; 256 - bus->read = iproc_mdiomux_read; 257 - bus->write = iproc_mdiomux_write; 226 + bus->read = iproc_mdiomux_read_c22; 227 + bus->write = iproc_mdiomux_write_c22; 228 + bus->read_c45 = iproc_mdiomux_read_c45; 229 + bus->write_c45 = iproc_mdiomux_write_c45; 258 230 259 231 bus->phy_mask = ~0; 260 232 bus->dev.of_node = pdev->dev.of_node;
+4 -2
drivers/net/mdio/mdio-octeon.c
··· 58 58 snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%px", bus->register_base); 59 59 bus->mii_bus->parent = &pdev->dev; 60 60 61 - bus->mii_bus->read = cavium_mdiobus_read; 62 - bus->mii_bus->write = cavium_mdiobus_write; 61 + bus->mii_bus->read = cavium_mdiobus_read_c22; 62 + bus->mii_bus->write = cavium_mdiobus_write_c22; 63 + bus->mii_bus->read_c45 = cavium_mdiobus_read_c45; 64 + bus->mii_bus->write_c45 = cavium_mdiobus_write_c45; 63 65 64 66 platform_set_drvdata(pdev, bus); 65 67
+4 -2
drivers/net/mdio/mdio-thunder.c
··· 93 93 bus->mii_bus->name = KBUILD_MODNAME; 94 94 snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", r.start); 95 95 bus->mii_bus->parent = &pdev->dev; 96 - bus->mii_bus->read = cavium_mdiobus_read; 97 - bus->mii_bus->write = cavium_mdiobus_write; 96 + bus->mii_bus->read = cavium_mdiobus_read_c22; 97 + bus->mii_bus->write = cavium_mdiobus_write_c22; 98 + bus->mii_bus->read_c45 = cavium_mdiobus_read_c45; 99 + bus->mii_bus->write_c45 = cavium_mdiobus_write_c45; 98 100 99 101 err = of_mdiobus_register(bus->mii_bus, node); 100 102 if (err)
+16 -5
include/linux/fsl/enetc_mdio.h
··· 37 37 38 38 #if IS_REACHABLE(CONFIG_FSL_ENETC_MDIO) 39 39 40 - int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum); 41 - int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value); 40 + int enetc_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum); 41 + int enetc_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, 42 + u16 value); 43 + int enetc_mdio_read_c45(struct mii_bus *bus, int phy_id, int devad, int regnum); 44 + int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id, int devad, int regnum, 45 + u16 value); 42 46 struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs); 43 47 44 48 #else 45 49 46 - static inline int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum) 50 + static inline int enetc_mdio_read_c22(struct mii_bus *bus, int phy_id, 51 + int regnum) 47 52 { return -EINVAL; } 48 - static inline int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, 49 - u16 value) 53 + static inline int enetc_mdio_write_c22(struct mii_bus *bus, int phy_id, 54 + int regnum, u16 value) 55 + { return -EINVAL; } 56 + static inline int enetc_mdio_read_c45(struct mii_bus *bus, int phy_id, 57 + int devad, int regnum) 58 + { return -EINVAL; } 59 + static inline int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id, 60 + int devad, int regnum, u16 value) 50 61 { return -EINVAL; } 51 62 struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs) 52 63 { return ERR_PTR(-EINVAL); }