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iio: adc: ad4062: Add GPIO Controller support

When gp0 or gp1 is not taken as an interrupt, expose them as GPO if
gpio-contoller is set in the devicetree. gpio-regmap is not used
because the GPO static low is 'b101 and static high is 0b110; low state
requires setting bit 0, not fitting the abstraction of low=0 and
high=mask.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Jorge Marques and committed by
Jonathan Cameron da1d3596 d2ca7af2

+125
+125
drivers/iio/adc/ad4062.c
··· 11 11 #include <linux/delay.h> 12 12 #include <linux/devm-helpers.h> 13 13 #include <linux/err.h> 14 + #include <linux/gpio/driver.h> 14 15 #include <linux/i3c/device.h> 15 16 #include <linux/i3c/master.h> 16 17 #include <linux/iio/buffer.h> ··· 89 88 #define AD4060_PROD_ID 0x7A 90 89 #define AD4062_PROD_ID 0x7C 91 90 91 + #define AD4062_GP_DISABLED 0x0 92 92 #define AD4062_GP_INTR 0x1 93 93 #define AD4062_GP_DRDY 0x2 94 + #define AD4062_GP_STATIC_LOW 0x5 95 + #define AD4062_GP_STATIC_HIGH 0x6 94 96 95 97 #define AD4062_LIMIT_BITS 12 96 98 ··· 691 687 return ret; 692 688 693 689 if (ret < 0) { 690 + st->gpo_irq[0] = false; 694 691 ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN, 695 692 AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN, 696 693 AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN); 697 694 if (ret) 698 695 return ret; 699 696 } else { 697 + st->gpo_irq[0] = true; 700 698 ret = devm_request_threaded_irq(dev, ret, NULL, 701 699 ad4062_irq_handler_thresh, 702 700 IRQF_ONESHOT, indio_dev->name, ··· 1353 1347 return 0; 1354 1348 } 1355 1349 1350 + static int ad4062_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1351 + { 1352 + return GPIO_LINE_DIRECTION_OUT; 1353 + } 1354 + 1355 + static int ad4062_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1356 + { 1357 + struct ad4062_state *st = gpiochip_get_data(gc); 1358 + unsigned int reg_val = value ? AD4062_GP_STATIC_HIGH : AD4062_GP_STATIC_LOW; 1359 + 1360 + if (offset) 1361 + return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1362 + AD4062_REG_GP_CONF_MODE_MSK_1, 1363 + FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val)); 1364 + else 1365 + return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1366 + AD4062_REG_GP_CONF_MODE_MSK_0, 1367 + FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val)); 1368 + } 1369 + 1370 + static int ad4062_gpio_get(struct gpio_chip *gc, unsigned int offset) 1371 + { 1372 + struct ad4062_state *st = gpiochip_get_data(gc); 1373 + unsigned int reg_val; 1374 + int ret; 1375 + 1376 + ret = regmap_read(st->regmap, AD4062_REG_GP_CONF, &reg_val); 1377 + if (ret) 1378 + return ret; 1379 + 1380 + if (offset) 1381 + reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val); 1382 + else 1383 + reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val); 1384 + 1385 + return reg_val == AD4062_GP_STATIC_HIGH; 1386 + } 1387 + 1388 + static void ad4062_gpio_disable(void *data) 1389 + { 1390 + struct ad4062_state *st = data; 1391 + u8 val = FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_DISABLED) | 1392 + FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_DISABLED); 1393 + 1394 + regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1395 + AD4062_REG_GP_CONF_MODE_MSK_1 | AD4062_REG_GP_CONF_MODE_MSK_0, 1396 + val); 1397 + } 1398 + 1399 + static int ad4062_gpio_init_valid_mask(struct gpio_chip *gc, 1400 + unsigned long *valid_mask, 1401 + unsigned int ngpios) 1402 + { 1403 + struct ad4062_state *st = gpiochip_get_data(gc); 1404 + 1405 + bitmap_zero(valid_mask, ngpios); 1406 + 1407 + for (unsigned int i = 0; i < ARRAY_SIZE(st->gpo_irq); i++) 1408 + __assign_bit(i, valid_mask, !st->gpo_irq[i]); 1409 + 1410 + return 0; 1411 + } 1412 + 1413 + static int ad4062_gpio_init(struct ad4062_state *st) 1414 + { 1415 + struct device *dev = &st->i3cdev->dev; 1416 + struct gpio_chip *gc; 1417 + u8 val, mask; 1418 + int ret; 1419 + 1420 + if (!device_property_read_bool(dev, "gpio-controller")) 1421 + return 0; 1422 + 1423 + gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1424 + if (!gc) 1425 + return -ENOMEM; 1426 + 1427 + val = 0; 1428 + mask = 0; 1429 + if (!st->gpo_irq[0]) { 1430 + mask |= AD4062_REG_GP_CONF_MODE_MSK_0; 1431 + val |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_STATIC_LOW); 1432 + } 1433 + if (!st->gpo_irq[1]) { 1434 + mask |= AD4062_REG_GP_CONF_MODE_MSK_1; 1435 + val |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_STATIC_LOW); 1436 + } 1437 + 1438 + ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1439 + mask, val); 1440 + if (ret) 1441 + return ret; 1442 + 1443 + ret = devm_add_action_or_reset(dev, ad4062_gpio_disable, st); 1444 + if (ret) 1445 + return ret; 1446 + 1447 + gc->parent = dev; 1448 + gc->label = st->chip->name; 1449 + gc->owner = THIS_MODULE; 1450 + gc->base = -1; 1451 + gc->ngpio = 2; 1452 + gc->init_valid_mask = ad4062_gpio_init_valid_mask; 1453 + gc->get_direction = ad4062_gpio_get_direction; 1454 + gc->set = ad4062_gpio_set; 1455 + gc->get = ad4062_gpio_get; 1456 + gc->can_sleep = true; 1457 + 1458 + ret = devm_gpiochip_add_data(dev, gc, st); 1459 + if (ret) 1460 + return dev_err_probe(dev, ret, "Unable to register GPIO chip\n"); 1461 + 1462 + return 0; 1463 + } 1464 + 1356 1465 static const struct i3c_device_id ad4062_id_table[] = { 1357 1466 I3C_DEVICE(AD4062_I3C_VENDOR, AD4060_PROD_ID, &ad4060_chip_info), 1358 1467 I3C_DEVICE(AD4062_I3C_VENDOR, AD4062_PROD_ID, &ad4062_chip_info), ··· 1555 1434 ret = ad4062_request_ibi(i3cdev); 1556 1435 if (ret) 1557 1436 return dev_err_probe(dev, ret, "Failed to request i3c ibi\n"); 1437 + 1438 + ret = ad4062_gpio_init(st); 1439 + if (ret) 1440 + return ret; 1558 1441 1559 1442 ret = devm_work_autocancel(dev, &st->trig_conv, ad4062_trigger_work); 1560 1443 if (ret)