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drm/i915/gvt: use hardcoded reference clocks

Usually I'd argue hardcoding values is the wrong thing to do, but in
this case, GVT looking deep into the guts of the DPLL manager for the
reference clocks is worse. This is done for BDW and BXT only, and there
shouldn't be any reason to try to be so dynamic about it.

This helps reduce the direct pokes at display guts from non-display
code.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
Link: https://lore.kernel.org/r/20250321125114.750062-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

+2 -2
+2 -2
drivers/gpu/drm/i915/gvt/handlers.c
··· 514 514 515 515 switch (wrpll_ctl & WRPLL_REF_MASK) { 516 516 case WRPLL_REF_PCH_SSC: 517 - refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc; 517 + refclk = 135000; 518 518 break; 519 519 case WRPLL_REF_LCPLL: 520 520 refclk = 2700000; ··· 545 545 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 546 546 { 547 547 u32 dp_br = 0; 548 - int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc; 548 + int refclk = 100000; 549 549 enum dpio_phy phy = DPIO_PHY0; 550 550 enum dpio_channel ch = DPIO_CH0; 551 551 struct dpll clock = {};