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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: msm8996-cpu: Use parent_data/_hws for all clocks
Replace parent_names in PLLs, secondary muxes and primary muxes with
parent_data. For primary muxes there were never any *cl_pll_acd clocks,
so instead of adding them, put the primary PLLs in both PLL_INDEX and
ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when
setting parent since we always want ACD when using the primary PLLs.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
[DB: switch to parent_hws for pmux clocks]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220714100351.1834711-2-dmitry.baryshkov@linaro.org
authored by
Yassine Oudjana
and committed by
Bjorn Andersson
da5daae8
b4feed4a
+47
-32
+47
-32
drivers/clk/qcom/clk-cpu-8996.c
+47
-32
drivers/clk/qcom/clk-cpu-8996.c
···
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.early_output_mask = BIT(3),
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};
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+
static const struct clk_parent_data pll_parent[] = {
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+
{ .fw_name = "xo" },
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+
};
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+
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static struct clk_alpha_pll pwrcl_pll = {
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.offset = PWRCL_REG_OFFSET,
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.regs = prim_pll_regs,
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.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pwrcl_pll",
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-
.parent_names = (const char *[]){ "xo" },
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-
.num_parents = 1,
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+
.parent_data = pll_parent,
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+
.num_parents = ARRAY_SIZE(pll_parent),
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.ops = &clk_alpha_pll_huayra_ops,
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},
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};
···
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.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "perfcl_pll",
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-
.parent_names = (const char *[]){ "xo" },
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-
.num_parents = 1,
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+
.parent_data = pll_parent,
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+
.num_parents = ARRAY_SIZE(pll_parent),
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.ops = &clk_alpha_pll_huayra_ops,
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},
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};
···
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.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "pwrcl_alt_pll",
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-
.parent_names = (const char *[]){ "xo" },
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-
.num_parents = 1,
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+
.parent_data = pll_parent,
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+
.num_parents = ARRAY_SIZE(pll_parent),
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.ops = &clk_alpha_pll_hwfsm_ops,
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},
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};
···
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.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "perfcl_alt_pll",
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-
.parent_names = (const char *[]){ "xo" },
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-
.num_parents = 1,
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+
.parent_data = pll_parent,
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+
.num_parents = ARRAY_SIZE(pll_parent),
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.ops = &clk_alpha_pll_hwfsm_ops,
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},
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};
···
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u32 val;
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val = index;
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+
/* We always want ACD when using the primary PLL */
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if (val == PLL_INDEX)
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val = ACD_INDEX;
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val <<= cpuclk->shift;
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return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
···
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.determine_rate = clk_cpu_8996_pmux_determine_rate,
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};
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+
static const struct clk_parent_data pwrcl_smux_parents[] = {
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{ .fw_name = "xo" },
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{ .hw = &pwrcl_pll_postdiv.hw },
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};
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+
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static const struct clk_parent_data perfcl_smux_parents[] = {
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{ .fw_name = "xo" },
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{ .hw = &perfcl_pll_postdiv.hw },
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};
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+
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static struct clk_regmap_mux pwrcl_smux = {
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.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
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.shift = 2,
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.width = 2,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "pwrcl_smux",
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-
.parent_names = (const char *[]){
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-
"xo",
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-
"pwrcl_pll_postdiv",
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-
},
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-
.num_parents = 2,
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.parent_data = pwrcl_smux_parents,
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.num_parents = ARRAY_SIZE(pwrcl_smux_parents),
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.ops = &clk_regmap_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
···
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.width = 2,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "perfcl_smux",
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-
.parent_names = (const char *[]){
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-
"xo",
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-
"perfcl_pll_postdiv",
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-
},
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-
.num_parents = 2,
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+
.parent_data = perfcl_smux_parents,
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+
.num_parents = ARRAY_SIZE(perfcl_smux_parents),
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.ops = &clk_regmap_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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+
};
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+
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static const struct clk_hw *pwrcl_pmux_parents[] = {
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[SMUX_INDEX] = &pwrcl_smux.clkr.hw,
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[PLL_INDEX] = &pwrcl_pll.clkr.hw,
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+
[ACD_INDEX] = &pwrcl_pll.clkr.hw,
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[ALT_INDEX] = &pwrcl_alt_pll.clkr.hw,
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};
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+
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static const struct clk_hw *perfcl_pmux_parents[] = {
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[SMUX_INDEX] = &perfcl_smux.clkr.hw,
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[PLL_INDEX] = &perfcl_pll.clkr.hw,
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[ACD_INDEX] = &perfcl_pll.clkr.hw,
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[ALT_INDEX] = &perfcl_alt_pll.clkr.hw,
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};
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static struct clk_cpu_8996_pmux pwrcl_pmux = {
···
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.nb.notifier_call = cpu_clk_notifier_cb,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "pwrcl_pmux",
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-
.parent_names = (const char *[]){
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"pwrcl_smux",
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"pwrcl_pll",
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"pwrcl_pll_acd",
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"pwrcl_alt_pll",
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},
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.num_parents = 4,
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.parent_hws = pwrcl_pmux_parents,
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.num_parents = ARRAY_SIZE(pwrcl_pmux_parents),
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.ops = &clk_cpu_8996_pmux_ops,
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/* CPU clock is critical and should never be gated */
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.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
···
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.nb.notifier_call = cpu_clk_notifier_cb,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "perfcl_pmux",
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-
.parent_names = (const char *[]){
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"perfcl_smux",
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"perfcl_pll",
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"perfcl_pll_acd",
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"perfcl_alt_pll",
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},
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.num_parents = 4,
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.parent_hws = perfcl_pmux_parents,
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.num_parents = ARRAY_SIZE(perfcl_pmux_parents),
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.ops = &clk_cpu_8996_pmux_ops,
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/* CPU clock is critical and should never be gated */
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.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,