tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
"A smallish set of fixes that we've been sitting on for a while now,
flushing the queue here so they go in. Summary:

A handful of fixes for OMAP, i.MX, Allwinner and Tegra:

- A clock rate and a PHY setup fix for i.MX6Q/DL
- A couple of fixes for the reduced serial bus (sunxi-rsb) on
Allwinner
- UART wakeirq fix for an OMAP4 board, timer config fixes for AM43XX.
- Suspend fix for Tegra124 Chromebooks
- Fix for missing implicit include that's different between
ARM/ARM64"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: tegra: Fix suspend hang on Tegra124 Chromebooks
bus: sunxi-rsb: Fix peripheral IC mapping runtime address
bus: sunxi-rsb: Fix primary PMIC mapping hardware address
ARM: dts: Fix UART wakeirq for omap4 duovero parlor
ARM: OMAP2+: AM43xx: select ARM TWD timer
ARM: OMAP2+: am43xx: enable GENERIC_CLOCKEVENTS_BROADCAST
fsl-ifc: add missing include on ARM64
ARM: dts: imx6: Fix Ethernet PHY mode on Ventana boards
ARM: dts: imx: Fix the assigned-clock mismatch issue on imx6q/dl
bus: sunxi-rsb: unlock on error in sunxi_rsb_read()
ARM: dts: sunxi: sun6i-a31s-primo81.dts: add touchscreen axis swapping property

Linus Torvalds db066501 2c96961f

+27 -13
+1 -1
arch/arm/boot/dts/imx6q-gw5400-a.dts
··· 154 154 &fec { 155 155 pinctrl-names = "default"; 156 156 pinctrl-0 = <&pinctrl_enet>; 157 - phy-mode = "rgmii"; 157 + phy-mode = "rgmii-id"; 158 158 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; 159 159 status = "okay"; 160 160 };
+1 -1
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
··· 94 94 &fec { 95 95 pinctrl-names = "default"; 96 96 pinctrl-0 = <&pinctrl_enet>; 97 - phy-mode = "rgmii"; 97 + phy-mode = "rgmii-id"; 98 98 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 99 99 status = "okay"; 100 100 };
+1 -1
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
··· 154 154 &fec { 155 155 pinctrl-names = "default"; 156 156 pinctrl-0 = <&pinctrl_enet>; 157 - phy-mode = "rgmii"; 157 + phy-mode = "rgmii-id"; 158 158 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 159 159 status = "okay"; 160 160 };
+1 -1
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
··· 155 155 &fec { 156 156 pinctrl-names = "default"; 157 157 pinctrl-0 = <&pinctrl_enet>; 158 - phy-mode = "rgmii"; 158 + phy-mode = "rgmii-id"; 159 159 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 160 160 status = "okay"; 161 161 };
+1 -1
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
··· 145 145 &fec { 146 146 pinctrl-names = "default"; 147 147 pinctrl-0 = <&pinctrl_enet>; 148 - phy-mode = "rgmii"; 148 + phy-mode = "rgmii-id"; 149 149 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 150 150 status = "okay"; 151 151 };
+3 -3
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
··· 113 113 &clks { 114 114 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, 115 115 <&clks IMX6QDL_PLL4_BYPASS>, 116 - <&clks IMX6QDL_CLK_PLL4_POST_DIV>, 117 116 <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 118 - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 117 + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, 118 + <&clks IMX6QDL_CLK_PLL4_POST_DIV>; 119 119 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, 120 120 <&clks IMX6QDL_PLL4_BYPASS_SRC>, 121 121 <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 122 122 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 123 - assigned-clock-rates = <0>, <0>, <24576000>; 123 + assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; 124 124 }; 125 125 126 126 &ecspi1 {
+4
arch/arm/boot/dts/omap4-duovero-parlor.dts
··· 189 189 }; 190 190 }; 191 191 192 + &uart3 { 193 + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH 194 + &omap4_pmx_core OMAP4_UART3_RX>; 195 + };
+1
arch/arm/boot/dts/sun6i-a31s-primo81.dts
··· 83 83 reg = <0x5d>; 84 84 interrupt-parent = <&pio>; 85 85 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ 86 + touchscreen-swapped-x-y; 86 87 }; 87 88 }; 88 89
+1 -1
arch/arm/boot/dts/tegra124-nyan.dtsi
··· 399 399 400 400 /* CPU DFLL clock */ 401 401 clock@0,70110000 { 402 - status = "okay"; 402 + status = "disabled"; 403 403 vdd-cpu-supply = <&vdd_cpu>; 404 404 nvidia,i2c-fs-rate = <400000>; 405 405 };
+2
arch/arm/mach-omap2/Kconfig
··· 65 65 select MACH_OMAP_GENERIC 66 66 select MIGHT_HAVE_CACHE_L2X0 67 67 select HAVE_ARM_SCU 68 + select GENERIC_CLOCKEVENTS_BROADCAST 69 + select HAVE_ARM_TWD 68 70 69 71 config SOC_DRA7XX 70 72 bool "TI DRA7XX"
+6
arch/arm/mach-omap2/timer.c
··· 320 320 return r; 321 321 } 322 322 323 + #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) 324 + void tick_broadcast(const struct cpumask *mask) 325 + { 326 + } 327 + #endif 328 + 323 329 static void __init omap2_gp_clockevent_init(int gptimer_id, 324 330 const char *fck_source, 325 331 const char *property)
+4 -4
drivers/bus/sunxi-rsb.c
··· 342 342 343 343 ret = _sunxi_rsb_run_xfer(rsb); 344 344 if (ret) 345 - goto out; 345 + goto unlock; 346 346 347 347 *buf = readl(rsb->regs + RSB_DATA); 348 348 349 + unlock: 349 350 mutex_unlock(&rsb->lock); 350 351 351 - out: 352 352 return ret; 353 353 } 354 354 ··· 527 527 */ 528 528 529 529 static const struct sunxi_rsb_addr_map sunxi_rsb_addr_maps[] = { 530 - { 0x3e3, 0x2d }, /* Primary PMIC: AXP223, AXP809, AXP81X, ... */ 530 + { 0x3a3, 0x2d }, /* Primary PMIC: AXP223, AXP809, AXP81X, ... */ 531 531 { 0x745, 0x3a }, /* Secondary PMIC: AXP806, ... */ 532 - { 0xe89, 0x45 }, /* Peripheral IC: AC100, ... */ 532 + { 0xe89, 0x4e }, /* Peripheral IC: AC100, ... */ 533 533 }; 534 534 535 535 static u8 sunxi_rsb_get_rtaddr(u16 hwaddr)
+1
drivers/memory/fsl_ifc.c
··· 22 22 #include <linux/module.h> 23 23 #include <linux/kernel.h> 24 24 #include <linux/compiler.h> 25 + #include <linux/sched.h> 25 26 #include <linux/spinlock.h> 26 27 #include <linux/types.h> 27 28 #include <linux/slab.h>