Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ata: ahci-dwc: Remove not-going-to-be-supported code for Baikal SoC
As noticed in the discussion [1] the Baikal SoC and platforms
are not going to be finalized, hence remove stale code.
Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
authored by
Andy Shevchenko
and committed by
Niklas Cassel
db1d3cfa
99d6b901
-171
-115
Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml
-115
Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Baikal-T1 SoC AHCI SATA controller
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maintainers:
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- Serge Semin <fancer.lancer@gmail.com>
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description:
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AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
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DWC AHCI SATA v4.10a IP-core.
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-
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allOf:
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- $ref: snps,dwc-ahci-common.yaml#
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-
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properties:
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compatible:
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const: baikal,bt1-ahci
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clocks:
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items:
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- description: Peripheral APB bus clock
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- description: Application AXI BIU clock
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- description: SATA Ports reference clock
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-
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clock-names:
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items:
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- const: pclk
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- const: aclk
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- const: ref
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resets:
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items:
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- description: Application AXI BIU domain reset
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- description: SATA Ports clock domain reset
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reset-names:
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items:
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- const: arst
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- const: ref
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ports-implemented:
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maximum: 0x3
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patternProperties:
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"^sata-port@[0-1]$":
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$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
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-
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properties:
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reg:
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minimum: 0
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maximum: 1
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snps,tx-ts-max:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Due to having AXI3 bus interface utilized the maximum Tx DMA
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transaction size can't exceed 16 beats (AxLEN[3:0]).
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enum: [ 1, 2, 4, 8, 16 ]
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snps,rx-ts-max:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Due to having AXI3 bus interface utilized the maximum Rx DMA
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transaction size can't exceed 16 beats (AxLEN[3:0]).
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enum: [ 1, 2, 4, 8, 16 ]
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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unevaluatedProperties: false
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examples:
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- |
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sata@1f050000 {
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compatible = "baikal,bt1-ahci";
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reg = <0x1f050000 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 64 4>;
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clocks = <&ccu_sys 1>, <&ccu_axi 2>, <&sata_ref_clk>;
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clock-names = "pclk", "aclk", "ref";
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resets = <&ccu_axi 2>, <&ccu_sys 0>;
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reset-names = "arst", "ref";
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ports-implemented = <0x3>;
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sata-port@0 {
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reg = <0>;
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snps,tx-ts-max = <4>;
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snps,rx-ts-max = <4>;
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};
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sata-port@1 {
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reg = <1>;
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snps,tx-ts-max = <4>;
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snps,rx-ts-max = <4>;
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};
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};
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...
-1
drivers/ata/Kconfig
-1
drivers/ata/Kconfig
-55
drivers/ata/ahci_dwc.c
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drivers/ata/ahci_dwc.c
···
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#include <linux/kernel.h>
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#include <linux/libata.h>
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#include <linux/log2.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/regmap.h>
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#include "ahci.h"
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···
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#define AHCI_DWC_PORT_PHYCR 0x74
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#define AHCI_DWC_PORT_PHYSR 0x78
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/* Baikal-T1 AHCI SATA specific registers */
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#define AHCI_BT1_HOST_PHYCR AHCI_DWC_HOST_GPCR
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#define AHCI_BT1_HOST_MPLM_MASK GENMASK(29, 23)
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#define AHCI_BT1_HOST_LOSDT_MASK GENMASK(22, 20)
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#define AHCI_BT1_HOST_CRR BIT(19)
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#define AHCI_BT1_HOST_CRW BIT(18)
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#define AHCI_BT1_HOST_CRCD BIT(17)
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#define AHCI_BT1_HOST_CRCA BIT(16)
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#define AHCI_BT1_HOST_CRDI_MASK GENMASK(15, 0)
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#define AHCI_BT1_HOST_PHYSR AHCI_DWC_HOST_GPSR
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#define AHCI_BT1_HOST_CRA BIT(16)
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#define AHCI_BT1_HOST_CRDO_MASK GENMASK(15, 0)
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struct ahci_dwc_plat_data {
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unsigned int pflags;
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unsigned int hflags;
···
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u32 timv;
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u32 dmacr[AHCI_MAX_PORTS];
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};
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static int ahci_bt1_init(struct ahci_host_priv *hpriv)
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{
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struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
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int ret;
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/* APB, application and reference clocks are required */
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if (!ahci_platform_find_clk(hpriv, "pclk") ||
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!ahci_platform_find_clk(hpriv, "aclk") ||
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!ahci_platform_find_clk(hpriv, "ref")) {
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dev_err(&dpriv->pdev->dev, "No system clocks specified\n");
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return -EINVAL;
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}
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/*
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* Fully reset the SATA AXI and ref clocks domain to ensure the state
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* machine is working from scratch especially if the reference clocks
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* source has been changed.
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*/
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ret = ahci_platform_assert_rsts(hpriv);
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if (ret) {
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dev_err(&dpriv->pdev->dev, "Couldn't assert the resets\n");
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return ret;
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}
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ret = ahci_platform_deassert_rsts(hpriv);
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if (ret) {
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dev_err(&dpriv->pdev->dev, "Couldn't de-assert the resets\n");
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return ret;
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}
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return 0;
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}
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static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_device *pdev)
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{
···
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.pflags = AHCI_PLATFORM_GET_RESETS,
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};
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static struct ahci_dwc_plat_data ahci_bt1_plat = {
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.pflags = AHCI_PLATFORM_GET_RESETS | AHCI_PLATFORM_RST_TRIGGER,
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.init = ahci_bt1_init,
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};
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static const struct of_device_id ahci_dwc_of_match[] = {
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{ .compatible = "snps,dwc-ahci", &ahci_dwc_plat },
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{ .compatible = "snps,spear-ahci", &ahci_dwc_plat },
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{ .compatible = "baikal,bt1-ahci", &ahci_bt1_plat },
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{},
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};
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MODULE_DEVICE_TABLE(of, ahci_dwc_of_match);