Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/ras: Add table reset func for pmfw eeprom
add table reset func for pmfw eeprom, add smu eeprom control
structure
Signed-off-by: Gangliang Xie <ganglxie@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Gangliang Xie
and committed by
Alex Deucher
db217d08
0e5eaa8d
+63
-2
+1
drivers/gpu/drm/amd/ras/rascore/ras.h
+1
drivers/gpu/drm/amd/ras/rascore/ras.h
+7
-2
drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
+7
-2
drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
···
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if (cmd->input_size != sizeof(struct ras_cmd_dev_handle))
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return RAS_CMD__ERROR_INVALID_INPUT_SIZE;
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-
if (ras_eeprom_reset_table(ras_core))
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-
return RAS_CMD__ERROR_GENERIC;
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+
if (ras_fw_eeprom_supported(ras_core)) {
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if (ras_fw_eeprom_reset_table(ras_core))
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return RAS_CMD__ERROR_GENERIC;
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} else {
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if (ras_eeprom_reset_table(ras_core))
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return RAS_CMD__ERROR_GENERIC;
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}
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if (ras_umc_clean_badpage_data(ras_core))
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return RAS_CMD__ERROR_GENERIC;
+29
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+29
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
···
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return sys_func->mp1_send_eeprom_msg(ras_core,
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RAS_SMU_EraseRasTable, 0, result);
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}
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int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core)
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{
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struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
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u32 erase_res = 0;
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int res;
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mutex_lock(&control->ras_tbl_mutex);
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res = ras_fw_erase_ras_table(ras_core, &erase_res);
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if (res || erase_res) {
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RAS_DEV_WARN(ras_core->dev, "RAS EEPROM reset failed, res:%d result:%d",
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res, erase_res);
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if (!res)
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res = -EIO;
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}
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control->ras_num_recs = 0;
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control->bad_channel_bitmap = 0;
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ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM,
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&control->ras_num_recs);
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ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP,
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&control->bad_channel_bitmap);
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control->update_channel_flag = false;
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mutex_unlock(&control->ras_tbl_mutex);
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return res;
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}
+26
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+26
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
···
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#ifndef __RAS_EEPROM_FW_H__
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#define __RAS_EEPROM_FW_H__
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struct ras_fw_eeprom_control {
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uint32_t version;
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/* record threshold */
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int record_threshold_config;
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uint32_t record_threshold_count;
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bool update_channel_flag;
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/* Number of records in the table.
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*/
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u32 ras_num_recs;
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/* Maximum possible number of records
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* we could store, i.e. the maximum capacity
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* of the table.
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*/
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u32 ras_max_record_count;
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/* Protect table access via this mutex.
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*/
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struct mutex ras_tbl_mutex;
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/* Record channel info which occurred bad pages
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*/
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u32 bad_channel_bitmap;
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};
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void ras_fw_init_feature_flags(struct ras_core_context *ras_core);
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bool ras_fw_eeprom_supported(struct ras_core_context *ras_core);
···
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uint16_t index, uint64_t *ipid);
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int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
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uint32_t *result);
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int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
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#endif