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perf/x86/intel: Output LBR TOS information correctly

For Intel LBR, the LBR Top-of-Stack (TOS) information is the HW index of
raw branch record for the most recent branch.

For non-adaptive PEBS and non-PEBS, the TOS information can be directly
retrieved from TOS MSR read in intel_pmu_lbr_read().

For adaptive PEBS, the LBR information stored in PEBS record doesn't
include the TOS information. For single PEBS, TOS can be directly read
from MSR, because the PMI is triggered immediately after PEBS is
written. TOS MSR is still unchanged.
For large PEBS, TOS MSR has stale value. Set -1ULL to indicate that the
TOS information is not available.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lkml.kernel.org/r/20200127165355.27495-3-kan.liang@linux.intel.com

authored by

Kan Liang and committed by
Ingo Molnar db278b90 bbfd5e4f

+9 -3
+9 -3
arch/x86/events/intel/lbr.c
··· 585 585 cpuc->lbr_entries[i].reserved = 0; 586 586 } 587 587 cpuc->lbr_stack.nr = i; 588 - cpuc->lbr_stack.hw_idx = -1ULL; 588 + cpuc->lbr_stack.hw_idx = tos; 589 589 } 590 590 591 591 /* ··· 681 681 out++; 682 682 } 683 683 cpuc->lbr_stack.nr = out; 684 - cpuc->lbr_stack.hw_idx = -1ULL; 684 + cpuc->lbr_stack.hw_idx = tos; 685 685 } 686 686 687 687 void intel_pmu_lbr_read(void) ··· 1122 1122 int i; 1123 1123 1124 1124 cpuc->lbr_stack.nr = x86_pmu.lbr_nr; 1125 - cpuc->lbr_stack.hw_idx = -1ULL; 1125 + 1126 + /* Cannot get TOS for large PEBS */ 1127 + if (cpuc->n_pebs == cpuc->n_large_pebs) 1128 + cpuc->lbr_stack.hw_idx = -1ULL; 1129 + else 1130 + cpuc->lbr_stack.hw_idx = intel_pmu_lbr_tos(); 1131 + 1126 1132 for (i = 0; i < x86_pmu.lbr_nr; i++) { 1127 1133 u64 info = lbr->lbr[i].info; 1128 1134 struct perf_branch_entry *e = &cpuc->lbr_entries[i];