Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull ARM KVM fixes from Paolo Bonzini:
- a series of fixes to deal with the aliasing between the sp and xzr
register
- a fix for the cache flush fix that went in -rc3
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
ARM/arm64: KVM: correct PTE uncachedness check
arm64: KVM: Get rid of old vcpu_reg()
arm64: KVM: Correctly handle zero register in system register accesses
arm64: KVM: Remove const from struct sys_reg_params
arm64: KVM: Correctly handle zero register during MMIO
+107
-89
+12
arch/arm/include/asm/kvm_emulate.h
+12
arch/arm/include/asm/kvm_emulate.h
···
28
28
unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
29
29
unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu);
30
30
31
+
static inline unsigned long vcpu_get_reg(struct kvm_vcpu *vcpu,
32
+
u8 reg_num)
33
+
{
34
+
return *vcpu_reg(vcpu, reg_num);
35
+
}
36
+
37
+
static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
38
+
unsigned long val)
39
+
{
40
+
*vcpu_reg(vcpu, reg_num) = val;
41
+
}
42
+
31
43
bool kvm_condition_valid(struct kvm_vcpu *vcpu);
32
44
void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr);
33
45
void kvm_inject_undefined(struct kvm_vcpu *vcpu);
+3
-2
arch/arm/kvm/mmio.c
+3
-2
arch/arm/kvm/mmio.c
···
115
115
trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr,
116
116
data);
117
117
data = vcpu_data_host_to_guest(vcpu, data, len);
118
-
*vcpu_reg(vcpu, vcpu->arch.mmio_decode.rt) = data;
118
+
vcpu_set_reg(vcpu, vcpu->arch.mmio_decode.rt, data);
119
119
}
120
120
121
121
return 0;
···
186
186
rt = vcpu->arch.mmio_decode.rt;
187
187
188
188
if (is_write) {
189
-
data = vcpu_data_guest_to_host(vcpu, *vcpu_reg(vcpu, rt), len);
189
+
data = vcpu_data_guest_to_host(vcpu, vcpu_get_reg(vcpu, rt),
190
+
len);
190
191
191
192
trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, len, fault_ipa, data);
192
193
mmio_write_buf(data_buf, len, data);
+2
-2
arch/arm/kvm/mmu.c
+2
-2
arch/arm/kvm/mmu.c
···
218
218
kvm_tlb_flush_vmid_ipa(kvm, addr);
219
219
220
220
/* No need to invalidate the cache for device mappings */
221
-
if (!kvm_is_device_pfn(__phys_to_pfn(addr)))
221
+
if (!kvm_is_device_pfn(pte_pfn(old_pte)))
222
222
kvm_flush_dcache_pte(old_pte);
223
223
224
224
put_page(virt_to_page(pte));
···
310
310
311
311
pte = pte_offset_kernel(pmd, addr);
312
312
do {
313
-
if (!pte_none(*pte) && !kvm_is_device_pfn(__phys_to_pfn(addr)))
313
+
if (!pte_none(*pte) && !kvm_is_device_pfn(pte_pfn(*pte)))
314
314
kvm_flush_dcache_pte(*pte);
315
315
} while (pte++, addr += PAGE_SIZE, addr != end);
316
316
}
+10
-10
arch/arm/kvm/psci.c
+10
-10
arch/arm/kvm/psci.c
···
75
75
unsigned long context_id;
76
76
phys_addr_t target_pc;
77
77
78
-
cpu_id = *vcpu_reg(source_vcpu, 1) & MPIDR_HWID_BITMASK;
78
+
cpu_id = vcpu_get_reg(source_vcpu, 1) & MPIDR_HWID_BITMASK;
79
79
if (vcpu_mode_is_32bit(source_vcpu))
80
80
cpu_id &= ~((u32) 0);
81
81
···
94
94
return PSCI_RET_INVALID_PARAMS;
95
95
}
96
96
97
-
target_pc = *vcpu_reg(source_vcpu, 2);
98
-
context_id = *vcpu_reg(source_vcpu, 3);
97
+
target_pc = vcpu_get_reg(source_vcpu, 2);
98
+
context_id = vcpu_get_reg(source_vcpu, 3);
99
99
100
100
kvm_reset_vcpu(vcpu);
101
101
···
114
114
* NOTE: We always update r0 (or x0) because for PSCI v0.1
115
115
* the general puspose registers are undefined upon CPU_ON.
116
116
*/
117
-
*vcpu_reg(vcpu, 0) = context_id;
117
+
vcpu_set_reg(vcpu, 0, context_id);
118
118
vcpu->arch.power_off = false;
119
119
smp_mb(); /* Make sure the above is visible */
120
120
···
134
134
struct kvm *kvm = vcpu->kvm;
135
135
struct kvm_vcpu *tmp;
136
136
137
-
target_affinity = *vcpu_reg(vcpu, 1);
138
-
lowest_affinity_level = *vcpu_reg(vcpu, 2);
137
+
target_affinity = vcpu_get_reg(vcpu, 1);
138
+
lowest_affinity_level = vcpu_get_reg(vcpu, 2);
139
139
140
140
/* Determine target affinity mask */
141
141
target_affinity_mask = psci_affinity_mask(lowest_affinity_level);
···
209
209
static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu)
210
210
{
211
211
int ret = 1;
212
-
unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0);
212
+
unsigned long psci_fn = vcpu_get_reg(vcpu, 0) & ~((u32) 0);
213
213
unsigned long val;
214
214
215
215
switch (psci_fn) {
···
273
273
break;
274
274
}
275
275
276
-
*vcpu_reg(vcpu, 0) = val;
276
+
vcpu_set_reg(vcpu, 0, val);
277
277
return ret;
278
278
}
279
279
280
280
static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu)
281
281
{
282
-
unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0);
282
+
unsigned long psci_fn = vcpu_get_reg(vcpu, 0) & ~((u32) 0);
283
283
unsigned long val;
284
284
285
285
switch (psci_fn) {
···
295
295
break;
296
296
}
297
297
298
-
*vcpu_reg(vcpu, 0) = val;
298
+
vcpu_set_reg(vcpu, 0, val);
299
299
return 1;
300
300
}
301
301
+13
-5
arch/arm64/include/asm/kvm_emulate.h
+13
-5
arch/arm64/include/asm/kvm_emulate.h
···
100
100
}
101
101
102
102
/*
103
-
* vcpu_reg should always be passed a register number coming from a
104
-
* read of ESR_EL2. Otherwise, it may give the wrong result on AArch32
105
-
* with banked registers.
103
+
* vcpu_get_reg and vcpu_set_reg should always be passed a register number
104
+
* coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
105
+
* AArch32 with banked registers.
106
106
*/
107
-
static inline unsigned long *vcpu_reg(const struct kvm_vcpu *vcpu, u8 reg_num)
107
+
static inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
108
+
u8 reg_num)
108
109
{
109
-
return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.regs[reg_num];
110
+
return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];
111
+
}
112
+
113
+
static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
114
+
unsigned long val)
115
+
{
116
+
if (reg_num != 31)
117
+
vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val;
110
118
}
111
119
112
120
/* Get vcpu SPSR for current mode */
+1
-1
arch/arm64/kvm/handle_exit.c
+1
-1
arch/arm64/kvm/handle_exit.c
+60
-63
arch/arm64/kvm/sys_regs.c
+60
-63
arch/arm64/kvm/sys_regs.c
···
78
78
* See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
79
79
*/
80
80
static bool access_dcsw(struct kvm_vcpu *vcpu,
81
-
const struct sys_reg_params *p,
81
+
struct sys_reg_params *p,
82
82
const struct sys_reg_desc *r)
83
83
{
84
84
if (!p->is_write)
···
94
94
* sys_regs and leave it in complete control of the caches.
95
95
*/
96
96
static bool access_vm_reg(struct kvm_vcpu *vcpu,
97
-
const struct sys_reg_params *p,
97
+
struct sys_reg_params *p,
98
98
const struct sys_reg_desc *r)
99
99
{
100
-
unsigned long val;
101
100
bool was_enabled = vcpu_has_cache_enabled(vcpu);
102
101
103
102
BUG_ON(!p->is_write);
104
103
105
-
val = *vcpu_reg(vcpu, p->Rt);
106
104
if (!p->is_aarch32) {
107
-
vcpu_sys_reg(vcpu, r->reg) = val;
105
+
vcpu_sys_reg(vcpu, r->reg) = p->regval;
108
106
} else {
109
107
if (!p->is_32bit)
110
-
vcpu_cp15_64_high(vcpu, r->reg) = val >> 32;
111
-
vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL;
108
+
vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
109
+
vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
112
110
}
113
111
114
112
kvm_toggle_cache(vcpu, was_enabled);
···
120
122
* for both AArch64 and AArch32 accesses.
121
123
*/
122
124
static bool access_gic_sgi(struct kvm_vcpu *vcpu,
123
-
const struct sys_reg_params *p,
125
+
struct sys_reg_params *p,
124
126
const struct sys_reg_desc *r)
125
127
{
126
-
u64 val;
127
-
128
128
if (!p->is_write)
129
129
return read_from_write_only(vcpu, p);
130
130
131
-
val = *vcpu_reg(vcpu, p->Rt);
132
-
vgic_v3_dispatch_sgi(vcpu, val);
131
+
vgic_v3_dispatch_sgi(vcpu, p->regval);
133
132
134
133
return true;
135
134
}
136
135
137
136
static bool trap_raz_wi(struct kvm_vcpu *vcpu,
138
-
const struct sys_reg_params *p,
137
+
struct sys_reg_params *p,
139
138
const struct sys_reg_desc *r)
140
139
{
141
140
if (p->is_write)
···
142
147
}
143
148
144
149
static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
145
-
const struct sys_reg_params *p,
150
+
struct sys_reg_params *p,
146
151
const struct sys_reg_desc *r)
147
152
{
148
153
if (p->is_write) {
149
154
return ignore_write(vcpu, p);
150
155
} else {
151
-
*vcpu_reg(vcpu, p->Rt) = (1 << 3);
156
+
p->regval = (1 << 3);
152
157
return true;
153
158
}
154
159
}
155
160
156
161
static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
157
-
const struct sys_reg_params *p,
162
+
struct sys_reg_params *p,
158
163
const struct sys_reg_desc *r)
159
164
{
160
165
if (p->is_write) {
···
162
167
} else {
163
168
u32 val;
164
169
asm volatile("mrs %0, dbgauthstatus_el1" : "=r" (val));
165
-
*vcpu_reg(vcpu, p->Rt) = val;
170
+
p->regval = val;
166
171
return true;
167
172
}
168
173
}
···
195
200
* now use the debug registers.
196
201
*/
197
202
static bool trap_debug_regs(struct kvm_vcpu *vcpu,
198
-
const struct sys_reg_params *p,
203
+
struct sys_reg_params *p,
199
204
const struct sys_reg_desc *r)
200
205
{
201
206
if (p->is_write) {
202
-
vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
207
+
vcpu_sys_reg(vcpu, r->reg) = p->regval;
203
208
vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
204
209
} else {
205
-
*vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg);
210
+
p->regval = vcpu_sys_reg(vcpu, r->reg);
206
211
}
207
212
208
-
trace_trap_reg(__func__, r->reg, p->is_write, *vcpu_reg(vcpu, p->Rt));
213
+
trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
209
214
210
215
return true;
211
216
}
···
220
225
* hyp.S code switches between host and guest values in future.
221
226
*/
222
227
static inline void reg_to_dbg(struct kvm_vcpu *vcpu,
223
-
const struct sys_reg_params *p,
228
+
struct sys_reg_params *p,
224
229
u64 *dbg_reg)
225
230
{
226
-
u64 val = *vcpu_reg(vcpu, p->Rt);
231
+
u64 val = p->regval;
227
232
228
233
if (p->is_32bit) {
229
234
val &= 0xffffffffUL;
···
235
240
}
236
241
237
242
static inline void dbg_to_reg(struct kvm_vcpu *vcpu,
238
-
const struct sys_reg_params *p,
243
+
struct sys_reg_params *p,
239
244
u64 *dbg_reg)
240
245
{
241
-
u64 val = *dbg_reg;
242
-
246
+
p->regval = *dbg_reg;
243
247
if (p->is_32bit)
244
-
val &= 0xffffffffUL;
245
-
246
-
*vcpu_reg(vcpu, p->Rt) = val;
248
+
p->regval &= 0xffffffffUL;
247
249
}
248
250
249
251
static inline bool trap_bvr(struct kvm_vcpu *vcpu,
250
-
const struct sys_reg_params *p,
252
+
struct sys_reg_params *p,
251
253
const struct sys_reg_desc *rd)
252
254
{
253
255
u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
···
286
294
}
287
295
288
296
static inline bool trap_bcr(struct kvm_vcpu *vcpu,
289
-
const struct sys_reg_params *p,
297
+
struct sys_reg_params *p,
290
298
const struct sys_reg_desc *rd)
291
299
{
292
300
u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
···
329
337
}
330
338
331
339
static inline bool trap_wvr(struct kvm_vcpu *vcpu,
332
-
const struct sys_reg_params *p,
340
+
struct sys_reg_params *p,
333
341
const struct sys_reg_desc *rd)
334
342
{
335
343
u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
···
372
380
}
373
381
374
382
static inline bool trap_wcr(struct kvm_vcpu *vcpu,
375
-
const struct sys_reg_params *p,
383
+
struct sys_reg_params *p,
376
384
const struct sys_reg_desc *rd)
377
385
{
378
386
u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
···
679
687
};
680
688
681
689
static bool trap_dbgidr(struct kvm_vcpu *vcpu,
682
-
const struct sys_reg_params *p,
690
+
struct sys_reg_params *p,
683
691
const struct sys_reg_desc *r)
684
692
{
685
693
if (p->is_write) {
···
689
697
u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
690
698
u32 el3 = !!cpuid_feature_extract_field(pfr, ID_AA64PFR0_EL3_SHIFT);
691
699
692
-
*vcpu_reg(vcpu, p->Rt) = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
693
-
(((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
694
-
(((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) |
695
-
(6 << 16) | (el3 << 14) | (el3 << 12));
700
+
p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
701
+
(((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
702
+
(((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
703
+
| (6 << 16) | (el3 << 14) | (el3 << 12));
696
704
return true;
697
705
}
698
706
}
699
707
700
708
static bool trap_debug32(struct kvm_vcpu *vcpu,
701
-
const struct sys_reg_params *p,
709
+
struct sys_reg_params *p,
702
710
const struct sys_reg_desc *r)
703
711
{
704
712
if (p->is_write) {
705
-
vcpu_cp14(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
713
+
vcpu_cp14(vcpu, r->reg) = p->regval;
706
714
vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
707
715
} else {
708
-
*vcpu_reg(vcpu, p->Rt) = vcpu_cp14(vcpu, r->reg);
716
+
p->regval = vcpu_cp14(vcpu, r->reg);
709
717
}
710
718
711
719
return true;
···
723
731
*/
724
732
725
733
static inline bool trap_xvr(struct kvm_vcpu *vcpu,
726
-
const struct sys_reg_params *p,
734
+
struct sys_reg_params *p,
727
735
const struct sys_reg_desc *rd)
728
736
{
729
737
u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
···
732
740
u64 val = *dbg_reg;
733
741
734
742
val &= 0xffffffffUL;
735
-
val |= *vcpu_reg(vcpu, p->Rt) << 32;
743
+
val |= p->regval << 32;
736
744
*dbg_reg = val;
737
745
738
746
vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
739
747
} else {
740
-
*vcpu_reg(vcpu, p->Rt) = *dbg_reg >> 32;
748
+
p->regval = *dbg_reg >> 32;
741
749
}
742
750
743
751
trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
···
983
991
* Return 0 if the access has been handled, and -1 if not.
984
992
*/
985
993
static int emulate_cp(struct kvm_vcpu *vcpu,
986
-
const struct sys_reg_params *params,
994
+
struct sys_reg_params *params,
987
995
const struct sys_reg_desc *table,
988
996
size_t num)
989
997
{
···
1054
1062
{
1055
1063
struct sys_reg_params params;
1056
1064
u32 hsr = kvm_vcpu_get_hsr(vcpu);
1065
+
int Rt = (hsr >> 5) & 0xf;
1057
1066
int Rt2 = (hsr >> 10) & 0xf;
1058
1067
1059
1068
params.is_aarch32 = true;
1060
1069
params.is_32bit = false;
1061
1070
params.CRm = (hsr >> 1) & 0xf;
1062
-
params.Rt = (hsr >> 5) & 0xf;
1063
1071
params.is_write = ((hsr & 1) == 0);
1064
1072
1065
1073
params.Op0 = 0;
···
1068
1076
params.CRn = 0;
1069
1077
1070
1078
/*
1071
-
* Massive hack here. Store Rt2 in the top 32bits so we only
1072
-
* have one register to deal with. As we use the same trap
1079
+
* Make a 64-bit value out of Rt and Rt2. As we use the same trap
1073
1080
* backends between AArch32 and AArch64, we get away with it.
1074
1081
*/
1075
1082
if (params.is_write) {
1076
-
u64 val = *vcpu_reg(vcpu, params.Rt);
1077
-
val &= 0xffffffff;
1078
-
val |= *vcpu_reg(vcpu, Rt2) << 32;
1079
-
*vcpu_reg(vcpu, params.Rt) = val;
1083
+
params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1084
+
params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
1080
1085
}
1081
1086
1082
1087
if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific))
···
1084
1095
unhandled_cp_access(vcpu, ¶ms);
1085
1096
1086
1097
out:
1087
-
/* Do the opposite hack for the read side */
1098
+
/* Split up the value between registers for the read side */
1088
1099
if (!params.is_write) {
1089
-
u64 val = *vcpu_reg(vcpu, params.Rt);
1090
-
val >>= 32;
1091
-
*vcpu_reg(vcpu, Rt2) = val;
1100
+
vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1101
+
vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
1092
1102
}
1093
1103
1094
1104
return 1;
···
1106
1118
{
1107
1119
struct sys_reg_params params;
1108
1120
u32 hsr = kvm_vcpu_get_hsr(vcpu);
1121
+
int Rt = (hsr >> 5) & 0xf;
1109
1122
1110
1123
params.is_aarch32 = true;
1111
1124
params.is_32bit = true;
1112
1125
params.CRm = (hsr >> 1) & 0xf;
1113
-
params.Rt = (hsr >> 5) & 0xf;
1126
+
params.regval = vcpu_get_reg(vcpu, Rt);
1114
1127
params.is_write = ((hsr & 1) == 0);
1115
1128
params.CRn = (hsr >> 10) & 0xf;
1116
1129
params.Op0 = 0;
1117
1130
params.Op1 = (hsr >> 14) & 0x7;
1118
1131
params.Op2 = (hsr >> 17) & 0x7;
1119
1132
1120
-
if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific))
1133
+
if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific) ||
1134
+
!emulate_cp(vcpu, ¶ms, global, nr_global)) {
1135
+
if (!params.is_write)
1136
+
vcpu_set_reg(vcpu, Rt, params.regval);
1121
1137
return 1;
1122
-
if (!emulate_cp(vcpu, ¶ms, global, nr_global))
1123
-
return 1;
1138
+
}
1124
1139
1125
1140
unhandled_cp_access(vcpu, ¶ms);
1126
1141
return 1;
···
1166
1175
}
1167
1176
1168
1177
static int emulate_sys_reg(struct kvm_vcpu *vcpu,
1169
-
const struct sys_reg_params *params)
1178
+
struct sys_reg_params *params)
1170
1179
{
1171
1180
size_t num;
1172
1181
const struct sys_reg_desc *table, *r;
···
1221
1230
{
1222
1231
struct sys_reg_params params;
1223
1232
unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1233
+
int Rt = (esr >> 5) & 0x1f;
1234
+
int ret;
1224
1235
1225
1236
trace_kvm_handle_sys_reg(esr);
1226
1237
···
1233
1240
params.CRn = (esr >> 10) & 0xf;
1234
1241
params.CRm = (esr >> 1) & 0xf;
1235
1242
params.Op2 = (esr >> 17) & 0x7;
1236
-
params.Rt = (esr >> 5) & 0x1f;
1243
+
params.regval = vcpu_get_reg(vcpu, Rt);
1237
1244
params.is_write = !(esr & 1);
1238
1245
1239
-
return emulate_sys_reg(vcpu, ¶ms);
1246
+
ret = emulate_sys_reg(vcpu, ¶ms);
1247
+
1248
+
if (!params.is_write)
1249
+
vcpu_set_reg(vcpu, Rt, params.regval);
1250
+
return ret;
1240
1251
}
1241
1252
1242
1253
/******************************************************************************
+4
-4
arch/arm64/kvm/sys_regs.h
+4
-4
arch/arm64/kvm/sys_regs.h
···
28
28
u8 CRn;
29
29
u8 CRm;
30
30
u8 Op2;
31
-
u8 Rt;
31
+
u64 regval;
32
32
bool is_write;
33
33
bool is_aarch32;
34
34
bool is_32bit; /* Only valid if is_aarch32 is true */
···
44
44
45
45
/* Trapped access from guest, if non-NULL. */
46
46
bool (*access)(struct kvm_vcpu *,
47
-
const struct sys_reg_params *,
47
+
struct sys_reg_params *,
48
48
const struct sys_reg_desc *);
49
49
50
50
/* Initialization for vcpu. */
···
77
77
}
78
78
79
79
static inline bool read_zero(struct kvm_vcpu *vcpu,
80
-
const struct sys_reg_params *p)
80
+
struct sys_reg_params *p)
81
81
{
82
-
*vcpu_reg(vcpu, p->Rt) = 0;
82
+
p->regval = 0;
83
83
return true;
84
84
}
85
85
+2
-2
arch/arm64/kvm/sys_regs_generic_v8.c
+2
-2
arch/arm64/kvm/sys_regs_generic_v8.c
···
31
31
#include "sys_regs.h"
32
32
33
33
static bool access_actlr(struct kvm_vcpu *vcpu,
34
-
const struct sys_reg_params *p,
34
+
struct sys_reg_params *p,
35
35
const struct sys_reg_desc *r)
36
36
{
37
37
if (p->is_write)
38
38
return ignore_write(vcpu, p);
39
39
40
-
*vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, ACTLR_EL1);
40
+
p->regval = vcpu_sys_reg(vcpu, ACTLR_EL1);
41
41
return true;
42
42
}
43
43