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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
Merge branch 'net-stmmac-mdio-related-cleanups'
Russell King says:
====================
net: stmmac: mdio related cleanups
The first four patches clean up the MDC clock divisor selection code,
turning the three different ways we choose a divisor into tabular form,
rather than doing the selection purely in code.
Convert MDIO to use field_prep() which allows a non-constant mask to be
used when preparing fields.
Then use u32 and the associated typed GENMASK for MDIO register field
definitions.
Finally, an extra couple of patches that use appropriate types in
struct mdio_bus_data.
====================
Link: https://patch.msgid.link/aald--qJquWGIvmO@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+92
-97
+4
-6
drivers/net/ethernet/stmicro/stmmac/common.h
+4
-6
drivers/net/ethernet/stmicro/stmmac/common.h
···
257
257
(sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
258
258
259
259
/* CSR Frequency Access Defines*/
260
+
#define CSR_F_20M 20000000
260
261
#define CSR_F_35M 35000000
261
262
#define CSR_F_60M 60000000
262
263
#define CSR_F_100M 100000000
···
608
607
struct mii_regs {
609
608
unsigned int addr; /* MII Address */
610
609
unsigned int data; /* MII Data */
611
-
unsigned int addr_shift; /* MII address shift */
612
-
unsigned int reg_shift; /* MII reg shift */
613
-
unsigned int addr_mask; /* MII address mask */
614
-
unsigned int reg_mask; /* MII reg mask */
615
-
unsigned int clk_csr_shift;
616
-
unsigned int clk_csr_mask;
610
+
u32 addr_mask; /* MII address mask */
611
+
u32 reg_mask; /* MII reg mask */
612
+
u32 clk_csr_mask;
617
613
};
618
614
619
615
struct mac_device_info {
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
···
699
699
/* Intel mgbe SGMII interface uses pcs-xcps */
700
700
if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
701
701
plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
702
-
plat->mdio_bus_data->pcs_mask = BIT(INTEL_MGBE_XPCS_ADDR);
702
+
plat->mdio_bus_data->pcs_mask = BIT_U32(INTEL_MGBE_XPCS_ADDR);
703
703
plat->mdio_bus_data->default_an_inband = true;
704
704
plat->select_pcs = intel_mgbe_select_pcs;
705
705
}
+4
-7
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+4
-7
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
···
168
168
loongson_default_data(pdev, plat);
169
169
170
170
plat->phy_interface = PHY_INTERFACE_MODE_GMII;
171
-
plat->mdio_bus_data->phy_mask = ~(u32)BIT(2);
171
+
plat->mdio_bus_data->phy_mask = ~BIT_U32(2);
172
172
plat->fix_mac_speed = loongson_gnet_fix_speed;
173
173
174
174
return 0;
···
367
367
mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
368
368
mac->mii.addr = GMAC_MII_ADDR;
369
369
mac->mii.data = GMAC_MII_DATA;
370
-
mac->mii.addr_shift = 11;
371
-
mac->mii.addr_mask = 0x0000F800;
372
-
mac->mii.reg_shift = 6;
373
-
mac->mii.reg_mask = 0x000007C0;
374
-
mac->mii.clk_csr_shift = 2;
375
-
mac->mii.clk_csr_mask = GENMASK(5, 2);
370
+
mac->mii.addr_mask = GENMASK_U32(15, 11);
371
+
mac->mii.reg_mask = GENMASK_U32(10, 6);
372
+
mac->mii.clk_csr_mask = GENMASK_U32(5, 2);
376
373
377
374
return 0;
378
375
}
+3
-6
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+3
-6
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
···
1063
1063
mac->link.duplex = EMAC_DUPLEX_FULL;
1064
1064
mac->mii.addr = EMAC_MDIO_CMD;
1065
1065
mac->mii.data = EMAC_MDIO_DATA;
1066
-
mac->mii.reg_shift = 4;
1067
-
mac->mii.reg_mask = GENMASK(8, 4);
1068
-
mac->mii.addr_shift = 12;
1069
-
mac->mii.addr_mask = GENMASK(16, 12);
1070
-
mac->mii.clk_csr_shift = 20;
1071
-
mac->mii.clk_csr_mask = GENMASK(22, 20);
1066
+
mac->mii.reg_mask = GENMASK_U32(8, 4);
1067
+
mac->mii.addr_mask = GENMASK_U32(16, 12);
1068
+
mac->mii.clk_csr_mask = GENMASK_U32(22, 20);
1072
1069
mac->unicast_filter_entries = 8;
1073
1070
1074
1071
/* Synopsys Id is not available */
+3
-6
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+3
-6
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
···
496
496
mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
497
497
mac->mii.addr = GMAC_MII_ADDR;
498
498
mac->mii.data = GMAC_MII_DATA;
499
-
mac->mii.addr_shift = 11;
500
-
mac->mii.addr_mask = 0x0000F800;
501
-
mac->mii.reg_shift = 6;
502
-
mac->mii.reg_mask = 0x000007C0;
503
-
mac->mii.clk_csr_shift = 2;
504
-
mac->mii.clk_csr_mask = GENMASK(5, 2);
499
+
mac->mii.addr_mask = GENMASK_U32(15, 11);
500
+
mac->mii.reg_mask = GENMASK_U32(10, 6);
501
+
mac->mii.clk_csr_mask = GENMASK_U32(5, 2);
505
502
506
503
return 0;
507
504
}
+3
-6
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+3
-6
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
···
184
184
mac->link.speed_mask = MAC_CONTROL_PS;
185
185
mac->mii.addr = MAC_MII_ADDR;
186
186
mac->mii.data = MAC_MII_DATA;
187
-
mac->mii.addr_shift = 11;
188
-
mac->mii.addr_mask = 0x0000F800;
189
-
mac->mii.reg_shift = 6;
190
-
mac->mii.reg_mask = 0x000007C0;
191
-
mac->mii.clk_csr_shift = 2;
192
-
mac->mii.clk_csr_mask = GENMASK(5, 2);
187
+
mac->mii.addr_mask = GENMASK_U32(15, 11);
188
+
mac->mii.reg_mask = GENMASK_U32(10, 6);
189
+
mac->mii.clk_csr_mask = GENMASK_U32(5, 2);
193
190
194
191
return 0;
195
192
}
+3
-6
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+3
-6
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
···
1030
1030
mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1031
1031
mac->mii.addr = GMAC_MDIO_ADDR;
1032
1032
mac->mii.data = GMAC_MDIO_DATA;
1033
-
mac->mii.addr_shift = 21;
1034
-
mac->mii.addr_mask = GENMASK(25, 21);
1035
-
mac->mii.reg_shift = 16;
1036
-
mac->mii.reg_mask = GENMASK(20, 16);
1037
-
mac->mii.clk_csr_shift = 8;
1038
-
mac->mii.clk_csr_mask = GENMASK(11, 8);
1033
+
mac->mii.addr_mask = GENMASK_U32(25, 21);
1034
+
mac->mii.reg_mask = GENMASK_U32(20, 16);
1035
+
mac->mii.clk_csr_mask = GENMASK_U32(11, 8);
1039
1036
mac->num_vlan = stmmac_get_num_vlan(priv->ioaddr);
1040
1037
1041
1038
return 0;
+6
-12
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+6
-12
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
···
1551
1551
1552
1552
mac->mii.addr = XGMAC_MDIO_ADDR;
1553
1553
mac->mii.data = XGMAC_MDIO_DATA;
1554
-
mac->mii.addr_shift = 16;
1555
-
mac->mii.addr_mask = GENMASK(20, 16);
1556
-
mac->mii.reg_shift = 0;
1557
-
mac->mii.reg_mask = GENMASK(15, 0);
1558
-
mac->mii.clk_csr_shift = 19;
1559
-
mac->mii.clk_csr_mask = GENMASK(21, 19);
1554
+
mac->mii.addr_mask = GENMASK_U32(20, 16);
1555
+
mac->mii.reg_mask = GENMASK_U32(15, 0);
1556
+
mac->mii.clk_csr_mask = GENMASK_U32(21, 19);
1560
1557
mac->num_vlan = stmmac_get_num_vlan(priv->ioaddr);
1561
1558
1562
1559
return 0;
···
1591
1594
1592
1595
mac->mii.addr = XGMAC_MDIO_ADDR;
1593
1596
mac->mii.data = XGMAC_MDIO_DATA;
1594
-
mac->mii.addr_shift = 16;
1595
-
mac->mii.addr_mask = GENMASK(20, 16);
1596
-
mac->mii.reg_shift = 0;
1597
-
mac->mii.reg_mask = GENMASK(15, 0);
1598
-
mac->mii.clk_csr_shift = 19;
1599
-
mac->mii.clk_csr_mask = GENMASK(21, 19);
1597
+
mac->mii.addr_mask = GENMASK_U32(20, 16);
1598
+
mac->mii.reg_mask = GENMASK_U32(15, 0);
1599
+
mac->mii.clk_csr_mask = GENMASK_U32(21, 19);
1600
1600
1601
1601
return 0;
1602
1602
}
+62
-44
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+62
-44
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
···
234
234
{
235
235
const struct mii_regs *mii_regs = &priv->hw->mii;
236
236
237
-
return ((pa << mii_regs->addr_shift) & mii_regs->addr_mask) |
238
-
((gr << mii_regs->reg_shift) & mii_regs->reg_mask) |
237
+
return field_prep(mii_regs->addr_mask, pa) |
238
+
field_prep(mii_regs->reg_mask, gr) |
239
239
priv->gmii_address_bus_config |
240
240
MII_ADDR_GBUSY;
241
241
}
···
473
473
priv->hw->xpcs = NULL;
474
474
}
475
475
476
+
struct stmmac_clk_rate {
477
+
unsigned long rate;
478
+
u8 cr;
479
+
};
480
+
481
+
/* The standard clk_csr_i to GMII_Address CR field mapping. The rate provided
482
+
* in this table is the exclusive maximum frequency for the divisor. The
483
+
* comments for each entry give the divisor and the resulting range of MDC
484
+
* clock frequencies.
485
+
*/
486
+
static const struct stmmac_clk_rate stmmac_std_csr_to_mdc[] = {
487
+
{ CSR_F_800M, ~0 },
488
+
{ CSR_F_500M, STMMAC_CSR_500_800M },
489
+
{ CSR_F_300M, STMMAC_CSR_300_500M },
490
+
{ CSR_F_250M, STMMAC_CSR_250_300M },
491
+
{ CSR_F_150M, STMMAC_CSR_150_250M },
492
+
{ CSR_F_100M, STMMAC_CSR_100_150M },
493
+
{ CSR_F_60M, STMMAC_CSR_60_100M },
494
+
{ CSR_F_35M, STMMAC_CSR_35_60M },
495
+
{ CSR_F_20M, STMMAC_CSR_20_35M },
496
+
{ 0, ~0 },
497
+
};
498
+
499
+
/* The sun8i clk_csr_i to GMII_Address CR field mapping uses rate as the
500
+
* exclusive minimum frequency for the divisor. Note that the last entry
501
+
* is valid and also acts as the sentinel.
502
+
*/
503
+
static const struct stmmac_clk_rate stmmac_sun8i_csr_to_mdc[] = {
504
+
{ 160000000, 3 },
505
+
{ 80000000, 2 },
506
+
{ 40000000, 1 },
507
+
{ 0, 0 },
508
+
};
509
+
510
+
/* The xgmac clk_csr_i to GMII_Address CR field mapping similarly uses rate
511
+
* as the exclusive minimum frequency for the divisor, and again the last
512
+
* entry is valid and also the sentinel.
513
+
*/
514
+
static const struct stmmac_clk_rate stmmac_xgmac_csr_to_mdc[] = {
515
+
{ 400000000, 5 },
516
+
{ 350000000, 4 },
517
+
{ 300000000, 3 },
518
+
{ 250000000, 2 },
519
+
{ 150000000, 1 },
520
+
{ 0, 0 },
521
+
};
522
+
476
523
/**
477
524
* stmmac_clk_csr_set - dynamically set the MDC clock
478
525
* @priv: driver private structure
···
535
488
*/
536
489
static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)
537
490
{
491
+
const struct stmmac_clk_rate *rates;
538
492
unsigned long clk_rate;
539
493
u32 value = ~0;
494
+
int i;
540
495
541
496
clk_rate = clk_get_rate(priv->plat->stmmac_clk);
542
497
···
549
500
* the frequency of clk_csr_i. So we do not change the default
550
501
* divider.
551
502
*/
552
-
if (clk_rate < CSR_F_35M)
553
-
value = STMMAC_CSR_20_35M;
554
-
else if (clk_rate < CSR_F_60M)
555
-
value = STMMAC_CSR_35_60M;
556
-
else if (clk_rate < CSR_F_100M)
557
-
value = STMMAC_CSR_60_100M;
558
-
else if (clk_rate < CSR_F_150M)
559
-
value = STMMAC_CSR_100_150M;
560
-
else if (clk_rate < CSR_F_250M)
561
-
value = STMMAC_CSR_150_250M;
562
-
else if (clk_rate <= CSR_F_300M)
563
-
value = STMMAC_CSR_250_300M;
564
-
else if (clk_rate < CSR_F_500M)
565
-
value = STMMAC_CSR_300_500M;
566
-
else if (clk_rate < CSR_F_800M)
567
-
value = STMMAC_CSR_500_800M;
503
+
rates = stmmac_std_csr_to_mdc;
504
+
if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I)
505
+
rates = stmmac_sun8i_csr_to_mdc;
506
+
if (priv->plat->core_type == DWMAC_CORE_XGMAC)
507
+
rates = stmmac_xgmac_csr_to_mdc;
568
508
569
-
if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) {
570
-
if (clk_rate > 160000000)
571
-
value = 0x03;
572
-
else if (clk_rate > 80000000)
573
-
value = 0x02;
574
-
else if (clk_rate > 40000000)
575
-
value = 0x01;
576
-
else
577
-
value = 0;
578
-
}
579
-
580
-
if (priv->plat->core_type == DWMAC_CORE_XGMAC) {
581
-
if (clk_rate > 400000000)
582
-
value = 0x5;
583
-
else if (clk_rate > 350000000)
584
-
value = 0x4;
585
-
else if (clk_rate > 300000000)
586
-
value = 0x3;
587
-
else if (clk_rate > 250000000)
588
-
value = 0x2;
589
-
else if (clk_rate > 150000000)
590
-
value = 0x1;
591
-
else
592
-
value = 0x0;
593
-
}
509
+
for (i = 0; rates[i].rate; i++)
510
+
if (clk_rate > rates[i].rate)
511
+
break;
512
+
if (rates[i].cr != (u8)~0)
513
+
value = rates[i].cr;
594
514
595
515
return value;
596
516
}
···
577
559
else
578
560
value = stmmac_clk_csr_set(priv);
579
561
580
-
value <<= priv->hw->mii.clk_csr_shift;
562
+
value <<= __ffs(priv->hw->mii.clk_csr_mask);
581
563
582
564
if (value & ~priv->hw->mii.clk_csr_mask)
583
565
dev_warn(priv->device,
+3
-3
include/linux/stmmac.h
+3
-3
include/linux/stmmac.h
···
84
84
/* Platfrom data for platform device structure's platform_data field */
85
85
86
86
struct stmmac_mdio_bus_data {
87
-
unsigned int phy_mask;
88
-
unsigned int pcs_mask;
89
-
unsigned int default_an_inband;
87
+
u32 phy_mask;
88
+
u32 pcs_mask;
90
89
int *irqs;
91
90
int probed_phy_irq;
92
91
bool needs_reset;
92
+
bool default_an_inband;
93
93
};
94
94
95
95
struct stmmac_dma_cfg {