tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'riscv-for-linus-6.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

- A few DT bindings fixes to more closely align the ISA string
requirements between the bindings and the ISA manual.

- A handful of build error/warning fixes.

- A fix to move init_cpu_topology() later in the boot flow, so it can
allocate memory.

- The IRC channel is now in the MAINTAINERS file, so it's easier to
find.

* tag 'riscv-for-linus-6.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Move call to init_cpu_topology() to later initialization stage
riscv/kprobe: Fix instruction simulation of JALR
riscv: fix -Wundef warning for CONFIG_RISCV_BOOT_SPINWAIT
MAINTAINERS: add an IRC entry for RISC-V
RISC-V: fix compile error from deduplicated __ALTERNATIVE_CFG_2
dt-bindings: riscv: fix single letter canonical order
dt-bindings: riscv: fix underscore requirement for multi-letter extensions

Linus Torvalds db7c4673 e5eb2b22

+8 -6
+1 -1
Documentation/devicetree/bindings/riscv/cpus.yaml
··· 83 83 insensitive, letters in the riscv,isa string must be all 84 84 lowercase to simplify parsing. 85 85 $ref: "/schemas/types.yaml#/definitions/string" 86 - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ 86 + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ 87 87 88 88 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 89 89 timebase-frequency: false
+1
MAINTAINERS
··· 17960 17960 L: linux-riscv@lists.infradead.org 17961 17961 S: Supported 17962 17962 Q: https://patchwork.kernel.org/project/linux-riscv/list/ 17963 + C: irc://irc.libera.chat/riscv 17963 17964 P: Documentation/riscv/patch-acceptance.rst 17964 17965 T: git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git 17965 17966 F: arch/riscv/
+1 -1
arch/riscv/include/asm/alternative-macros.h
··· 46 46 47 47 .macro ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \ 48 48 new_c_2, vendor_id_2, errata_id_2, enable_2 49 - ALTERNATIVE_CFG \old_c, \new_c_1, \vendor_id_1, \errata_id_1, \enable_1 49 + ALTERNATIVE_CFG "\old_c", "\new_c_1", \vendor_id_1, \errata_id_1, \enable_1 50 50 ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2 51 51 .endm 52 52
+1 -1
arch/riscv/kernel/head.S
··· 326 326 call soc_early_init 327 327 tail start_kernel 328 328 329 - #if CONFIG_RISCV_BOOT_SPINWAIT 329 + #ifdef CONFIG_RISCV_BOOT_SPINWAIT 330 330 .Lsecondary_start: 331 331 /* Set trap vector to spin forever to help debug */ 332 332 la a3, .Lsecondary_park
+2 -2
arch/riscv/kernel/probes/simulate-insn.c
··· 71 71 u32 rd_index = (opcode >> 7) & 0x1f; 72 72 u32 rs1_index = (opcode >> 15) & 0x1f; 73 73 74 - ret = rv_insn_reg_set_val(regs, rd_index, addr + 4); 74 + ret = rv_insn_reg_get_val(regs, rs1_index, &base_addr); 75 75 if (!ret) 76 76 return ret; 77 77 78 - ret = rv_insn_reg_get_val(regs, rs1_index, &base_addr); 78 + ret = rv_insn_reg_set_val(regs, rd_index, addr + 4); 79 79 if (!ret) 80 80 return ret; 81 81
+2 -1
arch/riscv/kernel/smpboot.c
··· 39 39 40 40 void __init smp_prepare_boot_cpu(void) 41 41 { 42 - init_cpu_topology(); 43 42 } 44 43 45 44 void __init smp_prepare_cpus(unsigned int max_cpus) ··· 46 47 int cpuid; 47 48 int ret; 48 49 unsigned int curr_cpuid; 50 + 51 + init_cpu_topology(); 49 52 50 53 curr_cpuid = smp_processor_id(); 51 54 store_cpu_topology(curr_cpuid);