Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Add soc v1_0 ih client id table
To acommandate the specific ih client for soc v1_0
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Hawking Zhang
and committed by
Alex Deucher
db9ca58e
0c9ad472
+96
-8
+35
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+35
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
···
99
99
"MP1"
100
100
};
101
101
102
+
const char *soc_v1_0_ih_clientid_name[] = {
103
+
"IH",
104
+
"Reserved",
105
+
"ATHUB",
106
+
"BIF",
107
+
"Reserved",
108
+
"Reserved",
109
+
"Reserved",
110
+
"RLC",
111
+
"Reserved",
112
+
"Reserved",
113
+
"GFX",
114
+
"IMU",
115
+
"Reserved",
116
+
"Reserved",
117
+
"VCN1 or UVD1",
118
+
"THM",
119
+
"VCN or UVD",
120
+
"Reserved",
121
+
"VMC",
122
+
"Reserved",
123
+
"GRBM_CP",
124
+
"GC_AID",
125
+
"ROM_SMUIO",
126
+
"DF",
127
+
"Reserved",
128
+
"PWR",
129
+
"LSDMA",
130
+
"GC_UTCL2",
131
+
"nHT",
132
+
"Reserved",
133
+
"MP0",
134
+
"MP1",
135
+
};
136
+
102
137
const int node_id_to_phys_map[NODEID_MAX] = {
103
138
[AID0_NODEID] = 0,
104
139
[XCD0_NODEID] = 0,
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+3
-3
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+3
-3
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
···
1140
1140
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1141
1141
1142
1142
/* EOP Event */
1143
-
r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1143
+
r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP,
1144
1144
GFX_11_0_0__SRCID__CP_EOP_INTERRUPT,
1145
1145
&adev->gfx.eop_irq);
1146
1146
if (r)
1147
1147
return r;
1148
1148
1149
1149
/* Privileged reg */
1150
-
r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1150
+
r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP,
1151
1151
GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,
1152
1152
&adev->gfx.priv_reg_irq);
1153
1153
if (r)
1154
1154
return r;
1155
1155
1156
1156
/* Privileged inst */
1157
-
r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1157
+
r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP,
1158
1158
GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1159
1159
&adev->gfx.priv_inst_irq);
1160
1160
if (r)
+3
-3
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
+3
-3
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
···
124
124
write_fault = !!(entry->src_data[1] & 0x200000);
125
125
}
126
126
127
-
if (entry->client_id == SOC21_IH_CLIENTID_VMC) {
127
+
if (entry->client_id == SOC_V1_0_IH_CLIENTID_VMC) {
128
128
hub_name = "mmhub0";
129
129
vmhub = AMDGPU_MMHUB0(node_id / 4);
130
130
} else {
···
198
198
amdgpu_vm_put_task_info(task_info);
199
199
}
200
200
201
-
dev_err(adev->dev, " in page starting at address 0x%016llx from IH client %d\n",
202
-
addr, entry->client_id);
201
+
dev_err(adev->dev, " in page starting at address 0x%016llx from IH client %d (%s)\n",
202
+
addr, entry->client_id, soc_v1_0_ih_clientid_name[entry->client_id]);
203
203
204
204
if (amdgpu_sriov_vf(adev))
205
205
return 0;
+2
-2
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
+2
-2
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
···
1277
1277
u32 xcc_id;
1278
1278
1279
1279
/* SDMA trap event */
1280
-
r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1280
+
r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GFX,
1281
1281
GFX_11_0_0__SRCID__SDMA_TRAP,
1282
1282
&adev->sdma.trap_irq);
1283
1283
if (r)
···
1526
1526
}
1527
1527
1528
1528
switch (entry->client_id) {
1529
-
case SOC21_IH_CLIENTID_GFX:
1529
+
case SOC_V1_0_IH_CLIENTID_GFX:
1530
1530
switch (queue) {
1531
1531
case 0:
1532
1532
amdgpu_fence_process(&adev->sdma.instance[instances].ring);
+52
drivers/gpu/drm/amd/include/soc_v1_0_ih_clientid.h
+52
drivers/gpu/drm/amd/include/soc_v1_0_ih_clientid.h
···
1
+
/*
2
+
* Copyright 2025 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
#ifndef __SOC_V1_0_IH_CLIENTID_H__
24
+
#define __SOC_V1_0_IH_CLIENTID_H__
25
+
26
+
extern const char *soc_v1_0_ih_clientid_name[];
27
+
28
+
enum soc_v1_0_ih_clientid {
29
+
SOC_V1_0_IH_CLIENTID_IH = 0x00,
30
+
SOC_V1_0_IH_CLIENTID_ATHUB = 0x02,
31
+
SOC_V1_0_IH_CLIENTID_BIF = 0x03,
32
+
SOC_V1_0_IH_CLIENTID_RLC = 0x07,
33
+
SOC_V1_0_IH_CLIENTID_GFX = 0x0a,
34
+
SOC_V1_0_IH_CLIENTID_IMU = 0x0b,
35
+
SOC_V1_0_IH_CLIENTID_VCN1 = 0x0e,
36
+
SOC_V1_0_IH_CLIENTID_THM = 0x0f,
37
+
SOC_V1_0_IH_CLIENTID_VCN = 0x10,
38
+
SOC_V1_0_IH_CLIENTID_VMC = 0x12,
39
+
SOC_V1_0_IH_CLIENTID_GRBM_CP = 0x14,
40
+
SOC_V1_0_IH_CLIENTID_GC_AID = 0x15,
41
+
SOC_V1_0_IH_CLIENTID_ROM_SMUIO = 0x16,
42
+
SOC_V1_0_IH_CLIENTID_DF = 0x17,
43
+
SOC_V1_0_IH_CLIENTID_PWR = 0x19,
44
+
SOC_V1_0_IH_CLIENTID_LSDMA = 0x1a,
45
+
SOC_V1_0_IH_CLIENTID_GC_UTCL2 = 0x1b,
46
+
SOC_V1_0_IH_CLIENTID_nHT = 0X1c,
47
+
SOC_V1_0_IH_CLIENTID_MP0 = 0x1e,
48
+
SOC_V1_0_IH_CLIENTID_MP1 = 0x1f,
49
+
SOC_V1_0_IH_CLIENTID_MAX,
50
+
};
51
+
52
+
#endif