Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"A bigger batch than I anticipated this week, for two reasons:
- Some fallout on Davinci from board file -> DTB conversion, that
also includes a few longer-standing fixes (i.e. not recent
regressions).
- drivers/reset material that has been in linux-next for a while, but
didn't get sent to us until now for a variety of reasons
(maintainer out sick, holidays, etc). There's a functional
dependency in there such that one platform (Altera's SoCFPGA) won't
boot without one of the patches; instead of reverting the patch
that got merged, I looked at this set and decided it was small
enough that I'll pick it up anyway. If you disagree I can revisit
with a smaller set.
That being said, there's also a handful of the usual stuff:
- Fix for a crash on Armada 7K/8K when the kernel touches
PSCI-reserved memory
- Fix for PCIe reset on Macchiatobin (Armada 8K development board,
what this email is sent from in fact :)
- Enable a few new-merged modules for Amlogic in arm64 defconfig
- Error path fixes on Integrator
- Build fix for Renesas and Qualcomm
- Initialization fix for Renesas RZ/G2E
.. plus a few more fixlets"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits)
ARM: integrator: impd1: use struct_size() in devm_kzalloc()
qcom-scm: Include <linux/err.h> header
gpio: pl061: handle failed allocations
ARM: dts: kirkwood: Fix polarity of GPIO fan lines
arm64: dts: marvell: mcbin: fix PCIe reset signal
arm64: dts: marvell: armada-ap806: reserve PSCI area
ARM: dts: da850-lcdk: Correct the sound card name
ARM: dts: da850-lcdk: Correct the audio codec regulators
ARM: dts: da850-evm: Correct the sound card name
ARM: dts: da850-evm: Correct the audio codec regulators
ARM: davinci: omapl138-hawk: fix label names in GPIO lookup entries
ARM: davinci: dm644x-evm: fix label names in GPIO lookup entries
ARM: davinci: dm355-evm: fix label names in GPIO lookup entries
ARM: davinci: da850-evm: fix label names in GPIO lookup entries
ARM: davinci: da830-evm: fix label names in GPIO lookup entries
arm64: defconfig: enable modules for amlogic s400 sound card
reset: uniphier-glue: Add AHCI reset control support in glue layer
dt-bindings: reset: uniphier: Add AHCI core reset description
reset: uniphier-usb3: Rename to reset-uniphier-glue
dt-bindings: reset: uniphier: Replace the expression of USB3 with generic peripherals
...
+321
-93
+2
-1
Documentation/devicetree/bindings/reset/socfpga-reset.txt
+2
-1
Documentation/devicetree/bindings/reset/socfpga-reset.txt
···
1
1
Altera SOCFPGA Reset Manager
2
2
3
3
Required properties:
4
-
- compatible : "altr,rst-mgr"
4
+
- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)
5
+
"altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC
5
6
- reg : Should contain 1 register ranges(address and length)
6
7
- altr,modrst-offset : Should contain the offset of the first modrst register.
7
8
- #reset-cells: 1
+14
-11
Documentation/devicetree/bindings/reset/uniphier-reset.txt
+14
-11
Documentation/devicetree/bindings/reset/uniphier-reset.txt
···
120
120
};
121
121
122
122
123
-
USB3 core reset
124
-
---------------
123
+
Peripheral core reset in glue layer
124
+
-----------------------------------
125
125
126
-
USB3 core reset belongs to USB3 glue layer. Before using the core reset,
127
-
it is necessary to control the clocks and resets to enable this layer.
128
-
These clocks and resets should be described in each property.
126
+
Some peripheral core reset belongs to its own glue layer. Before using
127
+
this core reset, it is necessary to control the clocks and resets to enable
128
+
this layer. These clocks and resets should be described in each property.
129
129
130
130
Required properties:
131
131
- compatible: Should be
132
-
"socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC
133
-
"socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC
134
-
"socionext,uniphier-ld20-usb3-reset" - for LD20 SoC
135
-
"socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC
132
+
"socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
133
+
"socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
134
+
"socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
135
+
"socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
136
+
"socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
137
+
"socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI
138
+
"socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI
136
139
- #reset-cells: Should be 1.
137
140
- reg: Specifies offset and length of the register set for the device.
138
-
- clocks: A list of phandles to the clock gate for USB3 glue layer.
141
+
- clocks: A list of phandles to the clock gate for the glue layer.
139
142
According to the clock-names, appropriate clocks are required.
140
143
- clock-names: Should contain
141
144
"gio", "link" - for Pro4 SoC
142
145
"link" - for others
143
-
- resets: A list of phandles to the reset control for USB3 glue layer.
146
+
- resets: A list of phandles to the reset control for the glue layer.
144
147
According to the reset-names, appropriate resets are required.
145
148
- reset-names: Should contain
146
149
"gio", "link" - for Pro4 SoC
+26
-5
arch/arm/boot/dts/da850-evm.dts
+26
-5
arch/arm/boot/dts/da850-evm.dts
···
94
94
regulator-boot-on;
95
95
};
96
96
97
+
baseboard_3v3: fixedregulator-3v3 {
98
+
/* TPS73701DCQ */
99
+
compatible = "regulator-fixed";
100
+
regulator-name = "baseboard_3v3";
101
+
regulator-min-microvolt = <3300000>;
102
+
regulator-max-microvolt = <3300000>;
103
+
vin-supply = <&vbat>;
104
+
regulator-always-on;
105
+
regulator-boot-on;
106
+
};
107
+
108
+
baseboard_1v8: fixedregulator-1v8 {
109
+
/* TPS73701DCQ */
110
+
compatible = "regulator-fixed";
111
+
regulator-name = "baseboard_1v8";
112
+
regulator-min-microvolt = <1800000>;
113
+
regulator-max-microvolt = <1800000>;
114
+
vin-supply = <&vbat>;
115
+
regulator-always-on;
116
+
regulator-boot-on;
117
+
};
118
+
97
119
backlight_lcd: backlight-regulator {
98
120
compatible = "regulator-fixed";
99
121
regulator-name = "lcd_backlight_pwr";
···
127
105
128
106
sound {
129
107
compatible = "simple-audio-card";
130
-
simple-audio-card,name = "DA850/OMAP-L138 EVM";
108
+
simple-audio-card,name = "DA850-OMAPL138 EVM";
131
109
simple-audio-card,widgets =
132
110
"Line", "Line In",
133
111
"Line", "Line Out";
···
232
210
233
211
/* Regulators */
234
212
IOVDD-supply = <&vdcdc2_reg>;
235
-
/* Derived from VBAT: Baseboard 3.3V / 1.8V */
236
-
AVDD-supply = <&vbat>;
237
-
DRVDD-supply = <&vbat>;
238
-
DVDD-supply = <&vbat>;
213
+
AVDD-supply = <&baseboard_3v3>;
214
+
DRVDD-supply = <&baseboard_3v3>;
215
+
DVDD-supply = <&baseboard_1v8>;
239
216
};
240
217
tca6416: gpio@20 {
241
218
compatible = "ti,tca6416";
+37
-1
arch/arm/boot/dts/da850-lcdk.dts
+37
-1
arch/arm/boot/dts/da850-lcdk.dts
···
39
39
};
40
40
};
41
41
42
+
vcc_5vd: fixedregulator-vcc_5vd {
43
+
compatible = "regulator-fixed";
44
+
regulator-name = "vcc_5vd";
45
+
regulator-min-microvolt = <5000000>;
46
+
regulator-max-microvolt = <5000000>;
47
+
regulator-boot-on;
48
+
};
49
+
50
+
vcc_3v3d: fixedregulator-vcc_3v3d {
51
+
/* TPS650250 - VDCDC1 */
52
+
compatible = "regulator-fixed";
53
+
regulator-name = "vcc_3v3d";
54
+
regulator-min-microvolt = <3300000>;
55
+
regulator-max-microvolt = <3300000>;
56
+
vin-supply = <&vcc_5vd>;
57
+
regulator-always-on;
58
+
regulator-boot-on;
59
+
};
60
+
61
+
vcc_1v8d: fixedregulator-vcc_1v8d {
62
+
/* TPS650250 - VDCDC2 */
63
+
compatible = "regulator-fixed";
64
+
regulator-name = "vcc_1v8d";
65
+
regulator-min-microvolt = <1800000>;
66
+
regulator-max-microvolt = <1800000>;
67
+
vin-supply = <&vcc_5vd>;
68
+
regulator-always-on;
69
+
regulator-boot-on;
70
+
};
71
+
42
72
sound {
43
73
compatible = "simple-audio-card";
44
-
simple-audio-card,name = "DA850/OMAP-L138 LCDK";
74
+
simple-audio-card,name = "DA850-OMAPL138 LCDK";
45
75
simple-audio-card,widgets =
46
76
"Line", "Line In",
47
77
"Line", "Line Out";
···
251
221
compatible = "ti,tlv320aic3106";
252
222
reg = <0x18>;
253
223
status = "okay";
224
+
225
+
/* Regulators */
226
+
IOVDD-supply = <&vcc_3v3d>;
227
+
AVDD-supply = <&vcc_3v3d>;
228
+
DRVDD-supply = <&vcc_3v3d>;
229
+
DVDD-supply = <&vcc_1v8d>;
254
230
};
255
231
};
256
232
+2
-2
arch/arm/boot/dts/kirkwood-dnskw.dtsi
+2
-2
arch/arm/boot/dts/kirkwood-dnskw.dtsi
···
36
36
compatible = "gpio-fan";
37
37
pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
38
38
pinctrl-names = "default";
39
-
gpios = <&gpio1 14 GPIO_ACTIVE_LOW
40
-
&gpio1 13 GPIO_ACTIVE_LOW>;
39
+
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH
40
+
&gpio1 13 GPIO_ACTIVE_HIGH>;
41
41
gpio-fan,speed-map = <0 0
42
42
3000 1
43
43
6000 2>;
+2
-2
arch/arm/mach-davinci/board-da830-evm.c
+2
-2
arch/arm/mach-davinci/board-da830-evm.c
···
208
208
.dev_id = "da830-mmc.0",
209
209
.table = {
210
210
/* gpio chip 1 contains gpio range 32-63 */
211
-
GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_CD_PIN, "cd",
211
+
GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_CD_PIN, "cd",
212
212
GPIO_ACTIVE_LOW),
213
-
GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_WP_PIN, "wp",
213
+
GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_WP_PIN, "wp",
214
214
GPIO_ACTIVE_LOW),
215
215
},
216
216
};
+2
-2
arch/arm/mach-davinci/board-da850-evm.c
+2
-2
arch/arm/mach-davinci/board-da850-evm.c
···
805
805
.dev_id = "da830-mmc.0",
806
806
.table = {
807
807
/* gpio chip 2 contains gpio range 64-95 */
808
-
GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_CD_PIN, "cd",
808
+
GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_CD_PIN, "cd",
809
809
GPIO_ACTIVE_LOW),
810
-
GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_WP_PIN, "wp",
810
+
GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_WP_PIN, "wp",
811
811
GPIO_ACTIVE_HIGH),
812
812
},
813
813
};
+2
-2
arch/arm/mach-davinci/board-dm355-evm.c
+2
-2
arch/arm/mach-davinci/board-dm355-evm.c
···
117
117
static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
118
118
.dev_id = "i2c_davinci.1",
119
119
.table = {
120
-
GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SDA_PIN, "sda",
120
+
GPIO_LOOKUP("davinci_gpio", DM355_I2C_SDA_PIN, "sda",
121
121
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
122
-
GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SCL_PIN, "scl",
122
+
GPIO_LOOKUP("davinci_gpio", DM355_I2C_SCL_PIN, "scl",
123
123
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
124
124
},
125
125
};
+2
-2
arch/arm/mach-davinci/board-dm644x-evm.c
+2
-2
arch/arm/mach-davinci/board-dm644x-evm.c
···
660
660
static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
661
661
.dev_id = "i2c_davinci.1",
662
662
.table = {
663
-
GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SDA_PIN, "sda",
663
+
GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SDA_PIN, "sda",
664
664
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
665
-
GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SCL_PIN, "scl",
665
+
GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SCL_PIN, "scl",
666
666
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
667
667
},
668
668
};
+2
-2
arch/arm/mach-davinci/board-omapl138-hawk.c
+2
-2
arch/arm/mach-davinci/board-omapl138-hawk.c
···
134
134
static struct gpiod_lookup_table mmc_gpios_table = {
135
135
.dev_id = "da830-mmc.0",
136
136
.table = {
137
-
GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_CD_PIN, "cd",
137
+
GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_CD_PIN, "cd",
138
138
GPIO_ACTIVE_LOW),
139
-
GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_WP_PIN, "wp",
139
+
GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_WP_PIN, "wp",
140
140
GPIO_ACTIVE_LOW),
141
141
},
142
142
};
+6
-2
arch/arm/mach-integrator/impd1.c
+6
-2
arch/arm/mach-integrator/impd1.c
···
390
390
char *mmciname;
391
391
392
392
lookup = devm_kzalloc(&dev->dev,
393
-
sizeof(*lookup) + 3 * sizeof(struct gpiod_lookup),
393
+
struct_size(lookup, table, 3),
394
394
GFP_KERNEL);
395
395
chipname = devm_kstrdup(&dev->dev, devname, GFP_KERNEL);
396
-
mmciname = kasprintf(GFP_KERNEL, "lm%x:00700", dev->id);
396
+
mmciname = devm_kasprintf(&dev->dev, GFP_KERNEL,
397
+
"lm%x:00700", dev->id);
398
+
if (!lookup || !chipname || !mmciname)
399
+
return -ENOMEM;
400
+
397
401
lookup->dev_id = mmciname;
398
402
/*
399
403
* Offsets on GPIO block 1:
+4
arch/arm/mach-socfpga/socfpga.c
+4
arch/arm/mach-socfpga/socfpga.c
···
32
32
void __iomem *sdr_ctl_base_addr;
33
33
unsigned long socfpga_cpu1start_addr;
34
34
35
+
extern void __init socfpga_reset_init(void);
36
+
35
37
static void __init socfpga_sysmgr_init(void)
36
38
{
37
39
struct device_node *np;
···
66
64
67
65
if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
68
66
socfpga_init_ocram_ecc();
67
+
socfpga_reset_init();
69
68
}
70
69
71
70
static void __init socfpga_arria10_init_irq(void)
···
77
74
socfpga_init_arria10_l2_ecc();
78
75
if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
79
76
socfpga_init_arria10_ocram_ecc();
77
+
socfpga_reset_init();
80
78
}
81
79
82
80
static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
+1
-1
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+1
-1
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+17
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+17
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
···
28
28
method = "smc";
29
29
};
30
30
31
+
reserved-memory {
32
+
#address-cells = <2>;
33
+
#size-cells = <2>;
34
+
ranges;
35
+
36
+
/*
37
+
* This area matches the mapping done with a
38
+
* mainline U-Boot, and should be updated by the
39
+
* bootloader.
40
+
*/
41
+
42
+
psci-area@4000000 {
43
+
reg = <0x0 0x4000000 0x0 0x200000>;
44
+
no-map;
45
+
};
46
+
};
47
+
31
48
ap806 {
32
49
#address-cells = <2>;
33
50
#size-cells = <2>;
+4
arch/arm64/configs/defconfig
+4
arch/arm64/configs/defconfig
···
506
506
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
507
507
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
508
508
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
509
+
CONFIG_SND_MESON_AXG_SOUND_CARD=m
509
510
CONFIG_SND_SOC_SAMSUNG=y
510
511
CONFIG_SND_SOC_RCAR=m
511
512
CONFIG_SND_SOC_AK4613=m
512
513
CONFIG_SND_SIMPLE_CARD=m
513
514
CONFIG_SND_AUDIO_GRAPH_CARD=m
515
+
CONFIG_SND_SOC_ES7134=m
516
+
CONFIG_SND_SOC_ES7241=m
517
+
CONFIG_SND_SOC_TAS571X=m
514
518
CONFIG_I2C_HID=m
515
519
CONFIG_USB=y
516
520
CONFIG_USB_OTG=y
+14
-6
drivers/reset/Kconfig
+14
-6
drivers/reset/Kconfig
···
109
109
110
110
config RESET_SIMPLE
111
111
bool "Simple Reset Controller Driver" if COMPILE_TEST
112
-
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
112
+
default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
113
113
help
114
114
This enables a simple reset controller driver for reset lines that
115
115
that can be asserted and deasserted by toggling bits in a contiguous,
···
127
127
default MACH_STM32MP157
128
128
help
129
129
This enables the RCC reset controller driver for STM32 MPUs.
130
+
131
+
config RESET_SOCFPGA
132
+
bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
133
+
default ARCH_SOCFPGA
134
+
select RESET_SIMPLE
135
+
help
136
+
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
137
+
driver gets initialized early during platform init calls.
130
138
131
139
config RESET_SUNXI
132
140
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
···
171
163
Say Y if you want to control reset signals provided by System Control
172
164
block, Media I/O block, Peripheral Block.
173
165
174
-
config RESET_UNIPHIER_USB3
175
-
tristate "USB3 reset driver for UniPhier SoCs"
166
+
config RESET_UNIPHIER_GLUE
167
+
tristate "Reset driver in glue layer for UniPhier SoCs"
176
168
depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
177
169
default ARCH_UNIPHIER
178
170
select RESET_SIMPLE
179
171
help
180
-
Support for the USB3 core reset on UniPhier SoCs.
181
-
Say Y if you want to control reset signals provided by
182
-
USB3 glue layer.
172
+
Support for peripheral core reset included in its own glue layer
173
+
on UniPhier SoCs. Say Y if you want to control reset signals
174
+
provided by the glue layer.
183
175
184
176
config RESET_ZYNQ
185
177
bool "ZYNQ Reset Driver" if COMPILE_TEST
+2
-1
drivers/reset/Makefile
+2
-1
drivers/reset/Makefile
···
19
19
obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
20
20
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
21
21
obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
22
+
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
22
23
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
23
24
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
24
25
obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
25
26
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
26
-
obj-$(CONFIG_RESET_UNIPHIER_USB3) += reset-uniphier-usb3.o
27
+
obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
27
28
obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
28
29
+42
drivers/reset/core.c
+42
drivers/reset/core.c
···
795
795
return rstc;
796
796
}
797
797
EXPORT_SYMBOL_GPL(devm_reset_control_array_get);
798
+
799
+
static int reset_control_get_count_from_lookup(struct device *dev)
800
+
{
801
+
const struct reset_control_lookup *lookup;
802
+
const char *dev_id;
803
+
int count = 0;
804
+
805
+
if (!dev)
806
+
return -EINVAL;
807
+
808
+
dev_id = dev_name(dev);
809
+
mutex_lock(&reset_lookup_mutex);
810
+
811
+
list_for_each_entry(lookup, &reset_lookup_list, list) {
812
+
if (!strcmp(lookup->dev_id, dev_id))
813
+
count++;
814
+
}
815
+
816
+
mutex_unlock(&reset_lookup_mutex);
817
+
818
+
if (count == 0)
819
+
count = -ENOENT;
820
+
821
+
return count;
822
+
}
823
+
824
+
/**
825
+
* reset_control_get_count - Count number of resets available with a device
826
+
*
827
+
* @dev: device for which to return the number of resets
828
+
*
829
+
* Returns positive reset count on success, or error number on failure and
830
+
* on count being zero.
831
+
*/
832
+
int reset_control_get_count(struct device *dev)
833
+
{
834
+
if (dev->of_node)
835
+
return of_reset_control_get_count(dev->of_node);
836
+
837
+
return reset_control_get_count_from_lookup(dev);
838
+
}
839
+
EXPORT_SYMBOL_GPL(reset_control_get_count);
+1
drivers/reset/reset-hsdk.c
+1
drivers/reset/reset-hsdk.c
+3
-10
drivers/reset/reset-simple.c
+3
-10
drivers/reset/reset-simple.c
···
109
109
#define SOCFPGA_NR_BANKS 8
110
110
111
111
static const struct reset_simple_devdata reset_simple_socfpga = {
112
-
.reg_offset = 0x10,
112
+
.reg_offset = 0x20,
113
113
.nr_resets = SOCFPGA_NR_BANKS * 32,
114
114
.status_active_low = true,
115
115
};
···
120
120
};
121
121
122
122
static const struct of_device_id reset_simple_dt_ids[] = {
123
-
{ .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga },
123
+
{ .compatible = "altr,stratix10-rst-mgr",
124
+
.data = &reset_simple_socfpga },
124
125
{ .compatible = "st,stm32-rcc", },
125
126
{ .compatible = "allwinner,sun6i-a31-clock-reset",
126
127
.data = &reset_simple_active_low },
···
165
164
data->rcdev.nr_resets = devdata->nr_resets;
166
165
data->active_low = devdata->active_low;
167
166
data->status_active_low = devdata->status_active_low;
168
-
}
169
-
170
-
if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
171
-
of_property_read_u32(dev->of_node, "altr,modrst-offset",
172
-
®_offset)) {
173
-
dev_warn(dev,
174
-
"missing altr,modrst-offset property, assuming 0x%x!\n",
175
-
reg_offset);
176
167
}
177
168
178
169
data->membase += reg_offset;
+88
drivers/reset/reset-socfpga.c
+88
drivers/reset/reset-socfpga.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2018, Intel Corporation
4
+
* Copied from reset-sunxi.c
5
+
*/
6
+
7
+
#include <linux/err.h>
8
+
#include <linux/io.h>
9
+
#include <linux/init.h>
10
+
#include <linux/of.h>
11
+
#include <linux/of_address.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/reset-controller.h>
14
+
#include <linux/slab.h>
15
+
#include <linux/spinlock.h>
16
+
#include <linux/types.h>
17
+
18
+
#include "reset-simple.h"
19
+
20
+
#define SOCFPGA_NR_BANKS 8
21
+
void __init socfpga_reset_init(void);
22
+
23
+
static int a10_reset_init(struct device_node *np)
24
+
{
25
+
struct reset_simple_data *data;
26
+
struct resource res;
27
+
resource_size_t size;
28
+
int ret;
29
+
u32 reg_offset = 0x10;
30
+
31
+
data = kzalloc(sizeof(*data), GFP_KERNEL);
32
+
if (!data)
33
+
return -ENOMEM;
34
+
35
+
ret = of_address_to_resource(np, 0, &res);
36
+
if (ret)
37
+
goto err_alloc;
38
+
39
+
size = resource_size(&res);
40
+
if (!request_mem_region(res.start, size, np->name)) {
41
+
ret = -EBUSY;
42
+
goto err_alloc;
43
+
}
44
+
45
+
data->membase = ioremap(res.start, size);
46
+
if (!data->membase) {
47
+
ret = -ENOMEM;
48
+
goto err_alloc;
49
+
}
50
+
51
+
if (of_property_read_u32(np, "altr,modrst-offset", ®_offset))
52
+
pr_warn("missing altr,modrst-offset property, assuming 0x10\n");
53
+
data->membase += reg_offset;
54
+
55
+
spin_lock_init(&data->lock);
56
+
57
+
data->rcdev.owner = THIS_MODULE;
58
+
data->rcdev.nr_resets = SOCFPGA_NR_BANKS * 32;
59
+
data->rcdev.ops = &reset_simple_ops;
60
+
data->rcdev.of_node = np;
61
+
data->status_active_low = true;
62
+
63
+
return reset_controller_register(&data->rcdev);
64
+
65
+
err_alloc:
66
+
kfree(data);
67
+
return ret;
68
+
};
69
+
70
+
/*
71
+
* These are the reset controller we need to initialize early on in
72
+
* our system, before we can even think of using a regular device
73
+
* driver for it.
74
+
* The controllers that we can register through the regular device
75
+
* model are handled by the simple reset driver directly.
76
+
*/
77
+
static const struct of_device_id socfpga_early_reset_dt_ids[] __initconst = {
78
+
{ .compatible = "altr,rst-mgr", },
79
+
{ /* sentinel */ },
80
+
};
81
+
82
+
void __init socfpga_reset_init(void)
83
+
{
84
+
struct device_node *np;
85
+
86
+
for_each_matching_node(np, socfpga_early_reset_dt_ids)
87
+
a10_reset_init(np);
88
+
}
+31
-19
drivers/reset/reset-uniphier-usb3.c
drivers/reset/reset-uniphier-glue.c
+31
-19
drivers/reset/reset-uniphier-usb3.c
drivers/reset/reset-uniphier-glue.c
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
//
3
-
// reset-uniphier-usb3.c - USB3 reset driver for UniPhier
3
+
// reset-uniphier-glue.c - Glue layer reset driver for UniPhier
4
4
// Copyright 2018 Socionext Inc.
5
5
// Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
6
6
···
15
15
#define MAX_CLKS 2
16
16
#define MAX_RSTS 2
17
17
18
-
struct uniphier_usb3_reset_soc_data {
18
+
struct uniphier_glue_reset_soc_data {
19
19
int nclks;
20
20
const char * const *clock_names;
21
21
int nrsts;
22
22
const char * const *reset_names;
23
23
};
24
24
25
-
struct uniphier_usb3_reset_priv {
25
+
struct uniphier_glue_reset_priv {
26
26
struct clk_bulk_data clk[MAX_CLKS];
27
27
struct reset_control *rst[MAX_RSTS];
28
28
struct reset_simple_data rdata;
29
-
const struct uniphier_usb3_reset_soc_data *data;
29
+
const struct uniphier_glue_reset_soc_data *data;
30
30
};
31
31
32
-
static int uniphier_usb3_reset_probe(struct platform_device *pdev)
32
+
static int uniphier_glue_reset_probe(struct platform_device *pdev)
33
33
{
34
34
struct device *dev = &pdev->dev;
35
-
struct uniphier_usb3_reset_priv *priv;
35
+
struct uniphier_glue_reset_priv *priv;
36
36
struct resource *res;
37
37
resource_size_t size;
38
38
const char *name;
···
100
100
return ret;
101
101
}
102
102
103
-
static int uniphier_usb3_reset_remove(struct platform_device *pdev)
103
+
static int uniphier_glue_reset_remove(struct platform_device *pdev)
104
104
{
105
-
struct uniphier_usb3_reset_priv *priv = platform_get_drvdata(pdev);
105
+
struct uniphier_glue_reset_priv *priv = platform_get_drvdata(pdev);
106
106
int i;
107
107
108
108
for (i = 0; i < priv->data->nrsts; i++)
···
117
117
"gio", "link",
118
118
};
119
119
120
-
static const struct uniphier_usb3_reset_soc_data uniphier_pro4_data = {
120
+
static const struct uniphier_glue_reset_soc_data uniphier_pro4_data = {
121
121
.nclks = ARRAY_SIZE(uniphier_pro4_clock_reset_names),
122
122
.clock_names = uniphier_pro4_clock_reset_names,
123
123
.nrsts = ARRAY_SIZE(uniphier_pro4_clock_reset_names),
···
128
128
"link",
129
129
};
130
130
131
-
static const struct uniphier_usb3_reset_soc_data uniphier_pxs2_data = {
131
+
static const struct uniphier_glue_reset_soc_data uniphier_pxs2_data = {
132
132
.nclks = ARRAY_SIZE(uniphier_pxs2_clock_reset_names),
133
133
.clock_names = uniphier_pxs2_clock_reset_names,
134
134
.nrsts = ARRAY_SIZE(uniphier_pxs2_clock_reset_names),
135
135
.reset_names = uniphier_pxs2_clock_reset_names,
136
136
};
137
137
138
-
static const struct of_device_id uniphier_usb3_reset_match[] = {
138
+
static const struct of_device_id uniphier_glue_reset_match[] = {
139
139
{
140
140
.compatible = "socionext,uniphier-pro4-usb3-reset",
141
141
.data = &uniphier_pro4_data,
···
152
152
.compatible = "socionext,uniphier-pxs3-usb3-reset",
153
153
.data = &uniphier_pxs2_data,
154
154
},
155
+
{
156
+
.compatible = "socionext,uniphier-pro4-ahci-reset",
157
+
.data = &uniphier_pro4_data,
158
+
},
159
+
{
160
+
.compatible = "socionext,uniphier-pxs2-ahci-reset",
161
+
.data = &uniphier_pxs2_data,
162
+
},
163
+
{
164
+
.compatible = "socionext,uniphier-pxs3-ahci-reset",
165
+
.data = &uniphier_pxs2_data,
166
+
},
155
167
{ /* Sentinel */ }
156
168
};
157
-
MODULE_DEVICE_TABLE(of, uniphier_usb3_reset_match);
169
+
MODULE_DEVICE_TABLE(of, uniphier_glue_reset_match);
158
170
159
-
static struct platform_driver uniphier_usb3_reset_driver = {
160
-
.probe = uniphier_usb3_reset_probe,
161
-
.remove = uniphier_usb3_reset_remove,
171
+
static struct platform_driver uniphier_glue_reset_driver = {
172
+
.probe = uniphier_glue_reset_probe,
173
+
.remove = uniphier_glue_reset_remove,
162
174
.driver = {
163
-
.name = "uniphier-usb3-reset",
164
-
.of_match_table = uniphier_usb3_reset_match,
175
+
.name = "uniphier-glue-reset",
176
+
.of_match_table = uniphier_glue_reset_match,
165
177
},
166
178
};
167
-
module_platform_driver(uniphier_usb3_reset_driver);
179
+
module_platform_driver(uniphier_glue_reset_driver);
168
180
169
181
MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
170
-
MODULE_DESCRIPTION("UniPhier USB3 Reset Driver");
182
+
MODULE_DESCRIPTION("UniPhier Glue layer reset driver");
171
183
MODULE_LICENSE("GPL");
+1
-1
drivers/soc/renesas/Kconfig
+1
-1
drivers/soc/renesas/Kconfig
+4
-19
drivers/soc/renesas/r8a774c0-sysc.c
+4
-19
drivers/soc/renesas/r8a774c0-sysc.c
···
28
28
{ "3dg-b", 0x100, 1, R8A774C0_PD_3DG_B, R8A774C0_PD_3DG_A },
29
29
};
30
30
31
-
static void __init rcar_sysc_fix_parent(struct rcar_sysc_area *areas,
32
-
unsigned int num_areas, u8 id,
33
-
int new_parent)
34
-
{
35
-
unsigned int i;
36
-
37
-
for (i = 0; i < num_areas; i++)
38
-
if (areas[i].isr_bit == id) {
39
-
areas[i].parent = new_parent;
40
-
return;
41
-
}
42
-
}
43
-
44
31
/* Fixups for RZ/G2E ES1.0 revision */
45
32
static const struct soc_device_attribute r8a774c0[] __initconst = {
46
33
{ .soc_id = "r8a774c0", .revision = "ES1.0" },
···
37
50
static int __init r8a774c0_sysc_init(void)
38
51
{
39
52
if (soc_device_match(r8a774c0)) {
40
-
rcar_sysc_fix_parent(r8a774c0_areas,
41
-
ARRAY_SIZE(r8a774c0_areas),
42
-
R8A774C0_PD_3DG_A, R8A774C0_PD_3DG_B);
43
-
rcar_sysc_fix_parent(r8a774c0_areas,
44
-
ARRAY_SIZE(r8a774c0_areas),
45
-
R8A774C0_PD_3DG_B, R8A774C0_PD_ALWAYS_ON);
53
+
/* Fix incorrect 3DG hierarchy */
54
+
swap(r8a774c0_areas[6], r8a774c0_areas[7]);
55
+
r8a774c0_areas[6].parent = R8A774C0_PD_ALWAYS_ON;
56
+
r8a774c0_areas[7].parent = R8A774C0_PD_3DG_B;
46
57
}
47
58
48
59
return 0;
+1
include/linux/qcom_scm.h
+1
include/linux/qcom_scm.h
+11
-4
include/linux/reset.h
+11
-4
include/linux/reset.h
···
32
32
struct reset_control *of_reset_control_array_get(struct device_node *np,
33
33
bool shared, bool optional);
34
34
35
+
int reset_control_get_count(struct device *dev);
36
+
35
37
#else
36
38
37
39
static inline int reset_control_reset(struct reset_control *rstc)
···
99
97
return optional ? NULL : ERR_PTR(-ENOTSUPP);
100
98
}
101
99
100
+
static inline int reset_control_get_count(struct device *dev)
101
+
{
102
+
return -ENOENT;
103
+
}
104
+
102
105
#endif /* CONFIG_RESET_CONTROLLER */
103
106
104
107
static inline int __must_check device_reset(struct device *dev)
···
145
138
*
146
139
* Returns a struct reset_control or IS_ERR() condition containing errno.
147
140
* This function is intended for use with reset-controls which are shared
148
-
* between hardware-blocks.
141
+
* between hardware blocks.
149
142
*
150
143
* When a reset-control is shared, the behavior of reset_control_assert /
151
144
* deassert is changed, the reset-core will keep track of a deassert_count
···
194
187
}
195
188
196
189
/**
197
-
* of_reset_control_get_shared - Lookup and obtain an shared reference
190
+
* of_reset_control_get_shared - Lookup and obtain a shared reference
198
191
* to a reset controller.
199
192
* @node: device to be reset by the controller
200
193
* @id: reset line name
···
236
229
}
237
230
238
231
/**
239
-
* of_reset_control_get_shared_by_index - Lookup and obtain an shared
232
+
* of_reset_control_get_shared_by_index - Lookup and obtain a shared
240
233
* reference to a reset controller
241
234
* by index.
242
235
* @node: device to be reset by the controller
···
329
322
330
323
/**
331
324
* devm_reset_control_get_shared_by_index - resource managed
332
-
* reset_control_get_shared
325
+
* reset_control_get_shared
333
326
* @dev: device to be reset by the controller
334
327
* @index: index of the reset controller
335
328
*